From 983baf29115db185c7c324a9553d9137107855db Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Mon, 20 Jul 2020 10:49:06 +0200 Subject: [PATCH 1/2] Add a new debug target for the atlys board (see timvideos/litex-buildenv#481) --- targets/atlys/debug.py | 65 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100755 targets/atlys/debug.py diff --git a/targets/atlys/debug.py b/targets/atlys/debug.py new file mode 100755 index 000000000..813cf12cc --- /dev/null +++ b/targets/atlys/debug.py @@ -0,0 +1,65 @@ +from litex.soc.cores import uart +from litescope import LiteScopeAnalyzer +from .base import BaseSoC + +# Connection Overview: +# +# |---> LiteScope +# HOST <--> UARTWishboneBridge <---|---> Crossover UART +# |---> CPU Debug Interface +# +# Note: The CPU Debug Interface is only available +# if your CPU_VARIANT includes "debug" +# +# There are currently two ways to connect to your UARTWishboneBridge: +# 1. Litex Server: +# Usage: litex_server --uart --uart-port /dev/ttyXXX +# - Features: +# - LiteScope: (todo) +# - Crossover UART: +# - cd into build/[target]/test/ +# - start litex_crossover_uart +# - connect to /dev/pts/XXX (e.g minicom -D /dev/pts/XXX) +# - CPU Debug Interface: (not supported) +# 2. Wishbone Tool (https://github.com/litex-hub/wishbone-utils) +# - Features: +# - LiteScope: (not supported) +# - Crossover UART: +# wishbone-tool -s terminal --csr-csv build/[target]/test/csr.csv +# - CPU Debug Interface: +# - wishbone-tool -s gdb --csr-csv build/[target]/test/csr.csv +# - start gdb +# - issue: target remote :1234 + +class DebugSoC(BaseSoC): + + def __init__(self, platform, *args, **kwargs): + + # Use the crossover uart that is able to connect over the uart bridge + kwargs['uart_name']="crossover" + + BaseSoC.__init__(self, platform, *args, **kwargs) + + #Add the uart bridge (you may adapt the baudrate e.g 500000, 921600) + self.submodules.uartbone = uart.UARTWishboneBridge( + pads = self.platform.request("serial"), + clk_freq = self.sys_clk_freq, + baudrate = 115200) + self.bus.add_master(name="uartbone", master=self.uartbone.wishbone) + + #add LitexScope + analyzer_signals = [ + self.ddrphy.dfi, + self.cpu.ibus.cyc, + self.cpu.ibus.stb + ] + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, + depth = 2048, + clock_domain = "sys") + self.add_csr("analyzer") + + # Generate the configuration file for the LiteScope client + def do_exit(self, vns, filename="test/analyzer.csv"): + self.analyzer.export_csv(vns, filename) + +SoC = DebugSoC From f07b421331143141e045057abccd5016f33ab318 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Wed, 22 Jul 2020 13:40:17 +0200 Subject: [PATCH 2/2] Update the debug target - More detailed connection overview - Tested/fixed all tool parameters --- targets/atlys/debug.py | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/targets/atlys/debug.py b/targets/atlys/debug.py index 813cf12cc..b6a8e8e50 100755 --- a/targets/atlys/debug.py +++ b/targets/atlys/debug.py @@ -4,32 +4,48 @@ # Connection Overview: # -# |---> LiteScope -# HOST <--> UARTWishboneBridge <---|---> Crossover UART -# |---> CPU Debug Interface -# -# Note: The CPU Debug Interface is only available -# if your CPU_VARIANT includes "debug" +# FPGA: +# |--> LiteScope +# --SERIAL--> UARTWishboneBridge <--WISHBONE-BUS--+--> Crossover UART +# | |--> CPU Debug Interface +# | +# | Host: +# | |-> LiteScope +# | |---> litex_server <--TCP-(ETHERBONE)--+-> litex_crossover_uart -> terminal +# | | |-> wishbone-tool +# | | |-> any custom python client that writes/reads any address +# ^-----or +# | |-> terminal +# |--> wishbone-tool <-------------------+-> gdb +# |-> client that writes/reads any address +# +# See also TBD +# +# Note: The CPU Debug Interface is only available +# if your CPU_VARIANT includes "debug". +# +# Note: You can run multiple litex_server clients or +# wishbone-tool clients at the same time. # # There are currently two ways to connect to your UARTWishboneBridge: # 1. Litex Server: # Usage: litex_server --uart --uart-port /dev/ttyXXX # - Features: -# - LiteScope: (todo) +# - LiteScope: (TBD) # - Crossover UART: # - cd into build/[target]/test/ # - start litex_crossover_uart # - connect to /dev/pts/XXX (e.g minicom -D /dev/pts/XXX) # - CPU Debug Interface: (not supported) +# - Wishbone-tool: wishbone-tool --ethernet-host 127.0.0.1 --ethernet-tcp # 2. Wishbone Tool (https://github.com/litex-hub/wishbone-utils) # - Features: # - LiteScope: (not supported) # - Crossover UART: -# wishbone-tool -s terminal --csr-csv build/[target]/test/csr.csv +# wishbone-tool --serial /dev/ttyXXX -s terminal --csr-csv build/[target]/test/csr.csv # - CPU Debug Interface: -# - wishbone-tool -s gdb --csr-csv build/[target]/test/csr.csv -# - start gdb -# - issue: target remote :1234 +# - wishbone-tool --serial /dev/ttyXXX -s gdb --csr-csv build/[target]/test/csr.csv +# - start gdb: gdb -ex 'target remote :3333' class DebugSoC(BaseSoC):