diff --git a/src/DRAMPower/DRAMPower/command/Command.h b/src/DRAMPower/DRAMPower/command/Command.h
index 8511cd6e..be27a36d 100644
--- a/src/DRAMPower/DRAMPower/command/Command.h
+++ b/src/DRAMPower/DRAMPower/command/Command.h
@@ -33,19 +33,19 @@ class Command {
 public:
     Command() = default;
 	Command(timestamp_t timestamp, CmdType type, TargetCoordinate targetCoord = {}, const uint8_t * data = nullptr, std::size_t sz_bits = 0)
-		: type(type)
+        : timestamp(timestamp)
+		, type(type)
 		, targetCoordinate(targetCoord)
-        , timestamp(timestamp)
 		, data(data)
 		, sz_bits(sz_bits)
 	{};
 
 public:
+    timestamp_t timestamp = 0;
+    CmdType type;
     TargetCoordinate targetCoordinate;
 
-    CmdType type;
 
-    timestamp_t timestamp = 0;
     const uint8_t * data = 0x00; // ToDo: buffer{ptr, sz} / TLM Standard
 	std::size_t sz_bits;
     //uint64_t burstLength;
diff --git a/src/DRAMPower/DRAMPower/command/Pattern.h b/src/DRAMPower/DRAMPower/command/Pattern.h
index d71a9409..b77ce47e 100644
--- a/src/DRAMPower/DRAMPower/command/Pattern.h
+++ b/src/DRAMPower/DRAMPower/command/Pattern.h
@@ -7,6 +7,7 @@
 #include <cassert>
 #include <unordered_map>
 #include <vector>
+#include <limits.h>
 
 namespace DRAMPower {
 namespace pattern_descriptor {
@@ -135,11 +136,12 @@ inline bool applyBitSpec(
         std::bitset<32> bank_group_bits(cmd.targetCoordinate.bankGroup);
 
         std::size_t n = pattern.size() - 1;
+        static_assert(std::numeric_limits<decltype(n)>::is_signed == false, "std::size_t must be unsigned");
 
         assert(n < 64);
 
         for (const auto descriptor : pattern) {
-            assert(n >= 0);
+            // assert(n >= 0); // std::size_t is unsigned
 
             switch (descriptor) {
             case H:
diff --git a/src/DRAMPower/DRAMPower/data/energy.h b/src/DRAMPower/DRAMPower/data/energy.h
index 75c76e03..68347da8 100644
--- a/src/DRAMPower/DRAMPower/data/energy.h
+++ b/src/DRAMPower/DRAMPower/data/energy.h
@@ -59,7 +59,7 @@ struct energy_t
 	std::vector<energy_info_t> bank_energy;
 	energy_info_t total_energy(); // TODO rename
 	void to_json(json_t &j) const;
-	constexpr inline const char * const get_Bank_energy_keyword() const
+	constexpr inline const char * get_Bank_energy_keyword() const
 	{
 		return "BankEnergy";
 	}
diff --git a/src/DRAMPower/DRAMPower/dram/dram_base.h b/src/DRAMPower/DRAMPower/dram/dram_base.h
index f112d319..87cc4630 100644
--- a/src/DRAMPower/DRAMPower/dram/dram_base.h
+++ b/src/DRAMPower/DRAMPower/dram/dram_base.h
@@ -31,19 +31,20 @@ class dram_base {
 
 public:
     commandCount_t commandCount;
-protected:
-    uint64_t lastPattern;
-    PatternEncoder encoder;
 private:
     commandRouter_t commandRouter;
     commandPatternMap_t commandPatternMap;
+protected:
+    PatternEncoder encoder;
+    uint64_t lastPattern;
+private:
     implicitCommandList_t implicitCommandList;
     timestamp_t last_command_time;
 
 public:
     dram_base(PatternEncoderOverrides encoderoverrides)
         : commandCount(static_cast<std::size_t>(CommandEnum::COUNT), 0)
-        , commandRouter(static_cast<std::size_t>(CommandEnum::COUNT), [](const Command& cmd) {})
+        , commandRouter(static_cast<std::size_t>(CommandEnum::COUNT), [](const Command&) {})
         , commandPatternMap(static_cast<std::size_t>(CommandEnum::COUNT), commandPattern_t {})
         , encoder(encoderoverrides)
         , lastPattern(0)
@@ -98,33 +99,33 @@ class dram_base {
             [](const auto& lhs, const auto& rhs) { return lhs.first < rhs.first; });
 
         implicitCommandList.emplace(upper, entry);
-    };
+    }
 
     template <CommandEnum cmd, typename Func>
     void routeCommand(Func&& func)
     {
         assert(commandRouter.size() > static_cast<std::size_t>(cmd));
         this->commandRouter[static_cast<std::size_t>(cmd)] = func;
-    };
+    }
 
     template <CommandEnum cmd_type>
     void registerPattern(std::initializer_list<pattern_descriptor::t> pattern)
     {
         this->commandPatternMap[static_cast<std::size_t>(cmd_type)] = commandPattern_t(pattern);
-    };
+    }
 
     template <CommandEnum cmd_type>
     void registerPattern(const commandPattern_t &pattern)
     {
         this->commandPatternMap[static_cast<std::size_t>(cmd_type)] = pattern;
-    };
+    }
 
     const commandPattern_t& getPattern(CmdType cmd_type)
     {
         return this->commandPatternMap[static_cast<std::size_t>(cmd_type)];
-    };
+    }
 
-    const std::size_t implicitCommandCount() const { return this->implicitCommandList.size(); };
+    std::size_t implicitCommandCount() const { return this->implicitCommandList.size(); };
 
     void processImplicitCommandQueue(timestamp_t timestamp)
     {
diff --git a/src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.h b/src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.h
index ef2f5207..6d694d77 100644
--- a/src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.h
+++ b/src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.h
@@ -77,8 +77,8 @@ class MemSpecDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecDDR4>
 
     uint64_t timeToCompletion(CmdType type) override;
 
-	unsigned numberOfBankGroups;
-	unsigned numberOfRanks;
+	uint64_t numberOfBankGroups;
+	uint64_t numberOfRanks;
 
 	double vddq;
 
diff --git a/src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.h b/src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.h
index e42014cf..225beec6 100644
--- a/src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.h
+++ b/src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.h
@@ -38,9 +38,9 @@ namespace DRAMPower {
         uint64_t timeToCompletion(CmdType type) override;
 
 
-        unsigned numberOfBankGroups;
-        unsigned banksPerGroup;
-        unsigned numberOfRanks;
+        uint64_t numberOfBankGroups;
+        uint64_t banksPerGroup;
+        uint64_t numberOfRanks;
 
         double vddq;
 
@@ -94,9 +94,9 @@ namespace DRAMPower {
         };
 
         struct DataRateSpec {
-            uint32_t commandBusRate;
-            uint32_t dataBusRate;
-            uint32_t dqsBusRate;
+            uint64_t commandBusRate;
+            uint64_t dataBusRate;
+            uint64_t dqsBusRate;
         };
 
         struct BankWiseParams
diff --git a/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.h b/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.h
index 0e7b1f98..0fcd8c1f 100644
--- a/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.h
+++ b/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.h
@@ -37,9 +37,9 @@ class MemSpecLPDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecLPDDR4>
 	~MemSpecLPDDR4() = default;
 	uint64_t timeToCompletion(CmdType type) override;
 
-    unsigned numberOfBankGroups;
-    unsigned banksPerGroup;
-    unsigned numberOfRanks;
+    uint64_t numberOfBankGroups;
+    uint64_t banksPerGroup;
+    uint64_t numberOfRanks;
 
 	double vddq;
 
@@ -110,7 +110,7 @@ class MemSpecLPDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecLPDDR4>
 		// ACT Standby power factor
 		double bwPowerFactRho;
 		// Self-Refresh power factor
-		uint64_t bwPowerFactSigma;
+		double bwPowerFactSigma;
 		// Whether PASR is enabled ( true : enabled )
 		bool flgPASR;
 		// PASR mode utilized (int 0-7)
diff --git a/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.h b/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.h
index 4e854592..791c1656 100644
--- a/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.h
+++ b/src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.h
@@ -42,9 +42,9 @@ namespace DRAMPower {
         uint64_t timeToCompletion(CmdType type) override;
 
 
-        unsigned numberOfBankGroups;
-        unsigned banksPerGroup;
-        unsigned numberOfRanks;
+        uint64_t numberOfBankGroups;
+        uint64_t banksPerGroup;
+        uint64_t numberOfRanks;
         std::size_t perTwoBankOffset = 8;
         BankArchitectureMode bank_arch;
         bool wckAlwaysOnMode;
diff --git a/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.cpp b/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.cpp
index f96c5cf1..b15c65bc 100644
--- a/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.cpp
+++ b/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.cpp
@@ -9,8 +9,12 @@
 namespace DRAMPower {
 
     DDR4::DDR4(const MemSpecDDR4 &memSpec)
-		: memSpec(memSpec)
-		, ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks})
+        : dram_base<CmdType>({
+            {pattern_descriptor::V, PatternEncoderBitSpec::H},
+            {pattern_descriptor::X, PatternEncoderBitSpec::H},
+          })
+        , memSpec(memSpec)
+        , ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks})
         , readBus(
             memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
              util::Bus::BusIdlePatternSpec::H, util::Bus::BusInitPatternSpec::H
@@ -21,19 +25,15 @@ namespace DRAMPower {
         )
         , cmdBusWidth(27)
         , cmdBusInitPattern((1<<cmdBusWidth)-1)
+        , readDQS_(2, true)
+        , writeDQS_(2, true)
         , commandBus(
             cmdBusWidth, 1,
             util::Bus::BusIdlePatternSpec::H,
             util::Bus::burst_t(cmdBusWidth, cmdBusInitPattern)
         )
-        , readDQS_(2, true)
-        , writeDQS_(2, true)
         , prepostambleReadMinTccd(memSpec.prePostamble.readMinTccd)
         , prepostambleWriteMinTccd(memSpec.prePostamble.writeMinTccd)
-        , dram_base<CmdType>({
-            {pattern_descriptor::V, PatternEncoderBitSpec::H},
-            {pattern_descriptor::X, PatternEncoderBitSpec::H},
-        })
 	{
         // In the first state all ranks are precharged
         //for (auto &rank : ranks) {
@@ -166,24 +166,25 @@ namespace DRAMPower {
     )
     {
         // TODO: If simulation finishes in read/write transaction the postamble needs to be substracted
-        uint64_t minTccd = prepostambleWriteMinTccd;
+        // uint64_t minTccd = prepostambleWriteMinTccd; // Todo use minTccd
         uint64_t *lastAccess = &rank.lastWriteEnd;
         uint64_t diff = 0;
 
         if(read)
         {
             lastAccess = &rank.lastReadEnd;
-            minTccd = prepostambleReadMinTccd;
+            // minTccd = prepostambleReadMinTccd;
         }
         
-        diff = timestamp - *lastAccess;
-        *lastAccess = timestamp + length;
-        
-        if(diff < 0)
+        assert(timestamp >= *lastAccess);
+        if(timestamp < *lastAccess)
         {
             std::cout << "[Error] PrePostamble diff is negative. The last read/write transaction was not completed" << std::endl;
             return;
         }
+        diff = timestamp - *lastAccess;
+        *lastAccess = timestamp + length;
+        
         //assert(diff >= 0);
         
         // Pre and Postamble seamless
@@ -255,26 +256,22 @@ namespace DRAMPower {
         assert(this->ranks.size()>cmd.targetCoordinate.rank);
         auto & rank = this->ranks[cmd.targetCoordinate.rank];
 
-        switch (cmd.type) {
-            case CmdType::RD:
-            case CmdType::RDA:
-                length = cmd.sz_bits / readBus.get_width();
-                if ( length != 0 )
-                {
-                    readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Use default burst length
-                    // Cannot load readBus with data. TODO toggling rate
-                }
-                readDQS_.start(cmd.timestamp);
-                readDQS_.stop(cmd.timestamp + length / memSpec.dataRate);
-                handlePrePostamble(cmd.timestamp, length / memSpec.dataRate, rank, true);
-                handleInterfaceOverrides(length, true);
-                break;
-            case CmdType::WR:
-            case CmdType::WRA:
+        if (cmd.type == CmdType::RD || cmd.type == CmdType::RDA) {
+            length = cmd.sz_bits / readBus.get_width();
+            if ( length != 0 )
+            {
+                readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Use default burst length
+                // Cannot load readBus with data. TODO toggling rate
+            }
+            readDQS_.start(cmd.timestamp);
+            readDQS_.stop(cmd.timestamp + length / memSpec.dataRate);
+            handlePrePostamble(cmd.timestamp, length / memSpec.dataRate, rank, true);
+            handleInterfaceOverrides(length, true);
+        } else if (cmd.type == CmdType::WR || cmd.type == CmdType::WRA) {
                 length = cmd.sz_bits / writeBus.get_width();
                 if ( length != 0 )
                 {
@@ -289,8 +286,7 @@ namespace DRAMPower {
                 writeDQS_.stop(cmd.timestamp + length / memSpec.dataRate);
                 handlePrePostamble(cmd.timestamp, length / memSpec.dataRate, rank, false);
                 handleInterfaceOverrides(length, false);
-                break;
-        };
+        }
 
         auto pattern = this->getCommandPattern(cmd);
         length = this->getPattern(cmd.type).size() / commandBus.get_width();
@@ -361,7 +357,7 @@ namespace DRAMPower {
         // Required for precharge power-down
     }
 
-    void DDR4::handleRead(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void DDR4::handleRead(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.reads;
     }
 
@@ -379,7 +375,7 @@ namespace DRAMPower {
         });
     }
 
-    void DDR4::handleWrite(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void DDR4::handleWrite(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.writes;
     }
 
@@ -493,7 +489,7 @@ namespace DRAMPower {
         });
     }
 
-    void DDR4::endOfSimulation(timestamp_t timestamp) {
+    void DDR4::endOfSimulation(timestamp_t) {
         assert(this->implicitCommandCount() == 0);
 	}
 
diff --git a/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.h b/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.h
index 459f6d35..233a1807 100644
--- a/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.h
+++ b/src/DRAMPower/DRAMPower/standards/ddr4/DDR4.h
@@ -27,6 +27,8 @@ class DDR4 : public dram_base<CmdType>{
 public:
     MemSpecDDR4 memSpec;
     std::vector<Rank> ranks;
+    util::Bus readBus;
+    util::Bus writeBus;
 
 // commandBus dependes on cmdBusInitPattern and cmdBusWidth
 // cmdBusInitPattern must be initialized before commandBus
@@ -35,11 +37,11 @@ class DDR4 : public dram_base<CmdType>{
 private:
     std::size_t cmdBusWidth;
     uint64_t cmdBusInitPattern;
+    util::Clock readDQS_;
+    util::Clock writeDQS_;
+    util::Clock clock;
 public:
     util::Bus commandBus;
-    util::Bus readBus;
-    util::Bus writeBus;
-
     uint64_t prepostambleReadMinTccd;
     uint64_t prepostambleWriteMinTccd;
 
@@ -56,7 +58,7 @@ class DDR4 : public dram_base<CmdType>{
             rank.commandCounter.inc(command.type);
             (this->*member_func)(rank, bank, command.timestamp);
         });
-    };
+    }
 
     template<dram_base::commandEnum_t Cmd, typename Func>
     void registerRankHandler(Func && member_func) {
@@ -67,14 +69,14 @@ class DDR4 : public dram_base<CmdType>{
             rank.commandCounter.inc(command.type);
             (this->*member_func)(rank, command.timestamp);
         });
-    };
+    }
 
     template<dram_base::commandEnum_t Cmd, typename Func>
     void registerHandler(Func && member_func) {
         this->routeCommand<Cmd>([this, member_func](const Command & command) {
             (this->*member_func)(command.timestamp);
         });
-    };
+    }
 
     void registerPatterns();
 public:
@@ -130,10 +132,6 @@ class DDR4 : public dram_base<CmdType>{
 public:
     SimulationStats getWindowStats(timestamp_t timestamp);
 
-private:
-    util::Clock clock;
-    util::Clock readDQS_;
-    util::Clock writeDQS_;
 };
 
 };
diff --git a/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.cpp b/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.cpp
index 549e865c..ac563dac 100644
--- a/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.cpp
+++ b/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.cpp
@@ -10,22 +10,7 @@
 namespace DRAMPower {
 
     DDR5::DDR5(const MemSpecDDR5 &memSpec)
-        : memSpec(memSpec),
-        ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks}),
-        cmdBusWidth(14),
-        cmdBusInitPattern((1<<cmdBusWidth)-1),
-        commandBus(
-            cmdBusWidth, 1,
-            util::Bus::BusIdlePatternSpec::H,
-            util::Bus::burst_t(cmdBusWidth, cmdBusInitPattern)
-        ),
-        readBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
-            util::Bus::BusIdlePatternSpec::H, util::Bus::BusInitPatternSpec::H},
-        writeBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
-            util::Bus::BusIdlePatternSpec::H, util::Bus::BusInitPatternSpec::H},
-        readDQS(memSpec.dataRateSpec.dqsBusRate, true),
-        writeDQS(memSpec.dataRateSpec.dqsBusRate, true),
-        dram_base<CmdType>(PatternEncoderOverrides{
+        : dram_base<CmdType>(PatternEncoderOverrides{
             {pattern_descriptor::V, PatternEncoderBitSpec::H},
             {pattern_descriptor::X, PatternEncoderBitSpec::H}, // TODO high impedance ???
             {pattern_descriptor::C0, PatternEncoderBitSpec::H},
@@ -35,7 +20,22 @@ namespace DRAMPower {
             // {pattern_descriptor::CID1, PatternEncoderBitSpec::H},
             // {pattern_descriptor::CID2, PatternEncoderBitSpec::H},
             // {pattern_descriptor::CID3, PatternEncoderBitSpec::H},
-        })
+          })
+        , memSpec(memSpec)
+        , ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks})
+        , writeBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
+            util::Bus::BusIdlePatternSpec::H, util::Bus::BusInitPatternSpec::H}
+        , readBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
+            util::Bus::BusIdlePatternSpec::H, util::Bus::BusInitPatternSpec::H}
+        , cmdBusWidth(14)
+        , cmdBusInitPattern((1<<cmdBusWidth)-1)
+        , commandBus(
+            cmdBusWidth, 1,
+            util::Bus::BusIdlePatternSpec::H,
+            util::Bus::burst_t(cmdBusWidth, cmdBusInitPattern)
+        )
+        , readDQS(memSpec.dataRateSpec.dqsBusRate, true)
+        , writeDQS(memSpec.dataRateSpec.dqsBusRate, true)
     {
         this->registerPatterns();
 
@@ -212,39 +212,34 @@ namespace DRAMPower {
         size_t length = 0;
 
         // Handle data bus and dqs lines
-        switch (cmd.type) {
-            case CmdType::RD:
-            case CmdType::RDA:
-                length = cmd.sz_bits / readBus.get_width();
-                if ( length != 0 )
-                {
-                    readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Default default burst length
-                    // Cannot load readBus with data. TODO toggling rate
-                }
-                readDQS.start(cmd.timestamp);
-                readDQS.stop(cmd.timestamp + length / memSpec.dataRateSpec.dqsBusRate);
-                this->handleInterfaceOverrides(length, true);
-                break;
-            case CmdType::WR:
-            case CmdType::WRA:
-                length = cmd.sz_bits / writeBus.get_width();
-                if ( length != 0 )
-                {
-                    writeBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Default default burst length
-                    // Cannot load writeBus with data. TODO toggling rate
-                }
-                writeDQS.start(cmd.timestamp);
-                writeDQS.stop(cmd.timestamp + length / memSpec.dataRateSpec.dqsBusRate);
-                this->handleInterfaceOverrides(length, false);
-                break;
+        if (cmd.type == CmdType::RD || cmd.type == CmdType::RDA) {
+            length = cmd.sz_bits / readBus.get_width();
+            if ( length != 0 )
+            {
+                readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Default default burst length
+                // Cannot load readBus with data. TODO toggling rate
+            }
+            readDQS.start(cmd.timestamp);
+            readDQS.stop(cmd.timestamp + length / memSpec.dataRateSpec.dqsBusRate);
+            this->handleInterfaceOverrides(length, true);
+        } else if (cmd.type == CmdType::WR || cmd.type == CmdType::WRA) {
+            length = cmd.sz_bits / writeBus.get_width();
+            if ( length != 0 )
+            {
+                writeBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Default default burst length
+                // Cannot load writeBus with data. TODO toggling rate
+            }
+            writeDQS.start(cmd.timestamp);
+            writeDQS.stop(cmd.timestamp + length / memSpec.dataRateSpec.dqsBusRate);
+            this->handleInterfaceOverrides(length, false);
         }
 
         // command bus
@@ -281,7 +276,7 @@ namespace DRAMPower {
 
     void DDR5::handlePreSameBank(Rank & rank, std::size_t bank_id, timestamp_t timestamp) {
         auto bank_id_inside_bg = bank_id % this->memSpec.banksPerGroup;
-        for(auto bank_group = 0; bank_group < this->memSpec.numberOfBankGroups; bank_group++) {
+        for(unsigned bank_group = 0; bank_group < this->memSpec.numberOfBankGroups; bank_group++) {
             auto & bank = rank.banks[bank_group * this->memSpec.banksPerGroup + bank_id_inside_bg];
             handlePre(rank, bank, timestamp);
         }
@@ -295,7 +290,7 @@ namespace DRAMPower {
 
     void DDR5::handleRefSameBank(Rank & rank, std::size_t bank_id, timestamp_t timestamp) {
         auto bank_id_inside_bg = bank_id % this->memSpec.banksPerGroup;
-        for(auto bank_group = 0; bank_group < this->memSpec.numberOfBankGroups; bank_group++) {
+        for(unsigned bank_group = 0; bank_group < this->memSpec.numberOfBankGroups; bank_group++) {
             auto & bank = rank.banks[bank_group * this->memSpec.banksPerGroup + bank_id_inside_bg];
             handleRefreshOnBank(rank, bank, timestamp, memSpec.memTimingSpec.tRFCsb, bank.counter.refSameBank);
         }
@@ -336,7 +331,7 @@ namespace DRAMPower {
         });
     }
 
-    void DDR5::handleRead(Rank &rank, Bank &bank, timestamp_t timestamp){
+    void DDR5::handleRead(Rank&, Bank &bank, timestamp_t){
         ++bank.counter.reads;
     }
 
@@ -354,7 +349,7 @@ namespace DRAMPower {
         });
     }
 
-    void DDR5::handleWrite(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void DDR5::handleWrite(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.writes;
     }
 
@@ -453,7 +448,7 @@ namespace DRAMPower {
         });
     }
 
-    void DDR5::endOfSimulation(timestamp_t timestamp) {
+    void DDR5::endOfSimulation(timestamp_t) {
         if (this->implicitCommandCount() > 0)
             std::cout << ("[WARN] End of simulation but still implicit commands left!") << std::endl;
     }
diff --git a/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.h b/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.h
index cf5dd9c4..5f49451c 100644
--- a/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.h
+++ b/src/DRAMPower/DRAMPower/standards/ddr5/DDR5.h
@@ -20,16 +20,22 @@ namespace DRAMPower {
 
 class DDR5 : public dram_base<CmdType> {
 
+public:
+    MemSpecDDR5 memSpec;
+    std::vector<Rank> ranks;
+    util::Bus writeBus;
+    util::Bus readBus;
 private:
     std::size_t cmdBusWidth;
     uint64_t cmdBusInitPattern;
 public:
-    MemSpecDDR5 memSpec;
-    std::vector<Rank> ranks;
     util::Bus commandBus;
-    util::Bus readBus;
-    util::Bus writeBus;
+private:
+    util::Clock readDQS;
+    util::Clock writeDQS;
+    util::Clock clock;
 
+public:
     DDR5(const MemSpecDDR5& memSpec);
     virtual ~DDR5() = default;
 
@@ -101,21 +107,16 @@ class DDR5 : public dram_base<CmdType> {
             rank.commandCounter.inc(command.type);
             (this->*member_func)(rank, command.timestamp);
         });
-    };
+    }
 
     template <dram_base::commandEnum_t Cmd, typename Func>
     void registerHandler(Func&& member_func) {
         this->routeCommand<Cmd>([this, member_func](const Command& command) {
             (this->*member_func)(command.timestamp);
         });
-    };
+    }
 
     void registerPatterns();
-
-private:
-    util::Clock clock;
-    util::Clock readDQS;
-    util::Clock writeDQS;
 };
 
 }  // namespace DRAMPower
diff --git a/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.cpp b/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.cpp
index 288f35cd..9e95e5fe 100644
--- a/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.cpp
+++ b/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.cpp
@@ -7,20 +7,22 @@
 
 namespace DRAMPower {
 
-    LPDDR4::LPDDR4(const MemSpecLPDDR4 &memSpec): 
-        memSpec(memSpec), ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks}),
-        commandBus{6, 1, util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L},
-        readBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
-            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L
-        },
-        writeBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
-            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L
-        },
-        readDQS(memSpec.dataRate, true), writeDQS(memSpec.dataRate, true),
-        dram_base<CmdType>(PatternEncoderOverrides{
+    LPDDR4::LPDDR4(const MemSpecLPDDR4 &memSpec)
+        : dram_base<CmdType>(PatternEncoderOverrides{
             {pattern_descriptor::C0, PatternEncoderBitSpec::L},
             {pattern_descriptor::C1, PatternEncoderBitSpec::L},
-        }) 
+          }) 
+        , memSpec(memSpec)
+        , ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks})
+        , commandBus{6, 1, util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L}
+        , readBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
+            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L
+        }
+        , writeBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
+            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L
+        }
+        , readDQS(memSpec.dataRate, true)
+        , writeDQS(memSpec.dataRate, true)
     {
         this->registerPatterns();
 
@@ -118,10 +120,9 @@ namespace DRAMPower {
                                            });
     };
 
-    void LPDDR4::handleInterfaceOverrides(size_t length, bool read)
+    void LPDDR4::handleInterfaceOverrides(size_t length, bool /*read*/)
     {
         // Set command bus pattern overrides
-        bool def = false;
         switch(length) {
             case 32:
                 this->encoder.settings.updateSettings({
@@ -150,39 +151,34 @@ namespace DRAMPower {
         size_t length = 0;
 
         // Handle data bus and dqs lines
-        switch (cmd.type) {
-            case CmdType::RD:
-            case CmdType::RDA:
-                length = cmd.sz_bits / readBus.get_width();
-                if ( length != 0 )
-                {
-                    readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Use default burst length
-                    // Cannot load readBus with data. TODO toggling rate
-                }
-                readDQS.start(cmd.timestamp);
-                readDQS.stop(cmd.timestamp + length / memSpec.dataRate);
-                handleInterfaceOverrides(length, true);
-                break;
-            case CmdType::WR:
-            case CmdType::WRA:
-                length = cmd.sz_bits / writeBus.get_width();
-                if ( length != 0 )
-                {
-                    writeBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Use default burst length
-                    // Cannot load writeBus with data. TODO toggling rate
-                }
-                writeDQS.start(cmd.timestamp);
-                writeDQS.stop(cmd.timestamp + length / memSpec.dataRate);
-                handleInterfaceOverrides(length, false);
-                break;
+        if (cmd.type == CmdType::RD || cmd.type == CmdType::RDA) {
+            length = cmd.sz_bits / readBus.get_width();
+            if ( length != 0 )
+            {
+                readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Use default burst length
+                // Cannot load readBus with data. TODO toggling rate
+            }
+            readDQS.start(cmd.timestamp);
+            readDQS.stop(cmd.timestamp + length / memSpec.dataRate);
+            handleInterfaceOverrides(length, true);
+        } else if (cmd.type == CmdType::WR || cmd.type == CmdType::WRA) {
+            length = cmd.sz_bits / writeBus.get_width();
+            if ( length != 0 )
+            {
+                writeBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Use default burst length
+                // Cannot load writeBus with data. TODO toggling rate
+            }
+            writeDQS.start(cmd.timestamp);
+            writeDQS.stop(cmd.timestamp + length / memSpec.dataRate);
+            handleInterfaceOverrides(length, false);
         }
 
         // Command bus
@@ -339,11 +335,11 @@ namespace DRAMPower {
         });
     }
 
-    void LPDDR4::handleRead(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void LPDDR4::handleRead(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.reads;
     }
 
-    void LPDDR4::handleWrite(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void LPDDR4::handleWrite(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.writes;
     }
 
@@ -375,7 +371,7 @@ namespace DRAMPower {
         });
     }
 
-    void LPDDR4::endOfSimulation(timestamp_t timestamp) {
+    void LPDDR4::endOfSimulation(timestamp_t) {
         if (this->implicitCommandCount() > 0)
 			std::cout << ("[WARN] End of simulation but still implicit commands left!") << std::endl;
 	}
diff --git a/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.h b/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.h
index f40902c1..4555174a 100644
--- a/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.h
+++ b/src/DRAMPower/DRAMPower/standards/lpddr4/LPDDR4.h
@@ -28,17 +28,15 @@ class LPDDR4 : public dram_base<CmdType>{
 public:
     MemSpecLPDDR4 memSpec;
     std::vector<Rank> ranks;
-
-    util::Clock clock;
-
     util::Bus commandBus;
     util::Bus readBus;
     util::Bus writeBus;
-
     util::Clock readDQS;
-
     util::Clock writeDQS;
 
+    util::Clock clock;
+
+
     //util::Bus dataBus;
 protected:
     template<dram_base::commandEnum_t Cmd, typename Func>
@@ -49,7 +47,7 @@ class LPDDR4 : public dram_base<CmdType>{
             rank.commandCounter.inc(command.type);
             (this->*member_func)(rank, bank, command.timestamp);
         });
-    };
+    }
 
     template<dram_base::commandEnum_t Cmd, typename Func>
     void registerRankHandler(Func && member_func) {
@@ -59,14 +57,14 @@ class LPDDR4 : public dram_base<CmdType>{
             rank.commandCounter.inc(command.type);
             (this->*member_func)(rank, command.timestamp);
         });
-    };
+    }
 
     template<dram_base::commandEnum_t Cmd, typename Func>
     void registerHandler(Func && member_func) {
         this->routeCommand<Cmd>([this, member_func](const Command & command) {
             (this->*member_func)(command.timestamp);
         });
-    };
+    }
 
     void registerPatterns();
 public:
diff --git a/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.cpp b/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.cpp
index 7be10dcf..64e59d9c 100644
--- a/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.cpp
+++ b/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.cpp
@@ -9,17 +9,17 @@
 namespace DRAMPower {
 
     LPDDR5::LPDDR5(const MemSpecLPDDR5 &memSpec)
-        : memSpec(memSpec),
-        ranks(memSpec.numberOfRanks, { (std::size_t)memSpec.numberOfBanks }),
-        commandBus{7, 2, // modelled with datarate 2
-            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L},
-        readBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
-            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L},
-        writeBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
-            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L},
-        readDQS(memSpec.dataRate, true),
-        wck(memSpec.dataRate / memSpec.memTimingSpec.WCKtoCK, !memSpec.wckAlwaysOnMode),
-        dram_base<CmdType>(PatternEncoderOverrides{})
+        : dram_base<CmdType>(PatternEncoderOverrides{})
+        , memSpec(memSpec)
+        , ranks(memSpec.numberOfRanks, { (std::size_t)memSpec.numberOfBanks })
+        , commandBus{7, 2, // modelled with datarate 2
+            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L}
+        , readBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
+            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L}
+        , writeBus{memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
+            util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L}
+        , readDQS(memSpec.dataRate, true)
+        , wck(memSpec.dataRate / memSpec.memTimingSpec.WCKtoCK, !memSpec.wckAlwaysOnMode)
     {
         this->registerPatterns();
 
@@ -247,10 +247,9 @@ namespace DRAMPower {
         });
     }
 
-    void LPDDR5::handleInterfaceOverrides(size_t length, bool read)
+    void LPDDR5::handleInterfaceOverrides(size_t length, bool /*read*/)
     {
         // Set command bus pattern overrides
-        bool def = false;
         switch(length) {
             case 32:
                 this->encoder.settings.updateSettings({
@@ -270,49 +269,43 @@ namespace DRAMPower {
     void LPDDR5::handle_interface(const Command &cmd) {
         size_t length = 0;
 
-        switch (cmd.type) {
-            case CmdType::RD:
-            case CmdType::RDA:
-                length = cmd.sz_bits / readBus.get_width();
-                if ( length != 0 )
-                {
-                    readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Use default burst length
-                    // Cannot load readBus with data. TODO toggling rate
-                }
-                readDQS.start(cmd.timestamp);
-                readDQS.stop(cmd.timestamp + length / memSpec.dataRate);
-
-                // WCK also during reads
-                if (!memSpec.wckAlwaysOnMode) {
-                    wck.start(cmd.timestamp);
-                    wck.stop(cmd.timestamp + length / memSpec.dataRate);
-                }
-                handleInterfaceOverrides(length, true);
+        if (cmd.type == CmdType::RD || cmd.type == CmdType::RDA) {
+            length = cmd.sz_bits / readBus.get_width();
+            if ( length != 0 )
+            {
+                readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Use default burst length
+                // Cannot load readBus with data. TODO toggling rate
+            }
+            readDQS.start(cmd.timestamp);
+            readDQS.stop(cmd.timestamp + length / memSpec.dataRate);
 
-                break;
-            case CmdType::WR:
-            case CmdType::WRA:
-                length = cmd.sz_bits / writeBus.get_width();
-                if ( length != 0 )
-                {
-                    writeBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Use default burst length
-                    // Cannot load writeBus with data. TODO toggling rate
-                }
+            // WCK also during reads
+            if (!memSpec.wckAlwaysOnMode) {
+                wck.start(cmd.timestamp);
+                wck.stop(cmd.timestamp + length / memSpec.dataRate);
+            }
+            handleInterfaceOverrides(length, true);
+        } else if (cmd.type == CmdType::WR || cmd.type == CmdType::WRA) {
+            length = cmd.sz_bits / writeBus.get_width();
+            if ( length != 0 )
+            {
+                writeBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Use default burst length
+                // Cannot load writeBus with data. TODO toggling rate
+            }
 
-                if (!memSpec.wckAlwaysOnMode) {
-                    wck.start(cmd.timestamp);
-                    wck.stop(cmd.timestamp + length / memSpec.dataRate);
-                }
-                handleInterfaceOverrides(length, true);
-                break;
+            if (!memSpec.wckAlwaysOnMode) {
+                wck.start(cmd.timestamp);
+                wck.stop(cmd.timestamp + length / memSpec.dataRate);
+            }
+            handleInterfaceOverrides(length, true);
         }
         auto pattern = getCommandPattern(cmd);
         auto ca_length = getPattern(cmd.type).size() / commandBus.get_width();
@@ -391,7 +384,7 @@ namespace DRAMPower {
         });
     }
 
-    void LPDDR5::handleRead(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void LPDDR5::handleRead(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.reads;
     }
 
@@ -409,7 +402,7 @@ namespace DRAMPower {
         });
     }
 
-    void LPDDR5::handleWrite(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void LPDDR5::handleWrite(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.writes;
     }
 
@@ -519,7 +512,7 @@ namespace DRAMPower {
         rank.memState = MemState::SREF;
     }
 
-    void LPDDR5::endOfSimulation(timestamp_t timestamp) {
+    void LPDDR5::endOfSimulation(timestamp_t) {
         if (this->implicitCommandCount() > 0)
 			std::cout << ("[WARN] End of simulation but still implicit commands left!") << std::endl;
 	}
@@ -593,9 +586,9 @@ namespace DRAMPower {
         stats.readBus = readBus.get_stats(timestamp);
         stats.writeBus = writeBus.get_stats(timestamp);
 
-        stats.clockStats = 2.0 * clock.get_stats_at(timestamp);
-        stats.wClockStats = 2.0 * wck.get_stats_at(timestamp);
-        stats.readDQSStats = 2.0 * readDQS.get_stats_at(timestamp);
+        stats.clockStats = 2 * clock.get_stats_at(timestamp);
+        stats.wClockStats = 2 * wck.get_stats_at(timestamp);
+        stats.readDQSStats = 2 * readDQS.get_stats_at(timestamp);
 
         return stats;
     }
diff --git a/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.h b/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.h
index 0157e902..1a95a0cf 100644
--- a/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.h
+++ b/src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.h
@@ -20,10 +20,23 @@
 
 namespace DRAMPower {
 class LPDDR5 : public dram_base<CmdType> {
-   public:
+
+public:
     LPDDR5(const MemSpecLPDDR5& memSpec);
     virtual ~LPDDR5() = default;
 
+public:
+    MemSpecLPDDR5 memSpec;
+    std::vector<Rank> ranks;
+private:
+    util::Bus commandBus;
+    util::Bus readBus;
+    util::Bus writeBus;
+    util::Clock readDQS;
+    util::Clock wck;
+    util::Clock clock;
+
+public:
 
     SimulationStats getStats() override;
     uint64_t getBankCount() override;
@@ -56,17 +69,11 @@ class LPDDR5 : public dram_base<CmdType> {
     energy_t calcCoreEnergy(timestamp_t timestamp) override;
     interface_energy_info_t calcInterfaceEnergy(timestamp_t timestamp) override;
     
-    MemSpecLPDDR5 memSpec;
-    std::vector<Rank> ranks;
 private:
     // Calculations
     void handle_interface(const Command& cmd) override;
     void handleInterfaceOverrides(size_t length, bool read);
 
-    util::Bus commandBus;
-    util::Bus readBus;
-    util::Bus writeBus;
-
 private:
     template <dram_base::commandEnum_t Cmd, typename Func>
     void registerBankHandler(Func&& member_func) {
@@ -76,13 +83,12 @@ class LPDDR5 : public dram_base<CmdType> {
             rank.commandCounter.inc(command.type);
             (this->*member_func)(rank, bank, command.timestamp);
         });
-    };
+    }
 
     template <dram_base::commandEnum_t Cmd, typename Func>
     void registerBankGroupHandler(Func&& member_func) {
         this->routeCommand<Cmd>([this, member_func](const Command& command) {
             auto& rank = this->ranks[command.targetCoordinate.rank];
-            auto& bank = rank.banks[command.targetCoordinate.bank];
             rank.commandCounter.inc(command.type);
             auto bank_id = command.targetCoordinate.bank;
             (this->*member_func)(rank, bank_id, command.timestamp);
@@ -97,21 +103,18 @@ class LPDDR5 : public dram_base<CmdType> {
             rank.commandCounter.inc(command.type);
             (this->*member_func)(rank, command.timestamp);
         });
-    };
+    }
 
     template <dram_base::commandEnum_t Cmd, typename Func>
     void registerHandler(Func&& member_func) {
         this->routeCommand<Cmd>([this, member_func](const Command& command) {
             (this->*member_func)(command.timestamp);
         });
-    };
+    }
 
     void registerPatterns();
     timestamp_t earliestPossiblePowerDownEntryTime(Rank& rank);
 
-    util::Clock clock;
-    util::Clock wck;
-    util::Clock readDQS;
 };
 };  // namespace DRAMPower
 
diff --git a/src/DRAMPower/DRAMPower/util/binary_ops.h b/src/DRAMPower/DRAMPower/util/binary_ops.h
index b38ae8c9..bdb135ca 100644
--- a/src/DRAMPower/DRAMPower/util/binary_ops.h
+++ b/src/DRAMPower/DRAMPower/util/binary_ops.h
@@ -34,25 +34,25 @@ struct BinaryOps {
     static std::size_t popcount(const T& bitset)
     {
         return bitset.count();
-    };
+    }
 
     template <typename T>
     static std::size_t zero_to_ones(const T& p, const T& q)
     {
         return popcount(~p & q);
-    };
+    }
 
     template <typename T>
     static std::size_t one_to_zeroes(const T& p, const T& q)
     {
         return popcount(p & ~q);
-    };
+    }
 
     template <typename T>
     static std::size_t bit_changes(const T& p, const T& q)
     {
         return popcount(p ^ q);
-    };
+    }
 };
 
 };
diff --git a/src/DRAMPower/DRAMPower/util/burst_storage.h b/src/DRAMPower/DRAMPower/util/burst_storage.h
index 29f8ecec..14af6830 100644
--- a/src/DRAMPower/DRAMPower/util/burst_storage.h
+++ b/src/DRAMPower/DRAMPower/util/burst_storage.h
@@ -21,9 +21,9 @@ class burst_storage
 	public:
 		using bitset_t = burst_t;
 	private:
-		const std::size_t N;
 		std::size_t pos = 0;
 		bitset_t& bitset;
+		const std::size_t N;
 	public:
 		bitset_inserter(bitset_t& bitset, std::size_t N)
 			: bitset(bitset) , N(N) {};
diff --git a/src/DRAMPower/DRAMPower/util/bus.h b/src/DRAMPower/DRAMPower/util/bus.h
index 15c54278..8c23d72c 100644
--- a/src/DRAMPower/DRAMPower/util/bus.h
+++ b/src/DRAMPower/DRAMPower/util/bus.h
@@ -12,6 +12,7 @@
 #include <cstdint>
 #include <limits>
 #include <cassert>
+#include <limits.h>
 
 #include <iostream>
 
@@ -148,8 +149,7 @@ class Bus {
 		width(width), burst_storage(width), datarate(datarate),
 		idle_pattern(idle_pattern), init_pattern(init_pattern), custom_init_pattern (custom_init_pattern)
 	{
-			
-		assert(width >= 0);
+		static_assert(std::numeric_limits<decltype(width)>::is_signed == false, "std::size_t must be unsigned");
 		
 		// Initialize zero and one patterns
 		this->zero_pattern = burst_t();
@@ -294,7 +294,7 @@ class Bus {
 	std::optional<burst_t> at(timestamp_t n) const
 	{
 		// Assert timestamp does not lie in past
-		assert(n - last_load >= 0);
+		assert(n >= last_load);
 
 		if (n - this->last_load >= burst_storage.size()) {
 			switch(this->idle_pattern)
diff --git a/src/DRAMPower/DRAMPower/util/dynamic_bitset.cpp b/src/DRAMPower/DRAMPower/util/dynamic_bitset.cpp
index 3bf38bfd..3ae93a04 100644
--- a/src/DRAMPower/DRAMPower/util/dynamic_bitset.cpp
+++ b/src/DRAMPower/DRAMPower/util/dynamic_bitset.cpp
@@ -10,7 +10,7 @@ dynamic_bitset::dynamic_bitset()
 dynamic_bitset::dynamic_bitset(std::size_t num_bits)
     : buffer(num_bits, 0) {};
 
-dynamic_bitset::dynamic_bitset(std::size_t num_bits, unsigned long value)
+dynamic_bitset::dynamic_bitset(std::size_t num_bits, uint64_t value)
     : buffer(num_bits)
 {
     std::size_t accumulator = 1;
diff --git a/src/DRAMPower/DRAMPower/util/dynamic_bitset.h b/src/DRAMPower/DRAMPower/util/dynamic_bitset.h
index c855a38f..9be4f9e0 100644
--- a/src/DRAMPower/DRAMPower/util/dynamic_bitset.h
+++ b/src/DRAMPower/DRAMPower/util/dynamic_bitset.h
@@ -22,7 +22,7 @@ class dynamic_bitset
 public:
     explicit dynamic_bitset();
     explicit dynamic_bitset(std::size_t num_bits);
-    explicit dynamic_bitset(std::size_t num_bits, unsigned long value = 0);
+    explicit dynamic_bitset(std::size_t num_bits, uint64_t value = 0);
 public:
     dynamic_bitset(const dynamic_bitset&) = default;
     dynamic_bitset(dynamic_bitset&&) noexcept = default;
diff --git a/tests/tests_drampower/CMakeLists.txt b/tests/tests_drampower/CMakeLists.txt
index 5f5ac9b0..99361e1b 100644
--- a/tests/tests_drampower/CMakeLists.txt
+++ b/tests/tests_drampower/CMakeLists.txt
@@ -2,7 +2,7 @@
 ###              tests_drampower            ###
 ###############################################
 
-cmake_minimum_required(VERSION 3.1.0)
+cmake_minimum_required(VERSION 3.5.0)
 
 project(tests_drampower)
 
diff --git a/tests/tests_drampower/base/test_ddr_base.cpp b/tests/tests_drampower/base/test_ddr_base.cpp
index 3de6fcc2..fc4b6769 100644
--- a/tests/tests_drampower/base/test_ddr_base.cpp
+++ b/tests/tests_drampower/base/test_ddr_base.cpp
@@ -14,10 +14,10 @@ class test_ddr : public dram_base<CmdType>
 {
 	// Overrides
 private:
-	void handle_interface(const Command& cmd) override {};
+	void handle_interface(const Command&) override {};
 public:
-	energy_t calcCoreEnergy(timestamp_t timestamp) override { return energy_t(1); };
-    interface_energy_info_t calcInterfaceEnergy(timestamp_t timestamp) override { return interface_energy_info_t(); };
+	energy_t calcCoreEnergy(timestamp_t) override { return energy_t(1); };
+    interface_energy_info_t calcInterfaceEnergy(timestamp_t) override { return interface_energy_info_t(); };
 	uint64_t getBankCount() override { return 1; };
 	uint64_t getRankCount() override { return 1; };
 	uint64_t getDeviceCount() override { return 1; };
diff --git a/tests/tests_drampower/base/test_pattern_pre_cycles.cpp b/tests/tests_drampower/base/test_pattern_pre_cycles.cpp
index f3221659..d9fb52c6 100644
--- a/tests/tests_drampower/base/test_pattern_pre_cycles.cpp
+++ b/tests/tests_drampower/base/test_pattern_pre_cycles.cpp
@@ -77,8 +77,6 @@ class DramPowerTest_Pre_Cycles : public ::testing::Test {
 
 TEST_F(DramPowerTest_Pre_Cycles, Test)
 {
-	Rank & rank_1 = ddr->ranks[0];
-
 	for (const auto& command : testPattern) {
 		ddr->doCoreCommand(command);
 	};
@@ -111,9 +109,6 @@ TEST_F(DramPowerTest_Pre_Cycles, Test_Detailed)
 		return this->ddr->getWindowStats(timestamp);
 	};
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 5
 	window = iterate_to_timestamp(5);
 	ASSERT_EQ(window.rank_total[0].cycles.act, 5);    ASSERT_EQ(window.rank_total[0].cycles.pre, 0);
diff --git a/tests/tests_drampower/core/DDR4/ddr4_multidevice_tests.cpp b/tests/tests_drampower/core/DDR4/ddr4_multidevice_tests.cpp
index 6080246d..ad677ef7 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_multidevice_tests.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_multidevice_tests.cpp
@@ -29,6 +29,7 @@ Total * 5:				22040.913461538462
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <memory>
 
@@ -79,7 +80,7 @@ TEST_F(DramPowerTest_DDR4_MultiDevice, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -87,7 +88,7 @@ TEST_F(DramPowerTest_DDR4_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if(b == 3)
@@ -97,7 +98,7 @@ TEST_F(DramPowerTest_DDR4_MultiDevice, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -109,7 +110,7 @@ TEST_F(DramPowerTest_DDR4_MultiDevice, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -119,7 +120,7 @@ TEST_F(DramPowerTest_DDR4_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_0.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_0.cpp
index e701bf41..8e4032fd 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_0.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_0.cpp
@@ -7,6 +7,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <memory>
 
@@ -51,7 +52,7 @@ TEST_F(DramPowerTest_DDR4_0, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
 
     // Check cycles count
@@ -60,12 +61,12 @@ TEST_F(DramPowerTest_DDR4_0, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 15);
 }
 
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_1.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_1.cpp
index a251ae21..fba28c9c 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_1.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_1.cpp
@@ -7,6 +7,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <memory>
 
@@ -50,17 +51,17 @@ TEST_F(DramPowerTest_DDR4_1, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -69,12 +70,12 @@ TEST_F(DramPowerTest_DDR4_1, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 35);
 }
 
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_12.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_12.cpp
index 22870c1e..ba7d49fa 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_12.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_12.cpp
@@ -72,8 +72,6 @@ class DramPowerTest_DDR4_12 : public ::testing::Test {
         memSpec.prechargeOffsetRD    =  memSpec.memTimingSpec.tAL + memSpec.memTimingSpec.tRTP;
         memSpec.prechargeOffsetWR    =  memSpec.memTimingSpec.tBurst + memSpec.memTimingSpec.tWL + memSpec.memTimingSpec.tWR;
 
-		memSpec.memImpedanceSpec = {1.0};
-
         ddr = std::make_unique<DDR4>(memSpec);
     }
 
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_13.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_13.cpp
index 21a3a356..c9ba6203 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_13.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_13.cpp
@@ -78,7 +78,6 @@ TEST_F(DramPowerTest_DDR4_13, Test)
         ddr->doCoreCommand(command);
     };
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_14.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_14.cpp
index cb1ac9d7..b111087b 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_14.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_14.cpp
@@ -78,7 +78,6 @@ TEST_F(DramPowerTest_DDR4_14, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_15.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_15.cpp
index ce29eca4..8ed9e41e 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_15.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_15.cpp
@@ -80,7 +80,6 @@ TEST_F(DramPowerTest_DDR4_15, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
@@ -132,9 +131,6 @@ TEST_F(DramPowerTest_DDR4_15, CalcWindow)
 	auto command = testPattern.begin();
 
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 5
 	window = iterate_to_timestamp(command, 5);
 	ASSERT_EQ(window.rank_total[0].cycles.act, 5);
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_2.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_2.cpp
index 07dccaa7..21d23187 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_2.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_2.cpp
@@ -7,6 +7,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <memory>
 
@@ -51,17 +52,17 @@ TEST_F(DramPowerTest_DDR4_2, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -70,12 +71,12 @@ TEST_F(DramPowerTest_DDR4_2, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 50);
 }
 
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_3.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_3.cpp
index 8cd699e2..8606a530 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_3.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_3.cpp
@@ -7,6 +7,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <memory>
 
@@ -52,7 +53,7 @@ TEST_F(DramPowerTest_DDR4_3, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -60,7 +61,7 @@ TEST_F(DramPowerTest_DDR4_3, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
@@ -68,7 +69,7 @@ TEST_F(DramPowerTest_DDR4_3, Counters_and_Cycles){
     }
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_DDR4_3, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 5);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 35);
         else if(b == 3)
@@ -90,7 +91,7 @@ TEST_F(DramPowerTest_DDR4_3, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 15);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_4.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_4.cpp
index 9d91dd45..a22124b3 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_4.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_4.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_DDR4_4, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,7 +62,7 @@ TEST_F(DramPowerTest_DDR4_4, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if(b == 3)
@@ -71,7 +72,7 @@ TEST_F(DramPowerTest_DDR4_4, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -83,7 +84,7 @@ TEST_F(DramPowerTest_DDR4_4, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_DDR4_4, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_5.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_5.cpp
index 2041ccd2..40f12061 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_5.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_5.cpp
@@ -7,6 +7,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <memory>
 
@@ -54,7 +55,7 @@ TEST_F(DramPowerTest_DDR4_5, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -62,7 +63,7 @@ TEST_F(DramPowerTest_DDR4_5, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if( b == 3)
@@ -72,7 +73,7 @@ TEST_F(DramPowerTest_DDR4_5, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_DDR4_5, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -89,7 +90,7 @@ TEST_F(DramPowerTest_DDR4_5, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 75);
         else if(b == 3)
@@ -99,7 +100,7 @@ TEST_F(DramPowerTest_DDR4_5, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 25);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_6.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_6.cpp
index 125216a6..08fa8e55 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_6.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_6.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_DDR4_6, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,14 +62,14 @@ TEST_F(DramPowerTest_DDR4_6, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 3)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
             ASSERT_EQ(stats.bank[b].counter.reads, 0);
     }
 
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.readAuto, 1);
         else
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_DDR4_6, Counters_and_Cycles){
     }
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -84,7 +85,7 @@ TEST_F(DramPowerTest_DDR4_6, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_DDR4_6, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 45);
         else if(b == 3)
@@ -103,7 +104,7 @@ TEST_F(DramPowerTest_DDR4_6, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 55);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_7.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_7.cpp
index e735ef53..d7aa6290 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_7.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_7.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -49,10 +50,10 @@ TEST_F(DramPowerTest_DDR4_7, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
 
 
     // Check cycles count
@@ -61,13 +62,13 @@ TEST_F(DramPowerTest_DDR4_7, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.selfRefresh, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
 
 }
 
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_8.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_8.cpp
index 402a2773..d012821b 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_8.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_8.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 #include <string>
@@ -64,19 +65,19 @@ TEST_F(DramPowerTest_DDR4_8, Counters_and_Cycles){
     // TODO pre for banks 2-16 invalid
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_DDR4_8, Energy) {
diff --git a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_9.cpp b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_9.cpp
index 6285fbd7..521c7a13 100644
--- a/tests/tests_drampower/core/DDR4/ddr4_test_pattern_9.cpp
+++ b/tests/tests_drampower/core/DDR4/ddr4_test_pattern_9.cpp
@@ -7,6 +7,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <memory>
 
@@ -66,7 +67,7 @@ TEST_F(DramPowerTest_DDR4_9, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats .bank[b].cycles.act, 45);
         }else if (b == 5){
@@ -77,7 +78,7 @@ TEST_F(DramPowerTest_DDR4_9, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         }else if (b == 5){
@@ -88,13 +89,13 @@ TEST_F(DramPowerTest_DDR4_9, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_DDR4_9, Energy) {
diff --git a/tests/tests_drampower/core/DDR5/ddr5_multidevice_tests.cpp b/tests/tests_drampower/core/DDR5/ddr5_multidevice_tests.cpp
index e16158ea..9b2ed363 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_multidevice_tests.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_multidevice_tests.cpp
@@ -31,6 +31,7 @@ Total * 5:				22040.913461538462
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -79,7 +80,7 @@ TEST_F(DramPowerTest_DDR5_MultiDevice, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -87,7 +88,7 @@ TEST_F(DramPowerTest_DDR5_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if(b == 3)
@@ -97,7 +98,7 @@ TEST_F(DramPowerTest_DDR5_MultiDevice, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -109,7 +110,7 @@ TEST_F(DramPowerTest_DDR5_MultiDevice, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -119,7 +120,7 @@ TEST_F(DramPowerTest_DDR5_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_0.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_0.cpp
index e9ffa0f1..d98b3b15 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_0.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_0.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -50,7 +51,7 @@ TEST_F(DramPowerTest_DDR5_0, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
 
     // Check cycles count
@@ -59,11 +60,11 @@ TEST_F(DramPowerTest_DDR5_0, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 15);
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 15);
 }
 
 TEST_F(DramPowerTest_DDR5_0, Energy) {
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_1.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_1.cpp
index 12278d25..a372f857 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_1.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_1.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -51,17 +52,17 @@ TEST_F(DramPowerTest_DDR5_1, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -70,12 +71,12 @@ TEST_F(DramPowerTest_DDR5_1, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 35);
 }
 
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_10.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_10.cpp
index a687ca3e..814a556e 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_10.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_10.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -61,7 +62,7 @@ TEST_F(DramPowerTest_DDR5_10, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 0);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.act, 75);
         }else if (b == 3 || b == 8){
@@ -74,7 +75,7 @@ TEST_F(DramPowerTest_DDR5_10, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 25);
         }else if (b == 3 || b == 8){
@@ -87,13 +88,13 @@ TEST_F(DramPowerTest_DDR5_10, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_DDR5_10, Energy) {
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_11.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_11.cpp
index 5079f47f..a71b64cd 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_11.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_11.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -63,7 +64,7 @@ TEST_F(DramPowerTest_DDR5_11, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 0);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.act, 55);
         }else if (b == 3){
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_DDR5_11, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 45);
         }else if (b == 3){
@@ -89,13 +90,13 @@ TEST_F(DramPowerTest_DDR5_11, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 
 }
 
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_15.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_15.cpp
index 03769327..ffb152bf 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_15.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_15.cpp
@@ -81,7 +81,6 @@ TEST_F(DramPowerTest_DDR5_15, Test)
         ddr->doCoreCommand(command);
     };
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_16.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_16.cpp
index 8e786a72..af542a9f 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_16.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_16.cpp
@@ -80,7 +80,6 @@ TEST_F(DramPowerTest_DDR5_16, Test)
         ddr->doCoreCommand(command);
     };
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_17.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_17.cpp
index c5c209af..0df9f822 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_17.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_17.cpp
@@ -81,7 +81,6 @@ TEST_F(DramPowerTest_DDR5_17, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_18.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_18.cpp
index c66e9c20..0cbaa401 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_18.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_18.cpp
@@ -82,7 +82,6 @@ TEST_F(DramPowerTest_DDR5_18, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
@@ -134,9 +133,6 @@ TEST_F(DramPowerTest_DDR5_18, CalcWindow)
 	auto command = testPattern.begin();
 
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 5
 	window = iterate_to_timestamp(command, 5);
 	ASSERT_EQ(window.rank_total[0].cycles.act, 5);
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_2.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_2.cpp
index aa0f6782..fff226db 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_2.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_2.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -51,17 +52,17 @@ TEST_F(DramPowerTest_DDR5_2, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -70,12 +71,12 @@ TEST_F(DramPowerTest_DDR5_2, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 50);
 }
 
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_3.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_3.cpp
index d837a0f5..36f8c46c 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_3.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_3.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -52,7 +53,7 @@ TEST_F(DramPowerTest_DDR5_3, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -60,7 +61,7 @@ TEST_F(DramPowerTest_DDR5_3, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
@@ -68,7 +69,7 @@ TEST_F(DramPowerTest_DDR5_3, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_DDR5_3, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 5);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 35);
         else if(b == 3)
@@ -90,7 +91,7 @@ TEST_F(DramPowerTest_DDR5_3, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 15);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_4.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_4.cpp
index 411e575a..fc76e070 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_4.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_4.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_DDR5_4, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,7 +62,7 @@ TEST_F(DramPowerTest_DDR5_4, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if( b == 3)
@@ -71,7 +72,7 @@ TEST_F(DramPowerTest_DDR5_4, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -83,7 +84,7 @@ TEST_F(DramPowerTest_DDR5_4, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_DDR5_4, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_5.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_5.cpp
index 384e8e71..3b945233 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_5.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_5.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -54,7 +55,7 @@ TEST_F(DramPowerTest_DDR5_5, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -62,7 +63,7 @@ TEST_F(DramPowerTest_DDR5_5, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if( b == 3)
@@ -72,7 +73,7 @@ TEST_F(DramPowerTest_DDR5_5, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_DDR5_5, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -89,7 +90,7 @@ TEST_F(DramPowerTest_DDR5_5, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 75);
         else if(b == 3)
@@ -99,7 +100,7 @@ TEST_F(DramPowerTest_DDR5_5, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 25);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_6.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_6.cpp
index e4b084f3..240fb29f 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_6.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_6.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_DDR5_6, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,14 +62,14 @@ TEST_F(DramPowerTest_DDR5_6, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 3)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
             ASSERT_EQ(stats.bank[b].counter.reads, 0);
     }
 
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.readAuto, 1);
         else
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_DDR5_6, Counters_and_Cycles){
     }
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -84,7 +85,7 @@ TEST_F(DramPowerTest_DDR5_6, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_DDR5_6, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 45);
         else if(b == 3)
@@ -103,7 +104,7 @@ TEST_F(DramPowerTest_DDR5_6, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 55);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_7.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_7.cpp
index f3610fa6..f2dba591 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_7.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_7.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -49,10 +50,10 @@ TEST_F(DramPowerTest_DDR5_7, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
 
 
     // Check cycles count
@@ -61,13 +62,13 @@ TEST_F(DramPowerTest_DDR5_7, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.selfRefresh, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
 }
 
 TEST_F(DramPowerTest_DDR5_7, Energy) {
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_8.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_8.cpp
index 4e7176aa..c7660998 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_8.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_8.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -59,19 +60,19 @@ TEST_F(DramPowerTest_DDR5_8, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 25);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_DDR5_8, Energy) {
diff --git a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_9.cpp b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_9.cpp
index df7f2f61..837445fd 100644
--- a/tests/tests_drampower/core/DDR5/ddr5_test_pattern_9.cpp
+++ b/tests/tests_drampower/core/DDR5/ddr5_test_pattern_9.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -65,7 +66,7 @@ TEST_F(DramPowerTest_DDR5_9, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats .bank[b].cycles.act, 45);
         }else if (b == 5){
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_DDR5_9, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         }else if (b == 5){
@@ -87,13 +88,13 @@ TEST_F(DramPowerTest_DDR5_9, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_DDR5_9, Energy) {
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_multidevice_tests.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_multidevice_tests.cpp
index c4f2037f..377b1142 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_multidevice_tests.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_multidevice_tests.cpp
@@ -31,6 +31,7 @@ Total * 5:				22101.923076923081
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -79,7 +80,7 @@ TEST_F(DramPowerTest_LPDDR4_MultiDevice, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -87,7 +88,7 @@ TEST_F(DramPowerTest_LPDDR4_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if(b == 3)
@@ -97,7 +98,7 @@ TEST_F(DramPowerTest_LPDDR4_MultiDevice, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -109,7 +110,7 @@ TEST_F(DramPowerTest_LPDDR4_MultiDevice, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -119,7 +120,7 @@ TEST_F(DramPowerTest_LPDDR4_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_0.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_0.cpp
index a0d73a5d..8d6302cb 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_0.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_0.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -49,7 +50,7 @@ TEST_F(DramPowerTest_LPDDR4_0, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
 
     // Check cycles count
@@ -58,12 +59,12 @@ TEST_F(DramPowerTest_LPDDR4_0, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 15);
 }
 
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_1.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_1.cpp
index e6332251..24e1403a 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_1.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_1.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -50,17 +51,17 @@ TEST_F(DramPowerTest_LPDDR4_1, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -69,12 +70,12 @@ TEST_F(DramPowerTest_LPDDR4_1, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 35);
 }
 
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_10.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_10.cpp
index 321ce74b..0ea80c13 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_10.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_10.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -61,7 +62,7 @@ TEST_F(DramPowerTest_LPDDR4_10, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 0);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats .bank[b].cycles.act, 30);
         }else if (b == 2){
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_LPDDR4_10, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 70);
         }else if (b == 2){
@@ -91,13 +92,13 @@ TEST_F(DramPowerTest_LPDDR4_10, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_LPDDR4_10, Energy) {
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_14.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_14.cpp
index fdec694d..02690ca4 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_14.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_14.cpp
@@ -79,7 +79,6 @@ TEST_F(DramPowerTest_LPDDR4_14, Test)
         ddr->doCoreCommand(command);
     };
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_15.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_15.cpp
index 6a3f09fc..f27ab3ba 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_15.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_15.cpp
@@ -85,7 +85,6 @@ TEST_F(DramPowerTest_LPDDR4_15, Test)
         ddr->doCoreCommand(command);
     };
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_16.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_16.cpp
index 2a63b285..4e0b2588 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_16.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_16.cpp
@@ -83,7 +83,6 @@ TEST_F(DramPowerTest_LPDDR4_16, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_17.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_17.cpp
index 5e6cedcc..52eeacaf 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_17.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_17.cpp
@@ -84,7 +84,6 @@ TEST_F(DramPowerTest_LPDDR4_17, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
@@ -136,9 +135,6 @@ TEST_F(DramPowerTest_LPDDR4_17, CalcWindow)
 	auto command = testPattern.begin();
 
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 5
 	window = iterate_to_timestamp(command, 5);
 	ASSERT_EQ(window.rank_total[0].cycles.act, 5);
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_18.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_18.cpp
index 623fbd17..7ca9fef8 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_18.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_18.cpp
@@ -82,7 +82,6 @@ TEST_F(DramPowerTest_LPDDR4_18, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
@@ -131,9 +130,6 @@ TEST_F(DramPowerTest_LPDDR4_18, CalcWindow)
 	auto command = testPattern.begin();
 
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 5
 	window = iterate_to_timestamp(command, 5);
 	ASSERT_EQ(window.rank_total[0].cycles.act, 5);    ASSERT_EQ(window.rank_total[0].cycles.pre, 0);
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_2.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_2.cpp
index b36bcee8..43042e13 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_2.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_2.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -51,17 +52,17 @@ TEST_F(DramPowerTest_LPDDR4_2, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -70,12 +71,12 @@ TEST_F(DramPowerTest_LPDDR4_2, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 50);
 }
 
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_3.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_3.cpp
index 11561f3a..3b139a03 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_3.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_3.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -52,7 +53,7 @@ TEST_F(DramPowerTest_LPDDR4_3, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -60,7 +61,7 @@ TEST_F(DramPowerTest_LPDDR4_3, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
@@ -68,7 +69,7 @@ TEST_F(DramPowerTest_LPDDR4_3, Counters_and_Cycles){
     }
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_LPDDR4_3, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 5);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 35);
         else if(b == 3)
@@ -90,7 +91,7 @@ TEST_F(DramPowerTest_LPDDR4_3, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 15);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_4.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_4.cpp
index f1235aff..b5649049 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_4.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_4.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_LPDDR4_4, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,7 +62,7 @@ TEST_F(DramPowerTest_LPDDR4_4, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if(b == 3)
@@ -71,7 +72,7 @@ TEST_F(DramPowerTest_LPDDR4_4, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -83,7 +84,7 @@ TEST_F(DramPowerTest_LPDDR4_4, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_LPDDR4_4, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_5.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_5.cpp
index c815bf3b..46fe7b11 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_5.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_5.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -54,7 +55,7 @@ TEST_F(DramPowerTest_LPDDR4_5, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -62,7 +63,7 @@ TEST_F(DramPowerTest_LPDDR4_5, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if( b == 3)
@@ -72,7 +73,7 @@ TEST_F(DramPowerTest_LPDDR4_5, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_LPDDR4_5, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -89,7 +90,7 @@ TEST_F(DramPowerTest_LPDDR4_5, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 75);
         else if(b == 3)
@@ -99,7 +100,7 @@ TEST_F(DramPowerTest_LPDDR4_5, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 25);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_6.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_6.cpp
index ab92f759..57e7699d 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_6.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_6.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_LPDDR4_6, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,14 +62,14 @@ TEST_F(DramPowerTest_LPDDR4_6, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 3)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
             ASSERT_EQ(stats.bank[b].counter.reads, 0);
     }
 
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.readAuto, 1);
         else
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_LPDDR4_6, Counters_and_Cycles){
     }
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -84,7 +85,7 @@ TEST_F(DramPowerTest_LPDDR4_6, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_LPDDR4_6, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -103,7 +104,7 @@ TEST_F(DramPowerTest_LPDDR4_6, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 50);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_7.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_7.cpp
index 63f1fdec..98a4cae3 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_7.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_7.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -49,10 +50,10 @@ TEST_F(DramPowerTest_LPDDR4_7, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
 
 
     // Check cycles count
@@ -61,13 +62,13 @@ TEST_F(DramPowerTest_LPDDR4_7, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.selfRefresh, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
 
 }
 
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_8.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_8.cpp
index 098e3a8a..a0a952ca 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_8.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_8.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -59,19 +60,19 @@ TEST_F(DramPowerTest_LPDDR4_8, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 25);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_LPDDR4_8, Energy) {
diff --git a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_9.cpp b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_9.cpp
index e8402270..bec869ba 100644
--- a/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_9.cpp
+++ b/tests/tests_drampower/core/LPDDR4/lpddr4_test_pattern_9.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -65,7 +66,7 @@ TEST_F(DramPowerTest_LPDDR4_9, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats .bank[b].cycles.act, 45);
         }else if (b == 5){
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_LPDDR4_9, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         }else if (b == 5){
@@ -87,13 +88,13 @@ TEST_F(DramPowerTest_LPDDR4_9, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_LPDDR4_9, Energy) {
diff --git a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_15.cpp b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_15.cpp
index 637b91db..ffee17d1 100644
--- a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_15.cpp
+++ b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_15.cpp
@@ -81,7 +81,6 @@ TEST_F(DramPowerTest_LPDDR5_15, Test)
         ddr->doCoreCommand(command);
     };
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_16.cpp b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_16.cpp
index f663fb44..b68d8e3d 100644
--- a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_16.cpp
+++ b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_16.cpp
@@ -90,7 +90,6 @@ TEST_F(DramPowerTest_LPDDR5_16, Test)
         ddr->doCoreCommand(command);
     };
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_17.cpp b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_17.cpp
index 29ee4669..8a8e42b7 100644
--- a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_17.cpp
+++ b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_17.cpp
@@ -81,7 +81,6 @@ TEST_F(DramPowerTest_LPDDR5_17, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_18.cpp b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_18.cpp
index bc79c5aa..6df531b0 100644
--- a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_18.cpp
+++ b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_18.cpp
@@ -87,7 +87,6 @@ TEST_F(DramPowerTest_LPDDR5_18, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
diff --git a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_19.cpp b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_19.cpp
index a69b2774..05a84c97 100644
--- a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_19.cpp
+++ b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_19.cpp
@@ -87,7 +87,6 @@ TEST_F(DramPowerTest_LPDDR5_19, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
@@ -139,9 +138,6 @@ TEST_F(DramPowerTest_LPDDR5_19, CalcWindow)
 	auto command = testPattern.begin();
 
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 5
 	window = iterate_to_timestamp(command, 5);
 	ASSERT_EQ(window.rank_total[0].cycles.act, 5);
diff --git a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_20.cpp b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_20.cpp
index 848a8241..8d45a295 100644
--- a/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_20.cpp
+++ b/tests/tests_drampower/core/LPDDR5/LPDDR5_test_pattern_20.cpp
@@ -85,7 +85,6 @@ TEST_F(DramPowerTest_LPDDR5_20, Test)
 		ddr->doCoreCommand(command);
 	};
 
-	Rank & rank_1 = ddr->ranks[0];
 	auto stats = ddr->getStats();
 
 	// Check bank command count: ACT
@@ -134,9 +133,6 @@ TEST_F(DramPowerTest_LPDDR5_20, CalcWindow)
 	auto command = testPattern.begin();
 
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 5
 	window = iterate_to_timestamp(command, 5);
 	ASSERT_EQ(window.rank_total[0].cycles.act, 5);    ASSERT_EQ(window.rank_total[0].cycles.pre, 0);
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_multidevice_tests.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_multidevice_tests.cpp
index 9c0e2162..b08e1c9f 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_multidevice_tests.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_multidevice_tests.cpp
@@ -31,6 +31,7 @@ Total * 5:				18709.615384615388
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -79,7 +80,7 @@ TEST_F(DramPowerTest_LPDDR5_MultiDevice, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -87,7 +88,7 @@ TEST_F(DramPowerTest_LPDDR5_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if(b == 3)
@@ -97,7 +98,7 @@ TEST_F(DramPowerTest_LPDDR5_MultiDevice, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -109,7 +110,7 @@ TEST_F(DramPowerTest_LPDDR5_MultiDevice, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -119,7 +120,7 @@ TEST_F(DramPowerTest_LPDDR5_MultiDevice, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_0.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_0.cpp
index 859cfd18..364294c4 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_0.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_0.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -49,7 +50,7 @@ TEST_F(DramPowerTest_LPDDR5_0, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
 
     // Check cycles count
@@ -58,12 +59,12 @@ TEST_F(DramPowerTest_LPDDR5_0, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 15);
 }
 
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_1.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_1.cpp
index 969f8c9f..76387c38 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_1.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_1.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -50,17 +51,17 @@ TEST_F(DramPowerTest_LPDDR5_1, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -69,12 +70,12 @@ TEST_F(DramPowerTest_LPDDR5_1, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 0);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 35);
 }
 
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_10.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_10.cpp
index 3d4ad12f..cab979c7 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_10.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_10.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -62,7 +63,7 @@ TEST_F(DramPowerTest_LPDDR5_10, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 0);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.act, 45);
         }else{
@@ -71,7 +72,7 @@ TEST_F(DramPowerTest_LPDDR5_10, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 30);
         }else{
@@ -80,16 +81,16 @@ TEST_F(DramPowerTest_LPDDR5_10, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 10);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 10);
 
     // Check bank specific DSM cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.deepSleepMode, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.deepSleepMode, 15);
 }
 
 TEST_F(DramPowerTest_LPDDR5_10, Energy) {
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_11.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_11.cpp
index b1e639e1..70276695 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_11.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_11.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -61,7 +62,7 @@ TEST_F(DramPowerTest_LPDDR5_11, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 0);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats .bank[b].cycles.act, 30);
         }else if (b == 2){
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_LPDDR5_11, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 70);
         }else if (b == 2){
@@ -91,13 +92,13 @@ TEST_F(DramPowerTest_LPDDR5_11, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 0);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 0);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_LPDDR5_11, Energy) {
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_2.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_2.cpp
index 4c83e201..d67e5e52 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_2.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_2.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -51,17 +52,17 @@ TEST_F(DramPowerTest_LPDDR5_2, Counters_and_Cycles){
 
     // Check bank command count: ACT
     ASSERT_EQ(stats.bank[0].counter.act, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: RD
     ASSERT_EQ(stats.bank[0].counter.reads, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.reads, 0);
 
     // Check bank command count: PRE
     ASSERT_EQ(stats.bank[0].counter.pre, 1);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].counter.pre, 0);
 
     // Check cycles count
@@ -70,12 +71,12 @@ TEST_F(DramPowerTest_LPDDR5_2, Counters_and_Cycles){
 
     // Check bank specific ACT cycle count
     ASSERT_EQ(stats.bank[0].cycles.act, 35);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
     ASSERT_EQ(stats.bank[0].cycles.pre, 15);
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++)
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++)
         ASSERT_EQ(stats.bank[b].cycles.pre, 50);
 }
 
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_3.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_3.cpp
index bfdc5b39..4f708c23 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_3.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_3.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -52,7 +53,7 @@ TEST_F(DramPowerTest_LPDDR5_3, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -60,7 +61,7 @@ TEST_F(DramPowerTest_LPDDR5_3, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
@@ -68,7 +69,7 @@ TEST_F(DramPowerTest_LPDDR5_3, Counters_and_Cycles){
     }
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_LPDDR5_3, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 5);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 35);
         else if(b == 3)
@@ -90,7 +91,7 @@ TEST_F(DramPowerTest_LPDDR5_3, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 15);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_4.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_4.cpp
index d501879b..a9263aa2 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_4.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_4.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_LPDDR5_4, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,7 +62,7 @@ TEST_F(DramPowerTest_LPDDR5_4, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if(b == 3)
@@ -71,7 +72,7 @@ TEST_F(DramPowerTest_LPDDR5_4, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -83,7 +84,7 @@ TEST_F(DramPowerTest_LPDDR5_4, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 20);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 50);
         else if(b == 3)
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_LPDDR5_4, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_5.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_5.cpp
index be1dc715..564633b5 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_5.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_5.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -54,7 +55,7 @@ TEST_F(DramPowerTest_LPDDR5_5, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -62,7 +63,7 @@ TEST_F(DramPowerTest_LPDDR5_5, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.reads, 2);
         else if( b == 3)
@@ -72,7 +73,7 @@ TEST_F(DramPowerTest_LPDDR5_5, Counters_and_Cycles){
     };
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -80,7 +81,7 @@ TEST_F(DramPowerTest_LPDDR5_5, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -89,7 +90,7 @@ TEST_F(DramPowerTest_LPDDR5_5, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 75);
         else if(b == 3)
@@ -99,7 +100,7 @@ TEST_F(DramPowerTest_LPDDR5_5, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 25);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_6.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_6.cpp
index c1eeba9b..a52b1b3b 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_6.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_6.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -53,7 +54,7 @@ TEST_F(DramPowerTest_LPDDR5_6, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.act, 1);
         else
@@ -61,14 +62,14 @@ TEST_F(DramPowerTest_LPDDR5_6, Counters_and_Cycles){
     }
 
     // Check bank command count: RD
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 3)
             ASSERT_EQ(stats.bank[b].counter.reads, 1);
         else
             ASSERT_EQ(stats.bank[b].counter.reads, 0);
     }
 
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].counter.readAuto, 1);
         else
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_LPDDR5_6, Counters_and_Cycles){
     }
 
     // Check bank command count: PRE
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0 || b == 3)
             ASSERT_EQ(stats.bank[b].counter.pre, 1);
         else
@@ -84,7 +85,7 @@ TEST_F(DramPowerTest_LPDDR5_6, Counters_and_Cycles){
     }
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
     }
 
@@ -93,7 +94,7 @@ TEST_F(DramPowerTest_LPDDR5_6, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.pre, 25);
 
     // Check bank specific ACT cycle count;
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if (b == 0)
             ASSERT_EQ(stats.bank[b].cycles.act, 45);
         else if(b == 3)
@@ -103,7 +104,7 @@ TEST_F(DramPowerTest_LPDDR5_6, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 1; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 1; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0)
             ASSERT_EQ(stats.bank[b].cycles.pre, 55);
         else if (b == 3)
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_7.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_7.cpp
index 1f8b5e5a..b296f4e4 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_7.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_7.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -49,10 +50,10 @@ TEST_F(DramPowerTest_LPDDR5_7, Counters_and_Cycles){
     auto stats = ddr->getStats();
 
     // Check bank command count: ACT
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.act, 0);
 
     // Check bank command count: REFA
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].counter.refAllBank, 1);
 
 
     // Check cycles count
@@ -61,13 +62,13 @@ TEST_F(DramPowerTest_LPDDR5_7, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.selfRefresh, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 25);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 60);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 15);
 
 }
 
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_8.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_8.cpp
index 3c5ff7ce..0b4a8536 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_8.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_8.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -59,19 +60,19 @@ TEST_F(DramPowerTest_LPDDR5_8, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 25);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.act, 0);
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.pre, 30);
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 30);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 25);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_LPDDR5_8, Energy) {
diff --git a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_9.cpp b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_9.cpp
index 6c50729c..ee9a003a 100644
--- a/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_9.cpp
+++ b/tests/tests_drampower/core/LPDDR5/lpddr5_test_pattern_9.cpp
@@ -9,6 +9,7 @@
 #include <DRAMPower/memspec/MemSpec.h>
 #include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
 #include <variant>
+#include <stdint.h>
 
 #include <fstream>
 
@@ -65,7 +66,7 @@ TEST_F(DramPowerTest_LPDDR5_9, Counters_and_Cycles){
     ASSERT_EQ(stats.rank_total[0].cycles.powerDownPre, 15);
 
     // Check bank specific ACT cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats .bank[b].cycles.act, 45);
         }else if (b == 5){
@@ -76,7 +77,7 @@ TEST_F(DramPowerTest_LPDDR5_9, Counters_and_Cycles){
     }
 
     // Check bank specific PRE cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++){
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++){
         if(b == 0){
             ASSERT_EQ(stats.bank[b].cycles.pre, 20);
         }else if (b == 5){
@@ -87,13 +88,13 @@ TEST_F(DramPowerTest_LPDDR5_9, Counters_and_Cycles){
     }
 
     // Check bank specific PDNA cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownAct, 20);
 
     // Check bank specific PDNP cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.powerDownPre, 15);
 
     // Check bank specific SREF cycle count
-    for(auto b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
+    for(uint64_t b = 0; b < ddr->memSpec.numberOfBanks; b++)  ASSERT_EQ(stats.bank[b].cycles.selfRefresh, 0);
 }
 
 TEST_F(DramPowerTest_LPDDR5_9, Energy) {
diff --git a/tests/tests_drampower/interface/test_interface_ddr4.cpp b/tests/tests_drampower/interface/test_interface_ddr4.cpp
index f31fbd1c..7a31bf7b 100644
--- a/tests/tests_drampower/interface/test_interface_ddr4.cpp
+++ b/tests/tests_drampower/interface/test_interface_ddr4.cpp
@@ -132,14 +132,14 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_0) {
     // ("size in bits" / bus_size) / bus_rate
     // read and write have the same length
     // number of cycles per write/read
-    int number_of_cycles = (SZ_BITS(wr_data) / 8) / spec->dataRate;
+    uint64_t number_of_cycles = (SZ_BITS(wr_data) / 8) / spec->dataRate;
 
     // In this example read data and write data are the same size, so stats should be the same
     // DQs modelled as single line
-    int DQS_ones = number_of_cycles * spec->dataRate;
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = number_of_cycles * spec->dataRate;
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
     EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
     EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
@@ -194,12 +194,12 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_1) {
     // DQs bus
     // For write and read the number of clock cycles the strobes stay on is
     // (("number of writes/reads" * "size in bits") / bus_size) / bus_rate
-    int number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
+    uint64_t number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
 
-    int DQS_ones = number_of_cycles * spec->dataRate;
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = number_of_cycles * spec->dataRate;
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
     EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
     EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
@@ -251,13 +251,13 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_2) {
     // DQs bus
     // For write and read the number of clock cycles the strobes stay on is
     // (("number of reads/writes" * "size in bits") / bus_size) / bus_rate
-    int number_of_cycles = ((2 * SZ_BITS(rd_data)) / 8) / spec->dataRate;
+    uint64_t number_of_cycles = ((2 * SZ_BITS(rd_data)) / 8) / spec->dataRate;
 
     // Only read
-    int DQS_ones = number_of_cycles * spec->dataRate;
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = number_of_cycles * spec->dataRate;
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
     EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
     EXPECT_EQ(stats.readDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
@@ -309,13 +309,13 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_3) {
     // DQs bus
     // For write and read the number of clock cycles the strobes stay on is
     // (("number of writes/reads" * "size in bits") / bus_size) / bus_rate
-    int number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
+    uint64_t number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
 
     // Only writes
-    int DQS_ones = number_of_cycles * spec->dataRate;
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = number_of_cycles * spec->dataRate;
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
     EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
     EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
@@ -367,13 +367,13 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_4) {
     // DQs bus
     // For write and read the number of clock cycles the strobes stay on is
     // (("number of writes/reads" * "size in bits") / bus_size) / bus_rate
-    int number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
+    uint64_t number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
 
     // Only reads
-    int DQS_ones = number_of_cycles * spec->dataRate;
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = number_of_cycles * spec->dataRate;
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
     EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
     EXPECT_EQ(stats.readDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
@@ -450,7 +450,7 @@ TEST_F(DDR4_Energy_Tests, Parameters) {
 
 // Test pattern for energy consumption
 TEST_F(DDR4_Energy_Tests, Clock_Energy) {
-    SimulationStats stats = {0};
+    SimulationStats stats;
     stats.clockStats.ones = 200;
     stats.clockStats.zeroes_to_ones = 200;
 
@@ -594,8 +594,8 @@ TEST_F(DDR4_Energy_Tests, PrePostamble_Energy) {
     stats.rank_total[0].counter.writes = 6;
     stats.rank_total[0].counter.writeAuto = 11;
 
-    double writecount = stats.rank_total[0].counter.writes + stats.rank_total[0].counter.writeAuto;
-    double readcount = stats.rank_total[0].counter.reads + stats.rank_total[0].counter.readAuto;
+    uint64_t writecount = stats.rank_total[0].counter.writes + stats.rank_total[0].counter.writeAuto;
+    uint64_t readcount = stats.rank_total[0].counter.reads + stats.rank_total[0].counter.readAuto;
 
     // Dynamic power is consumed on 0 -> 1 transition
     double expected_dynamic_controller = stats.writeDQSStats.zeroes_to_ones *
diff --git a/tests/tests_drampower/interface/test_interface_ddr5.cpp b/tests/tests_drampower/interface/test_interface_ddr5.cpp
index 1145b69b..482c0a36 100644
--- a/tests/tests_drampower/interface/test_interface_ddr5.cpp
+++ b/tests/tests_drampower/interface/test_interface_ddr5.cpp
@@ -110,14 +110,14 @@ TEST_F(DDR5_WindowStats_Tests, Pattern_0) {
 
     // For write and read the number of clock cycles the strobes stay on is
     // currently ("size in bits" / bus_size) / bus_rate
-    int number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
+    uint64_t number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
 
     // In this example read data and write data are the same size, so stats should be the same
     uint_fast8_t dqspairs = 2 ? spec->bitWidth == 16 : 1;
-    int DQS_ones = dqspairs * number_of_cycles * spec->dataRate * 2; // Differential_Pairs * cycles * datarate * 2(Differential Pair)
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = dqspairs * number_of_cycles * spec->dataRate * 2; // Differential_Pairs * cycles * datarate * 2(Differential Pair)
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
     EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
     EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
diff --git a/tests/tests_drampower/interface/test_interface_lpddr4.cpp b/tests/tests_drampower/interface/test_interface_lpddr4.cpp
index a5465415..5803f3a8 100644
--- a/tests/tests_drampower/interface/test_interface_lpddr4.cpp
+++ b/tests/tests_drampower/interface/test_interface_lpddr4.cpp
@@ -136,8 +136,6 @@ class DramPowerTest_Interface_LPDDR4 : public ::testing::Test {
 
 TEST_F(DramPowerTest_Interface_LPDDR4, TestStats)
 {
-	Rank & rank_1 = ddr->ranks[0];
-
 	for (const auto& command : testPattern) {
 		ddr->doCoreCommand(command);
 		ddr->doInterfaceCommand(command);
@@ -167,8 +165,6 @@ TEST_F(DramPowerTest_Interface_LPDDR4, TestStats)
 
 TEST_F(DramPowerTest_Interface_LPDDR4, TestPower)
 {
-	Rank& rank_1 = ddr->ranks[0];
-
 	for (const auto& command : testPattern) {
 		ddr->doCoreCommand(command);
 		ddr->doInterfaceCommand(command);
@@ -180,14 +176,12 @@ TEST_F(DramPowerTest_Interface_LPDDR4, TestPower)
 
 	InterfacePowerCalculation_LPPDR4 interface_calc(this->ddr->memSpec);
 
-	auto interface_stats = interface_calc.calcEnergy(stats);
-	auto dqs_stats = interface_calc.calcDQSEnergy(stats);
+	// auto interface_stats = interface_calc.calcEnergy(stats);
+	// auto dqs_stats = interface_calc.calcDQSEnergy(stats);
 }
 
 TEST_F(DramPowerTest_Interface_LPDDR4, TestDQS)
 {
-	Rank& rank_1 = ddr->ranks[0];
-
 	for (const auto& command : testPattern_2) {
 		auto stats = ddr->getWindowStats(command.timestamp);
 
@@ -219,9 +213,6 @@ TEST_F(DramPowerTest_Interface_LPDDR4, Test_Detailed)
 		return this->ddr->getWindowStats(timestamp);
 	};
 
-	// Inspect first rank
-	auto & rank_1 = ddr->ranks[0];
-
 	// Cycle 0 to 0 (0 delta)
 	window = iterate_to_timestamp(0);
 	ASSERT_EQ(window.commandBus.ones, 0);
diff --git a/tests/tests_drampower/interface/test_interface_lpddr5.cpp b/tests/tests_drampower/interface/test_interface_lpddr5.cpp
index af11ad41..0ba8a4ec 100644
--- a/tests/tests_drampower/interface/test_interface_lpddr5.cpp
+++ b/tests/tests_drampower/interface/test_interface_lpddr5.cpp
@@ -137,12 +137,12 @@ TEST_F(LPDDR5_WindowStats_Tests, Pattern_0) {
 
     // For read the number of clock cycles the strobes stay on is
     // currently ("size in bits" / bus_size) / bus_rate
-    int number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
+    uint64_t number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
 
-    int DQS_ones = number_of_cycles * spec->dataRate;
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = number_of_cycles * spec->dataRate;
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
 
     EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
@@ -309,12 +309,12 @@ TEST_F(LPDDR5_WindowStats_Tests, Pattern_3_BG_Mode) {
     EXPECT_EQ(stats.commandBus.ones_to_zeroes, 21);
     EXPECT_EQ(stats.commandBus.zeroes_to_ones, 21);
 
-    int number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
+    uint64_t number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
 
-    int DQS_ones = number_of_cycles * spec->dataRate;
-    int DQS_zeros = DQS_ones;
-    int DQS_zeros_to_ones = DQS_ones;
-    int DQS_ones_to_zeros = DQS_zeros;
+    uint64_t DQS_ones = number_of_cycles * spec->dataRate;
+    uint64_t DQS_zeros = DQS_ones;
+    uint64_t DQS_zeros_to_ones = DQS_ones;
+    uint64_t DQS_ones_to_zeros = DQS_zeros;
 
     EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
     EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
diff --git a/tests/tests_misc/CMakeLists.txt b/tests/tests_misc/CMakeLists.txt
index 33732766..e68e6c5f 100644
--- a/tests/tests_misc/CMakeLists.txt
+++ b/tests/tests_misc/CMakeLists.txt
@@ -2,7 +2,7 @@
 ###              tests_misc                 ###
 ###############################################
 
-cmake_minimum_required(VERSION 3.1.0)
+cmake_minimum_required(VERSION 3.5.0)
 
 project(tests_misc)
 
diff --git a/tests/tests_misc/test_bus.cpp b/tests/tests_misc/test_bus.cpp
index 979be263..2ed837f2 100644
--- a/tests/tests_misc/test_bus.cpp
+++ b/tests/tests_misc/test_bus.cpp
@@ -658,14 +658,14 @@ TEST_F(BusTest, Load_Data)
 
 TEST_F(BusTest, Test_001)
 {
-	constexpr uint8_t data[] = {
-		0b1010'0000,
-		0b0000'0100,
-		0b0010'0110,
-		0b0001'0000,
-		0b0000'0000,
-		0b1000'0010,
-	};
+	// constexpr uint8_t data[] = {
+	// 	0b1010'0000,
+	// 	0b0000'0100,
+	// 	0b0010'0110,
+	// 	0b0001'0000,
+	// 	0b0000'0000,
+	// 	0b1000'0010,
+	// };
 
 	std::bitset<6 * 4> cmd_1("100000100000000000010000");
 	std::bitset<6 * 4> cmd_2("001001100000010010100000");
diff --git a/tests/tests_misc/test_bus_extended.cpp b/tests/tests_misc/test_bus_extended.cpp
index c7ffb3df..6bead16a 100644
--- a/tests/tests_misc/test_bus_extended.cpp
+++ b/tests/tests_misc/test_bus_extended.cpp
@@ -3,6 +3,7 @@
 #include <DRAMPower/util/bus.h>
 #include <array>
 #include <optional>
+#include <algorithm>
 
 using namespace DRAMPower;
 
@@ -17,7 +18,7 @@ class ExtendedBusIdlePatternTest : public ::testing::Test {
 
 	virtual void SetUp()
 	{
-		for(int i = 0; i < buswidth; i++)
+		for(size_t i = 0; i < buswidth; i++)
 		{
 			burst_ones.push_back(true);
 			burst_zeroes.push_back(false);
@@ -128,7 +129,7 @@ TEST_F(ExtendedBusIdlePatternTest, Load_Width_64)
 	auto expected = util::Bus::burst_t();
 
 	auto pattern_gen = [] (size_t i) -> uint8_t {
-		return i;
+		return static_cast<uint8_t>(i);
 	};
 
 	// Load bus
@@ -161,7 +162,7 @@ TEST_F(ExtendedBusIdlePatternTest, Load_Width_512)
 	auto expected = util::Bus::burst_t();
 
 	auto pattern_gen = [] (size_t i) -> uint8_t {
-		return i;
+		return static_cast<uint8_t>(i);
 	};
 
 	// Load bus
@@ -194,7 +195,7 @@ class ExtendedBusStatsTest : public ::testing::Test {
 
 	virtual void SetUp()
 	{
-		for(int i = 0; i < buswidth; i++)
+		for(size_t i = 0; i < buswidth; i++)
 		{
 			burst_ones.push_back(true);
 			burst_zeroes.push_back(false);
@@ -212,14 +213,6 @@ TEST_F(ExtendedBusStatsTest, Stats_Pattern_Datarate_1)
 	uint_fast8_t datarate = 2;
 	timestamp_t timestamp = 3;
 	util::Bus bus(buswidth, datarate, util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L);
-	std::size_t custom_ones = burst_custom.count();
-	std::size_t custom_zeroes = buswidth - custom_ones;
-	uint8_t burst_ones_data[bus_array_size] = { 0xFF };
-	uint8_t burst_zeroes_data[bus_array_size] = { 0 };
-
-	for(auto i = 0; i < bus_array_size; i++) {
-		burst_ones_data[i] = 0xFF;
-	}
 
 	ASSERT_EQ(buswidth, 128);
 
@@ -236,14 +229,6 @@ TEST_F(ExtendedBusStatsTest, Stats_Pattern_Datarate_2)
 	uint_fast8_t datarate = 13;
 	timestamp_t timestamp = 47;
 	util::Bus bus(buswidth, datarate, util::Bus::BusIdlePatternSpec::L, util::Bus::BusInitPatternSpec::L);
-	std::size_t custom_ones = burst_custom.count();
-	std::size_t custom_zeroes = buswidth - custom_ones;
-	uint8_t burst_ones_data[bus_array_size] = { 0xFF };
-	uint8_t burst_zeroes_data[bus_array_size] = { 0 };
-
-	for(auto i = 0; i < bus_array_size; i++) {
-		burst_ones_data[i] = 0xFF;
-	}
 
 	ASSERT_EQ(buswidth, 128);
 
@@ -260,12 +245,8 @@ TEST_F(ExtendedBusStatsTest, Stats_Pattern_1)
 	util::Bus bus(buswidth, 1, util::Bus::BusIdlePatternSpec::L, burst_custom);
 	std::size_t custom_ones = burst_custom.count();
 	std::size_t custom_zeroes = buswidth - custom_ones;
-	uint8_t burst_ones_data[bus_array_size] = { 0xFF };
-	uint8_t burst_zeroes_data[bus_array_size] = { 0 };
-
-	for(auto i = 0; i < bus_array_size; i++) {
-		burst_ones_data[i] = 0xFF;
-	}
+	uint8_t burst_ones_data[bus_array_size];
+	std::fill_n(burst_ones_data, bus_array_size, 0xFF);
 
 	ASSERT_EQ(buswidth, 128);
 	ASSERT_EQ(custom_ones, 85);
@@ -323,12 +304,8 @@ TEST_F(ExtendedBusStatsTest, Stats_Pattern_2)
 	util::Bus bus(buswidth, 1, util::Bus::BusIdlePatternSpec::LAST_PATTERN, burst_custom);
 	std::size_t custom_ones = burst_custom.count();
 	std::size_t custom_zeroes = buswidth - custom_ones;
-	uint8_t burst_ones_data[bus_array_size] = { 0xFF };
-	uint8_t burst_zeroes_data[bus_array_size] = { 0 };
-
-	for(auto i = 0; i < bus_array_size; i++) {
-		burst_ones_data[i] = 0xFF;
-	}
+	uint8_t burst_ones_data[bus_array_size];
+	std::fill_n(burst_ones_data, bus_array_size, 0xFF);
 
 	ASSERT_EQ(buswidth, 128);
 	ASSERT_EQ(custom_ones, 85);
diff --git a/tests/tests_misc/test_misc.cpp b/tests/tests_misc/test_misc.cpp
index 89b92d47..1e5d9a11 100644
--- a/tests/tests_misc/test_misc.cpp
+++ b/tests/tests_misc/test_misc.cpp
@@ -81,7 +81,6 @@ TEST_F(MiscTest, TestChunking)
 	};
 
 	// Test setup
-	constexpr std::size_t width = 6;
 	util::burst_storage burst_storage(6);
 
 	burst_storage.insert_data(data.data(), data.size() * 8);