diff --git a/src/main/scala/chiseltest/coverage/AliasAnalysis.scala b/src/main/scala/chiseltest/coverage/AliasAnalysis.scala new file mode 100644 index 000000000..c02415451 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/AliasAnalysis.scala @@ -0,0 +1,184 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import chiseltest.coverage.Builder.getKind +import firrtl2._ +import firrtl2.analyses.InstanceKeyGraph +import firrtl2.analyses.InstanceKeyGraph.InstanceKey + +import scala.collection.mutable + +/** Analyses which signals in a module always have the same value (are aliases of each other). + * + * @note + * will only work on low firrtl! + * @note + * right now this isn't an actual firrtl pass, but an analysis called into from a firrtl pass. + */ +object AliasAnalysis { + type Aliases = Seq[List[String]] + type Result = Map[String, Aliases] + + /** @return map from module name to signals in the module that alias */ + def findAliases(c: ir.Circuit, iGraph: InstanceKeyGraph): Result = { + // analyze each module in isolation + val local = c.modules.map(m => m.name -> findAliases(m)).toMap + + // compute global results + val moduleOrderBottomUp = iGraph.moduleOrder.reverseIterator + val childInstances = iGraph.getChildInstances.toMap + val portAliases = mutable.HashMap[String, PortAliases]() + + val aliases = moduleOrderBottomUp.map { + case m: ir.Module => + val groups = resolveAliases(m, local(m.name), portAliases, childInstances(m.name)) + val isPort = m.ports.map(_.name).toSet + portAliases(m.name) = computePortAliases(groups, isPort) + m.name -> groups + case other => + portAliases(other.name) = List() + other.name -> List() + } + + aliases.toMap + } + + private type PortAliases = List[(String, String)] + + // Incorporate the alias information from all sub modules. + // This matters if the submodule has an input and an output that aliases. + private def resolveAliases( + m: ir.Module, + local: LocalInfo, + portAliases: String => PortAliases, + instances: Seq[InstanceKey] + ): Seq[List[String]] = { + // compute any port aliases for all child modules + val instancePortAliases = instances.flatMap { case InstanceKey(name, module) => + portAliases(module).map { case (a, b) => + (name + "." + a) -> (name + "." + b) + } + }.toMap + + // if there are no port aliases in the children, nothing is going to change + if (instancePortAliases.isEmpty) return local.groups + + // we need to create a new group for signals that are not aliased when just looking at the local module, + // but are aliased through a connection in a submodule + val isAliasedPort = instancePortAliases.flatMap { case (a, b) => List(a, b) }.toSet + val isGroupedSignal = local.groups.flatten.toSet + val singleSignalGroups = (isAliasedPort -- isGroupedSignal).toList.sorted.map(List(_)) + val localGroups = local.groups ++ singleSignalGroups + + // build a map from (aliasing) instance port to group id + val localGroupsWithIds = localGroups.zipWithIndex + val instPortToGroupId = localGroupsWithIds.flatMap { case (g, ii) => + val ips = g.filter(isAliasedPort(_)) + ips.map(i => i -> ii) + }.toMap + + // check to see if there are any groups that need to be merged + val merges = findMerges(instancePortAliases, instPortToGroupId) + val updatedGroups = mergeGroups(localGroups, merges) + + updatedGroups + } + + private def computePortAliases(groups: Seq[List[String]], isPort: String => Boolean): PortAliases = { + groups.flatMap { g => + val ports = g.filter(isPort) + assert(ports.length < 32, s"Unexpected exponential blowup! Redesign the data-structure! $ports") + ports.flatMap { a => + ports.flatMap { b => + if (a == b) None else Some(a -> b) + } + } + }.toList + } + + private def findMerges(aliases: Iterable[(String, String)], signalToGroupId: Map[String, Int]): List[Set[Int]] = { + // check to see if there are any groups that need to be merged + var merges = List[Set[Int]]() + aliases.foreach { case (a, b) => + val (aId, bId) = (signalToGroupId(a), signalToGroupId(b)) + if (aId != bId) { + val merge = Set(aId, bId) + // update merges + val bothNew = !merges.exists(s => (s & merge).nonEmpty) + if (bothNew) { + merges = merge +: merges + } else { + merges = merges.map { old => + if ((old & merge).nonEmpty) { old | merge } + else { old } + }.distinct + } + } + } + merges + } + + private def mergeGroups(groups: Seq[List[String]], merges: List[Set[Int]]): Seq[List[String]] = { + if (merges.isEmpty) { groups } + else { + val merged = merges.map { m => + m.toList.sorted.flatMap(i => groups(i)) + } + val wasMerged = merges.flatten.toSet + val unmerged = groups.indices.filterNot(wasMerged).map(i => groups(i)) + merged ++ unmerged + } + } + + private def findAliases(m: ir.DefModule): LocalInfo = m match { + case mod: ir.Module => findAliasesM(mod) + case _ => LocalInfo(List()) + } + + private type Connects = mutable.HashMap[String, String] + private def findAliasesM(m: ir.Module): LocalInfo = { + // find all signals inside the module that alias + val cons = new Connects() + m.foreachStmt(onStmt(_, cons)) + val groups = groupSignals(cons) + // groups.foreach(g => println(g.mkString(" <-> "))) + LocalInfo(groups) + } + private def groupSignals(cons: Connects): Seq[List[String]] = { + val signalToGroup = mutable.HashMap[String, Int]() + val groups = mutable.ArrayBuffer[List[String]]() + val signals = (cons.keys.toSet | cons.values.toSet).toSeq + signals.foreach { sig => + signalToGroup.get(sig) match { + case Some(groupId) => + // we have seen this signal before, so all alias info is up to date and we just need to add it to the group! + groups(groupId) = sig +: groups(groupId) + case None => + // check to see if any group exists under any alias name + val aliases = getAliases(sig, cons) + val groupId = aliases.find(a => signalToGroup.contains(a)) match { + case Some(key) => signalToGroup(key) + case None => groups.append(List()); groups.length - 1 + } + groups(groupId) = sig +: groups(groupId) + aliases.foreach(a => signalToGroup(a) = groupId) + } + } + groups.toSeq + } + private def getAliases(name: String, cons: Connects): List[String] = cons.get(name) match { + case None => List(name) + case Some(a) => name +: getAliases(a, cons) + } + private def onStmt(s: ir.Statement, cons: Connects): Unit = s match { + case ir.DefNode(_, lhs, rhs: ir.RefLikeExpression) => + cons(lhs) = rhs.serialize + case ir.Connect(_, lhs: ir.RefLikeExpression, rhs: ir.RefLikeExpression) if getKind(lhs) != RegKind => + cons(lhs.serialize) = rhs.serialize + case other => other.foreachStmt(onStmt(_, cons)) + } + private case class LocalInfo(groups: Seq[List[String]]) +} diff --git a/src/main/scala/chiseltest/coverage/Builder.scala b/src/main/scala/chiseltest/coverage/Builder.scala new file mode 100644 index 000000000..798077211 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/Builder.scala @@ -0,0 +1,150 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.annotations.{IsModule, ReferenceTarget} +import firrtl2.logger.Logger + +import scala.collection.mutable + +/** Helps us construct well typed low-ish firrtl. Some of these convenience functions could be moved to firrtl at some + * point. + */ +object Builder { + + /** Fails if there isn't exactly one Clock input */ + def findClock(m: ir.Module): ir.RefLikeExpression = { + val clocks = findClocks(m) + assert( + clocks.length == 1, + s"[${m.name}] This transformation only works if there is exactly one clock.\n" + + s"Found: ${clocks.map(_.serialize)}\n" + ) + clocks.head + } + + def findClock(mod: ir.Module, logger: Logger): Option[ir.RefLikeExpression] = { + val clocks = Builder.findClocks(mod) + if (clocks.isEmpty) { + logger.warn(s"WARN: [${mod.name}] found no clock input, skipping ...") + } + if (clocks.length > 1) { + logger.warn( + s"WARN: [${mod.name}] found more than one clock, picking the first one: " + clocks + .map(_.serialize) + .mkString(", ") + ) + } + clocks.headOption + } + + def findClocks(m: ir.Module): Seq[ir.RefLikeExpression] = { + val ports = flattenedPorts(m.ports) + val clockIO = ports.filter(_.tpe == ir.ClockType) + val clockInputs = clockIO.filter(_.flow == SourceFlow) + + val isAsyncQueue = m.name == "AsyncQueue" || m.name.startsWith("AsyncQueue_") + if (isAsyncQueue) { + // The "clock" input of the AsyncQueue from rocketchip is unused + // thus, even if both sides of the AsyncQueue are in the same clock domain (which is an assumption that we make) + // using "clock" will lead to counters that never increment. + // Using any of the other clocks is fine! + clockInputs.filterNot(_.serialize == "clock") + } else { + clockInputs + } + } + + def refToTarget(module: IsModule, ref: ir.RefLikeExpression): ReferenceTarget = ref match { + case ir.Reference(name, _, _, _) => module.ref(name) + case ir.SubField(expr, name, _, _) => refToTarget(module, expr.asInstanceOf[ir.RefLikeExpression]).field(name) + case ir.SubIndex(expr, value, _, _) => refToTarget(module, expr.asInstanceOf[ir.RefLikeExpression]).index(value) + case other => throw new RuntimeException(s"Unsupported reference expression: $other") + } + + private def flattenedPorts(ports: Seq[ir.Port]): Seq[ir.RefLikeExpression] = { + ports.flatMap { p => expandRef(ir.Reference(p.name, p.tpe, PortKind, Utils.to_flow(p.direction))) } + } + + private def expandRef(ref: ir.RefLikeExpression): Seq[ir.RefLikeExpression] = ref.tpe match { + case ir.BundleType(fields) => + Seq(ref) ++ fields.flatMap(f => expandRef(ir.SubField(ref, f.name, f.tpe, Utils.times(f.flip, ref.flow)))) + case _ => Seq(ref) + } + + def findResets(m: ir.Module): Seq[ir.RefLikeExpression] = { + val ports = flattenedPorts(m.ports) + val inputs = ports.filter(_.flow == SourceFlow) + val ofResetType = inputs.filter(p => p.tpe == ir.AsyncResetType || p.tpe == ir.ResetType) + val boolWithCorrectName = inputs.filter(p => p.tpe == ir.UIntType(ir.IntWidth(1)) && p.serialize.endsWith("reset")) + val resetInputs = ofResetType ++ boolWithCorrectName + resetInputs + } + + def reduceAnd(e: ir.Expression): ir.Expression = ir.DoPrim(PrimOps.Andr, List(e), List(), Utils.BoolType) + + def add(a: ir.Expression, b: ir.Expression): ir.Expression = { + val (aWidth, bWidth) = (getWidth(a.tpe), getWidth(b.tpe)) + val resultWidth = Seq(aWidth, bWidth).max + val (aPad, bPad) = (pad(a, resultWidth), pad(b, resultWidth)) + val res = ir.DoPrim(PrimOps.Add, List(aPad, bPad), List(), withWidth(a.tpe, resultWidth + 1)) + ir.DoPrim(PrimOps.Bits, List(res), List(resultWidth - 1, 0), withWidth(a.tpe, resultWidth)) + } + + def pad(e: ir.Expression, to: BigInt): ir.Expression = { + val from = getWidth(e.tpe) + require(to >= from) + if (to == from) { e } + else { ir.DoPrim(PrimOps.Pad, List(e), List(to), withWidth(e.tpe, to)) } + } + + def withWidth(tpe: ir.Type, width: BigInt): ir.Type = tpe match { + case ir.UIntType(_) => ir.UIntType(ir.IntWidth(width)) + case ir.SIntType(_) => ir.SIntType(ir.IntWidth(width)) + case other => throw new RuntimeException(s"Cannot change the width of $other!") + } + + def getWidth(tpe: ir.Type): BigInt = firrtl2.bitWidth(tpe) + + def makeRegister( + stmts: mutable.ListBuffer[ir.Statement], + info: ir.Info, + name: String, + tpe: ir.Type, + clock: ir.Expression, + next: ir.Expression, + reset: ir.Expression = Utils.False(), + init: Option[ir.Expression] = None + ): ir.Reference = { + if (isAsyncReset(reset)) { + val initExpr = init.getOrElse(ir.Reference(name, tpe, RegKind)) + val reg = ir.DefRegister(info, name, tpe, clock, reset, initExpr) + stmts.append(reg) + stmts.append(ir.Connect(info, ir.Reference(reg), next)) + ir.Reference(reg) + } else { + val ref = ir.Reference(name, tpe, RegKind, UnknownFlow) + stmts.append(ir.DefRegister(info, name, tpe, clock, Utils.False(), ref)) + init match { + case Some(value) => stmts.append(ir.Connect(info, ref, Utils.mux(reset, value, next))) + case None => stmts.append(ir.Connect(info, ref, next)) + } + ref + } + } + + def isAsyncReset(reset: ir.Expression): Boolean = reset.tpe match { + case ir.AsyncResetType => true + case _ => false + } + + def getKind(ref: ir.RefLikeExpression): firrtl2.Kind = ref match { + case ir.Reference(_, _, kind, _) => kind + case ir.SubField(expr, _, _, _) => getKind(expr.asInstanceOf[ir.RefLikeExpression]) + case ir.SubIndex(expr, _, _, _) => getKind(expr.asInstanceOf[ir.RefLikeExpression]) + case ir.SubAccess(expr, _, _, _) => getKind(expr.asInstanceOf[ir.RefLikeExpression]) + } +} diff --git a/src/main/scala/chiseltest/coverage/CodeBase.scala b/src/main/scala/chiseltest/coverage/CodeBase.scala new file mode 100644 index 000000000..b4a66a0c8 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/CodeBase.scala @@ -0,0 +1,76 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2.logger.LazyLogging + +import scala.collection.mutable + +/** Represents a Scala code base. */ +class CodeBase(val root: os.Path) extends LazyLogging { + def this() = this(CodeBase.chiselRootGuess) + require(os.exists(root), s"Could not find root directory: $root") + require(os.isDir(root), s"Is not a directory: $root") + + val index = CodeBase.index(root) + + /** returns None if the key is not unique */ + def getLine(key: String, line: Int): Option[String] = { + require(line > 0) + getSource(key).map(_(line - 1)) + } + + private val sourceCache = mutable.HashMap[os.RelPath, IndexedSeq[String]]() + def getSource(key: String): Option[IndexedSeq[String]] = getFilePath(key).map { rel => + sourceCache.getOrElseUpdate(rel, os.read.lines(root / rel)) + } + + /** returns None if the key is not unique */ + private def getFilePath(key: String): Option[os.RelPath] = { + val path = os.RelPath(key) + if (os.exists(root / path)) { + Some(path) + } else { + index.get(key) match { + case Some(List(one)) => Some(one) + case _ => None + } + } + } + +} + +object CodeBase { + + /** Implements the algorithm from Chisel that determines the root for generating source info annotations. + * https://github.com/chipsalliance/chisel/blob/a5e29163ce11641056af18656658144465b0dfcf/core/src/main/scala/chisel3/internal/SourceInfo.scala#L57 + */ + private def chiselRootGuess: os.Path = { + val userDir = sys.props.get("user.dir") // Figure out what to do if not provided + val projectRoot = sys.props.get("chisel.project.root") + val root = projectRoot.orElse(userDir) + os.Path(root.get) + } + + /** finds all source files in the path and maps them by their filename */ + private def index(root: os.Path, exts: Set[String] = Set("scala")): Map[String, List[os.RelPath]] = { + val i = mutable.HashMap[String, List[os.RelPath]]() + index(root, root, exts, i) + i.toMap + } + + private def index(root: os.Path, dir: os.Path, exts: Set[String], i: mutable.HashMap[String, List[os.RelPath]]) + : Unit = { + val stream = os.walk.stream(dir) + stream.foreach { f: os.Path => + if (exts.contains(f.ext)) { + val key = f.last + val old = i.getOrElse(key, List()) + val relative = f.relativeTo(root) + i(key) = relative +: old + } + } + } +} diff --git a/src/main/scala/chiseltest/coverage/Coverage.scala b/src/main/scala/chiseltest/coverage/Coverage.scala index b82cb4350..3900a08fe 100644 --- a/src/main/scala/chiseltest/coverage/Coverage.scala +++ b/src/main/scala/chiseltest/coverage/Coverage.scala @@ -1,7 +1,22 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + package chiseltest.coverage import firrtl2._ -import firrtl2.annotations.{Annotation, NoTargetAnnotation} +import firrtl2.annotations._ +import firrtl2.options.Dependency +import firrtl2.stage.TransformManager.TransformDependency + +import scala.util.matching.Regex + +/** Tags a module that should not have any coverage added. This annotation should be respected by all automated coverage + * passes. + */ +case class DoNotCoverAnnotation(target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] { + override def duplicate(n: ModuleTarget) = copy(target = n) +} /** Coverage counts returned from the simulator interface. Each instance of a cover statement in the circuit is * represented by its hierarchical path (relative to the main module) and the number of times the cover predicate and @@ -27,6 +42,19 @@ case class TestCoverage(counts: List[(String, Long)]) extends NoTargetAnnotation trait CoverageInfo extends Annotation object Coverage { + val AllPasses: Seq[TransformDependency] = Seq( + Dependency(LineCoveragePass), + Dependency(ToggleCoveragePass), + Dependency(FsmCoveragePass) + ) + + def collectTestCoverage(annos: AnnotationSeq): List[(String, Long)] = { + annos.collect { case TestCoverage(e) => e } match { + case Seq(one) => one + case other => throw new RuntimeException(s"Expected exactly one TestCoverage annotation, not: $other") + } + } + def collectCoverageAnnotations(annos: AnnotationSeq): AnnotationSeq = { annos.collect { case a: CoverageInfo => a @@ -34,4 +62,50 @@ object Coverage { case a: ModuleInstancesAnnotation => a } } + + def collectModuleInstances(annos: AnnotationSeq): List[(String, String)] = { + annos.collect { case ModuleInstancesAnnotation(e) => e } match { + case Seq(one) => one + case other => throw new RuntimeException(s"Expected exactly one ModuleInstances annotation, not: $other") + } + } + + def moduleToInstances(annos: AnnotationSeq): Map[String, List[String]] = { + collectModuleInstances(annos).groupBy(_._2).map { case (k, v) => k -> v.map(_._1) } + } + + def collectModulesToIgnore(state: CircuitState): Set[String] = { + val main = state.circuit.main + state.annotations.collect { case DoNotCoverAnnotation(target) if target.circuit == main => target.module }.toSet + } + + def path(prefix: String, suffix: String): String = { + if (prefix.isEmpty) suffix else prefix + "." + suffix + } + + type Lines = List[(String, List[Int])] + private val chiselFileInfo: Regex = raw"\s*([^\.]+\.\w+) (\d+):(\d+)".r + + def parseFileInfo(i: ir.FileInfo): Seq[(String, Int)] = { + chiselFileInfo + .findAllIn(i.unescaped) + .map { case chiselFileInfo(filename, line, col) => + (filename, line.toInt) + } + .toSeq + } + + def infosToLines(infos: Seq[ir.Info]): Lines = { + val parsed = findFileInfos(infos).flatMap(parseFileInfo) + val byFile = parsed.groupBy(_._1).toList.sortBy(_._1) + byFile.map { case (filename, e) => filename -> e.map(_._2).toSet.toList.sorted } + } + + def findFileInfos(infos: Seq[ir.Info]): Seq[ir.FileInfo] = infos.flatMap(findFileInfos) + + def findFileInfos(info: ir.Info): Seq[ir.FileInfo] = info match { + case ir.MultiInfo(infos) => findFileInfos(infos) + case f: ir.FileInfo => List(f) + case _ => List() + } } diff --git a/src/main/scala/chiseltest/coverage/CoverageStatisticsPass.scala b/src/main/scala/chiseltest/coverage/CoverageStatisticsPass.scala new file mode 100644 index 000000000..43334c1d6 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/CoverageStatisticsPass.scala @@ -0,0 +1,79 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ + +/** Display information about all coverage instrumentation. This pass does not modify the circuit itself, it only prints + * out some information. Make sure to set the log level at least to "info" to see the output. + */ +object CoverageStatisticsPass extends Transform { + override def prerequisites = Seq() + override def optionalPrerequisites = Coverage.AllPasses + override def optionalPrerequisiteOf = AllEmitters() + override def invalidates(a: Transform) = false + + override def execute(state: CircuitState): CircuitState = { + analysis.foreach(a => a(state)) + state + } + + private val analysis = Seq( + generalAnalysis(_), + analyzeLineCoverage(_), + analyzeToggleCoverage(_), + analyzeFsmCoverage(_) + ) + + private def generalAnalysis(state: CircuitState): Unit = { + val coverPoints = state.annotations.collect { case a: CoverageInfo => a }.size + logger.info("Coverage Statistics:") + logger.info(s"- Total automatic cover points: $coverPoints") + val ignored = Coverage.collectModulesToIgnore(state) + if (ignored.nonEmpty) { + logger.info(s"- Ignored modules: " + ignored.toSeq.sorted.mkString(", ")) + } + } + + private def analyzeLineCoverage(state: CircuitState): Unit = { + val line = state.annotations.collect { case a: LineCoverageAnnotation => a } + if (line.nonEmpty) { + logger.info("Line Coverage:") + logger.info(s"- Line cover points: ${line.size}") + } + } + + private def analyzeToggleCoverage(state: CircuitState): Unit = { + val annos = state.annotations + val toggle = annos.collect { case a: ToggleCoverageAnnotation => a } + if (toggle.nonEmpty) { + logger.info("Toggle Coverage:") + logger.info(s"- Toggle cover points: ${toggle.size}") + val allBits = toggle.flatMap(a => a.signals.map(_.toString() + "[" + a.bit + "]")) + val allSignals = toggle.flatMap(_.signals.map(_.toString())).distinct + logger.info(s"- Signals covered: ${allSignals.size}") + logger.info(s"- Signal Bits covered: ${allBits.size}") + val opts = Seq( + PortToggleCoverage -> "ports", + RegisterToggleCoverage -> "regs", + MemoryToggleCoverage -> "mems", + WireToggleCoverage -> "wires" + ) + val on = opts.map { case (a, s) => if (annos.contains(a)) s + " ✅" else s + " ❌" }.mkString(" ") + logger.info("- " + on) + } + } + + private def analyzeFsmCoverage(state: CircuitState): Unit = { + val annos = state.annotations + val fsms = annos.collect { case a: FsmCoverageAnnotation => a } + if (fsms.nonEmpty) { + logger.info("FSM Coverage:") + fsms.foreach { case FsmCoverageAnnotation(stateReg, states, transitions) => + logger.info(s"- ${stateReg}: ${states.length} states, ${transitions.length} transitions") + } + } + } +} diff --git a/src/main/scala/chiseltest/coverage/FsmCoverage.scala b/src/main/scala/chiseltest/coverage/FsmCoverage.scala new file mode 100644 index 000000000..7d80257e6 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/FsmCoverage.scala @@ -0,0 +1,44 @@ +// Copyright 2021 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.options.Dependency +import firrtl2.stage.RunFirrtlTransformAnnotation + +object FsmCoverage { + def annotations: AnnotationSeq = Seq( + RunFirrtlTransformAnnotation(Dependency(FsmCoveragePass)), + RunFirrtlTransformAnnotation(Dependency(ModuleInstancesPass)) + ) + + def processCoverage(annos: AnnotationSeq): Seq[FsmCoverageData] = { + val fsms = annos.collect { case a: FsmCoverageAnnotation => a } + val cov = Coverage.collectTestCoverage(annos).toMap + val moduleToInst = Coverage.moduleToInstances(annos) + + fsms.flatMap { fsm => + val top = fsm.stateReg.circuit + "." + moduleToInst(fsm.stateReg.module).map { inst => + val states = fsm.states + .map(s => s._1 -> cov(Coverage.path(inst, s._2.ref))) + .toList + .sortBy(_._1) + val transitions = fsm.transitions + .map(t => t._1 -> cov(Coverage.path(inst, t._2.ref))) + .toList + .sortBy(_._1) + FsmCoverageData(top + Coverage.path(inst, fsm.stateReg.ref), states, transitions) + } + } + } + + def textReport(data: Seq[FsmCoverageData]): Iterable[String] = data.flatMap { fsm => + Seq(fsm.name, fsm.states.map { case (name, count) => s"$name ($count)" }.mkString(", ")) ++ + fsm.transitions.map { case ((from, to), count) => s"$from -> $to: $count" } + } +} + +case class FsmCoverageData(name: String, states: List[(String, Long)], transitions: List[((String, String), Long)]) diff --git a/src/main/scala/chiseltest/coverage/FsmCoveragePass.scala b/src/main/scala/chiseltest/coverage/FsmCoveragePass.scala new file mode 100644 index 000000000..8a1a2988e --- /dev/null +++ b/src/main/scala/chiseltest/coverage/FsmCoveragePass.scala @@ -0,0 +1,166 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.annotations._ +import firrtl2.options.Dependency +import firrtl2.stage.Forms +import firrtl2.stage.TransformManager.TransformDependency + +import scala.collection.mutable + +case class FsmCoverageAnnotation( + stateReg: ReferenceTarget, + states: Seq[(String, ReferenceTarget)], + transitions: Seq[((String, String), ReferenceTarget)]) + extends MultiTargetAnnotation + with CoverageInfo { + override def targets = Seq(Seq(stateReg)) ++ states.map(s => Seq(s._2)) ++ transitions.map(t => Seq(t._2)) + + override def duplicate(n: Seq[Seq[Target]]) = { + assert(n.length == 1 + states.length + transitions.length) + n.foreach(e => assert(e.length == 1, "Cover points and state registers should not be split up!")) + val targets = n.map(_.head.asInstanceOf[ReferenceTarget]) + val r = copy( + stateReg = targets.head, + states = states.map(_._1).zip(targets.slice(1, states.length + 1)), + transitions = transitions.map(_._1).zip(targets.drop(1 + states.length)) + ) + r + } +} + +case object SkipFsmCoverageAnnotation extends NoTargetAnnotation + +object FsmCoveragePass extends Transform { + val Prefix = "f" + + override def prerequisites: Seq[TransformDependency] = + Forms.LowForm ++ Seq(Dependency(FsmInfoPass), Dependency(RegisterResetAnnotationPass)) + override def invalidates(a: Transform): Boolean = false + + override def execute(state: CircuitState): CircuitState = { + if (state.annotations.contains(SkipFsmCoverageAnnotation)) { + logger.info("[FsmCoverage] skipping due to SkipFsmCoverage annotation") + return state + } + + // collect FSMs in modules that are not ignored + val ignoreMods = Coverage.collectModulesToIgnore(state) + val infos = state.annotations.collect { case a: FsmInfoAnnotation if !ignoreMods(a.target.module) => a } + + // if there are no FSMs there is nothing to do + if (infos.isEmpty) return state + + // instrument FSMs + val registerResets = state.annotations.collect { case a: RegisterResetAnnotation => a } + val newAnnos = mutable.ListBuffer[Annotation]() + val c = CircuitTarget(state.circuit.main) + val circuit = state.circuit.mapModule(onModule(_, c, newAnnos, infos, registerResets)) + state.copy(circuit = circuit, annotations = newAnnos.toList ++ state.annotations) + } + + private def onModule( + m: ir.DefModule, + c: CircuitTarget, + annos: mutable.ListBuffer[Annotation], + infos: Seq[FsmInfoAnnotation], + resets: Seq[RegisterResetAnnotation] + ): ir.DefModule = m match { + case mod: ir.Module => + val fsms = infos.filter(_.target.module == mod.name) + if (fsms.isEmpty) { mod } + else { + val isFsm = fsms.map(_.target.ref).toSet + val fsmRegs = findFsmRegs(mod.body, isFsm) + val stmts = new mutable.ListBuffer[ir.Statement]() + val ctx = ModuleCtx(c.module(mod.name), stmts, Namespace(mod)) + val toReset = RegisterResetAnnotationPass.findResetsInModule(ctx.m, resets) + val fsmAnnos = fsms.map { f => onFsm(f, fsmRegs.find(_.name == f.target.ref).get, ctx, toReset.get) } + annos ++= fsmAnnos + val newBody = ir.Block(mod.body +: stmts.toList) + + mod.copy(body = newBody) + } + case other => other + } + + private case class ModuleCtx(m: ModuleTarget, stmts: mutable.ListBuffer[ir.Statement], namespace: Namespace) + + private def onFsm(fsm: FsmInfoAnnotation, reg: ir.DefRegister, ctx: ModuleCtx, toReset: String => Option[String]) + : Annotation = { + val info = reg.info + val clock = reg.clock + val reset = toReset(reg.name).map(ir.Reference(_, Utils.BoolType, NodeKind, SourceFlow)).getOrElse(Utils.False()) + val notReset = Utils.not(reset) + val regRef = ir.Reference(reg) + val regWidth = firrtl2.bitWidth(reg.tpe) + def inState(s: BigInt): ir.Expression = Utils.eq(regRef, ir.UIntLiteral(s, ir.IntWidth(regWidth))) + + // cover state when FSM is _not_ in reset + val states = fsm.states.map { case (id, stateName) => + val name = ctx.namespace.newName(reg.name + "_" + stateName) + ctx.stmts.append(ir.Verification(ir.Formal.Cover, info, clock, inState(id), notReset, ir.StringLit(""), name)) + stateName -> ctx.m.ref(name) + } + + // create a register to hold the previous state + val prevState = + Builder.makeRegister(ctx.stmts, info, ctx.namespace.newName(reg.name + "_prev"), reg.tpe, clock, regRef) + def inPrevState(s: BigInt): ir.Expression = Utils.eq(prevState, ir.UIntLiteral(s, ir.IntWidth(regWidth))) + + // create a register to track if the previous state is valid + val prevValid = Builder.makeRegister( + ctx.stmts, + info, + ctx.namespace.newName(reg.name + "_prev_valid"), + Utils.BoolType, + clock, + notReset + ) + + // create a transition valid signal + val transitionValid = ir.Reference(ctx.namespace.newName(reg.name + "_t_valid"), Utils.BoolType, NodeKind) + ctx.stmts.append(ir.DefNode(info, transitionValid.name, Utils.and(notReset, prevValid))) + + val idToName = fsm.states.toMap + val transitions = fsm.transitions.map { case (from, to) => + val (fromName, toName) = (idToName(from), idToName(to)) + val name = ctx.namespace.newName(reg.name + "_" + fromName + "_to_" + toName) + ctx.stmts.append( + ir.Verification( + ir.Formal.Cover, + info, + clock, + Utils.and(inPrevState(from), inState(to)), + transitionValid, + ir.StringLit(""), + name + ) + ) + (fromName, toName) -> ctx.m.ref(name) + } + + FsmCoverageAnnotation(ctx.m.ref(reg.name), states, transitions) + } + + private def printFsmInfo(fsm: FsmInfoAnnotation): Unit = { + val toName = fsm.states.toMap + println(s"[${fsm.target.module}.${fsm.target.name}] Found FSM") + if (fsm.start.nonEmpty) { + println(s"Start: ${toName(fsm.start.get)}") + } + println("Transitions:") + fsm.transitions.foreach(t => println(s"${toName(t._1)} -> ${toName(t._2)}")) + } + + private def findFsmRegs(s: ir.Statement, isFsm: String => Boolean): Seq[ir.DefRegister] = s match { + case r: ir.DefRegister if isFsm(r.name) => List(r) + case ir.Block(stmts) => stmts.flatMap(findFsmRegs(_, isFsm)) + case _: ir.Conditionally => throw new RuntimeException("Unexpected when statement! Expected LoFirrtl.") + case _ => List() + } +} diff --git a/src/main/scala/chiseltest/coverage/FsmInfoPass.scala b/src/main/scala/chiseltest/coverage/FsmInfoPass.scala new file mode 100644 index 000000000..a80f265d3 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/FsmInfoPass.scala @@ -0,0 +1,224 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.annotations._ +import firrtl2.stage.Forms +import firrtl2.stage.TransformManager.TransformDependency + +import scala.collection.mutable + +case class FsmInfoAnnotation( + target: ReferenceTarget, + states: Seq[(BigInt, String)], + transitions: Seq[(BigInt, BigInt)], + start: Option[BigInt]) + extends SingleTargetAnnotation[ReferenceTarget] { + override def duplicate(n: ReferenceTarget) = copy(target = n) +} + +/** Annotates FSMs in the design with information about all available states and transitions. */ +object FsmInfoPass extends Transform { + val Prefix = "f" + + override def prerequisites: Seq[TransformDependency] = Forms.LowForm + override def invalidates(a: Transform): Boolean = false + + override protected def execute(state: CircuitState): CircuitState = { + val enums = state.annotations.collect { case a: EnumDefAnnotation => a.typeName -> a }.toMap + val components = state.annotations.collect { case a: EnumComponentAnnotation => a } + + // if there are no enums, we won't be able to find any FSMs + if (enums.isEmpty) return state + + val c = CircuitTarget(state.circuit.main) + val infos = state.circuit.modules.flatMap(onModule(_, c, enums, components)) + + state.copy(annotations = infos ++: state.annotations) + } + + private def onModule( + m: ir.DefModule, + c: CircuitTarget, + enums: Map[String, EnumDefAnnotation], + components: Seq[EnumComponentAnnotation] + ): List[Annotation] = m match { + case mod: ir.Module => + val localComponents = components + .filter(c => toReferenceTarget(c.target).module == mod.name) + .map(c => toReferenceTarget(c.target).ref -> c) + .toMap + if (localComponents.isEmpty) { + List() + } else { + // sometime wires/nodes get annotated instead of registers, we want to filter those out + val isReg = findRegNames(mod.body) + val realStateRegs = localComponents.filter(c => isReg(c._1)) + // extract net info from module + val regNames = realStateRegs.keySet + val netData = new ModuleNetAnalyzer(regNames).run(mod) + // sometimes wires/nodes instead of registers + realStateRegs.map { case (name, anno) => + analyzeFSM(c.module(mod.name), name, netData, enums(anno.enumTypeName).definition) + }.toList + } + case other => List() + } + + private def analyzeFSM(module: ModuleTarget, regName: String, netData: ModuleNetData, states: Map[String, BigInt]) + : FsmInfoAnnotation = { + val nextExpr = netData.next(regName) + val (resetState, next) = destructReset(nextExpr) + + // analyze next state expression for each start state + val allStates = states.values.toSeq + val transitions = states.toSeq.sortBy(_._2).flatMap { case (name, from) => + val res = new FsmAnalyzer(netData.con, regName, from, allStates).analyzeNext(next) + res.map(from -> _) + } + + FsmInfoAnnotation( + module.ref(regName), + states = states.toSeq.sorted.map { case (n, i) => i -> n }, + transitions = transitions, + start = resetState + ) + } + + // tries to extract the reset value, this assumes synchronous resets! + private def destructReset(e: ir.Expression): (Option[BigInt], ir.Expression) = e match { + case ir.Mux(ir.Reference("reset", _, _, _), rval: ir.UIntLiteral, oval, _) => (Some(rval.value), oval) + case ir.Mux(ir.DoPrim(PrimOps.Not, Seq(ir.Reference("reset", _, _, _)), _, _), oval, rval: ir.UIntLiteral, _) => + (Some(rval.value), oval) + case _ => (None, e) + } + + private def toReferenceTarget(n: Named): ReferenceTarget = n match { + case ComponentName(name, module) => module.toTarget.ref(name) + case other => throw new NotImplementedError(s"Unexpected $other") + } +} + +private class FsmAnalyzer( + con: Map[String, ConnectionInfo], + stateRegName: String, + stateValue: BigInt, + allStates: Seq[BigInt]) { + def analyzeNext(e: ir.Expression): Seq[BigInt] = { + val simplified = simplify(followAll = true)(e) + simplified match { + case ir.UIntLiteral(value, _) => Seq(value) // the state will be `value` without any condition + case ir.Mux(condExpr, tvalExpr, fvalExpr, _) => + // try to simplify the predicate (but only if it references the state register!) + val simplePred = simplify(followAll = false)(condExpr) + + // implement branch + simplePred match { + case ir.UIntLiteral(value, _) if value == 1 => analyzeNext(tvalExpr) + case ir.UIntLiteral(value, _) if value == 0 => analyzeNext(fvalExpr) + case _ => // both branches are feasible + analyzeNext(tvalExpr) ++ analyzeNext(fvalExpr) + } + case other => + // over approximate + allStates + } + } + def simplify(followAll: Boolean)(e: ir.Expression): ir.Expression = { + // we simplify bottom up! + e.mapExpr(simplify(followAll)) match { + // replace references to the state register with the state value + case ir.Reference(name, ir.UIntType(width), _, _) if name == stateRegName => + ir.UIntLiteral(stateValue, width) + // follow (i.e., inline) some references + case r @ ir.Reference(name, _, _, _) => + con.get(name) match { + case None => r // nothing to do, cannot follow + case Some(info) => + val dependsOnStateValue = info.registerDependencies.contains(stateRegName) + if (dependsOnStateValue || followAll) { + simplify(followAll)(info.expr) + } else { + r + } + } + case other => + // try to propagate any constants + val constPropped = propConst(other) + constPropped + } + } +} + +private object findRegNames { + def apply(s: ir.Statement): Set[String] = s match { + case ir.DefRegister(_, name, _, _, _, _) => Set(name) + case ir.Block(stmts) => stmts.map(apply).reduce(_ | _) + case ir.Conditionally(_, _, conseq, alt) => Seq(conseq, alt).map(apply).reduce(_ | _) + case _ => Set() + } +} + +private object propConst { + private def toUInt(cond: Boolean): ir.Expression = if (cond) { Utils.True() } + else { Utils.False() } + // performs a single level of constant propagation (does not recurse into expression!) + def apply(e: ir.Expression): ir.Expression = e match { + case ir.Mux(ir.UIntLiteral(value, _), tval, fval, _) => + if (value == 1) { tval } + else { fval } + case ir.DoPrim(PrimOps.Eq, Seq(ir.UIntLiteral(a, _), ir.UIntLiteral(b, _)), _, _) => toUInt(a == b) + case ir.DoPrim(PrimOps.AsUInt, Seq(lit: ir.UIntLiteral), _, _) => lit + case other => other + } +} + +/** Contains the right-hand-side expression and transitive register dependency for a single node or register next + * expression. + */ +private case class ConnectionInfo(expr: ir.Expression, registerDependencies: Set[String]) + +/** Contains information about all nodes and register next connections in the circuit */ +private case class ModuleNetData(con: Map[String, ConnectionInfo], next: Map[String, ir.Expression]) +private class ModuleNetAnalyzer(registers: Set[String]) { + private val con = mutable.HashMap[String, ConnectionInfo]() + private val next = mutable.HashMap[String, ir.Expression]() + def run(mod: ir.Module): ModuleNetData = { + mod.foreachStmt(onStmt) + ModuleNetData(con.toMap, next.toMap) + } + def onStmt(s: ir.Statement): Unit = s match { + case ir.Connect(_, ir.Reference(name, _, kind, _), expr) if kind == RegKind => + next(name) = expr + case ir.Connect(_, loc, expr) => + con(loc.serialize) = ConnectionInfo(expr, findDeps(expr)) + case ir.DefNode(_, name, expr) => + con(name) = ConnectionInfo(expr, findDeps(expr)) + case other => other.foreachStmt(onStmt) + } + def findDeps(e: ir.Expression): Set[String] = e match { + case ir.Reference(name, _, _, _) => + if (registers.contains(name)) { Set(name) } + else { + con.get(name).map(_.registerDependencies).getOrElse(Set()) + } + case other => + getChildren(other).map(findDeps) match { + case Seq() => Set() + case children => children.reduce(_ | _) + } + } +} + +private object getChildren { + def apply(e: ir.Expression): Seq[ir.Expression] = e match { + case _: ir.UIntLiteral | _: ir.SIntLiteral | _: ir.Reference => Seq() + case prim: ir.DoPrim => prim.args + case ir.Mux(cond, tval, fval, _) => Seq(cond, tval, fval) + case ir.ValidIf(cond, value, _) => Seq(cond, value) + case ir.SubField(expr, _, _, _) => Seq(expr) + } +} diff --git a/src/main/scala/chiseltest/coverage/KeepClockAndResetPass.scala b/src/main/scala/chiseltest/coverage/KeepClockAndResetPass.scala new file mode 100644 index 000000000..9640acc9b --- /dev/null +++ b/src/main/scala/chiseltest/coverage/KeepClockAndResetPass.scala @@ -0,0 +1,53 @@ +// Copyright 2021 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.annotations._ +import firrtl2.options.Dependency +import firrtl2.stage.Forms +import firrtl2.transforms._ + +case class KeepClockAndResetAnnotation(target: ReferenceTarget) + extends SingleTargetAnnotation[ReferenceTarget] + with HasDontTouches { + override def duplicate(n: ReferenceTarget) = copy(target = n) + override def dontTouches = List(target) +} + +/** Marks all `clock` and `reset` signals as DontTouch so that they are not removed by Dead Code Elimination. This makes + * adding coverage that relies on those pins being available easier. + */ +object KeepClockAndResetPass extends Transform { + // try to run early + override def prerequisites = Forms.Checks + override def invalidates(a: Transform) = false + // need to run before DCE + override def optionalPrerequisiteOf = Seq(Dependency[DeadCodeElimination]) + + override def execute(state: CircuitState): CircuitState = { + val c = CircuitTarget(state.circuit.main) + val annos = state.circuit.modules.flatMap(onModule(_, c)) + state.copy(annotations = annos ++ state.annotations) + } + + private def onModule(m: ir.DefModule, c: CircuitTarget): List[KeepClockAndResetAnnotation] = m match { + case mod: ir.Module => + val clock = Builder.findClocks(mod) + val reset = Builder.findResets(mod) + val mRef = c.module(mod.name) + (clock).map(e => KeepClockAndResetAnnotation(Builder.refToTarget(mRef, e))).toList + case _ => List() + } +} + +object RemoveKeepClockAndResetAnnotations extends Transform { + override def prerequisites = Seq(Dependency(KeepClockAndResetPass)) + override def invalidates(a: Transform) = a == KeepClockAndResetPass + override def execute(state: CircuitState): CircuitState = { + val filtered = state.annotations.filterNot(_.isInstanceOf[KeepClockAndResetAnnotation]) + state.copy(annotations = filtered) + } +} diff --git a/src/main/scala/chiseltest/coverage/LineCoverage.scala b/src/main/scala/chiseltest/coverage/LineCoverage.scala new file mode 100644 index 000000000..5cf8a0c5c --- /dev/null +++ b/src/main/scala/chiseltest/coverage/LineCoverage.scala @@ -0,0 +1,82 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.options.Dependency +import firrtl2.stage.RunFirrtlTransformAnnotation + +object LineCoverage { + def annotations: AnnotationSeq = Seq( + RunFirrtlTransformAnnotation(Dependency(LineCoveragePass)), + RunFirrtlTransformAnnotation(Dependency(ModuleInstancesPass)) + ) + + def processCoverage(annos: AnnotationSeq): LineCoverageData = { + val cov = Coverage.collectTestCoverage(annos).toMap + val moduleToInst = Coverage.moduleToInstances(annos) + val infos = annos.collect { case a: LineCoverageAnnotation => a } + + val counts = infos.flatMap { case LineCoverageAnnotation(target, lines) => + val insts = moduleToInst(target.module) + val counts = insts.map { i => + val path = Coverage.path(i, target.ref) + cov(path) + } + val total = counts.sum + + lines.flatMap { case (filename, ll) => + ll.map { line => + (filename, line) -> total + } + } + } + + val files = counts + .groupBy(_._1._1) + .map { case (filename, entries) => + val lines = entries.map(e => (e._1._2, e._2)).sortBy(_._1).toList + LineCoverageInFile(filename, lines) + } + .toList + .sortBy(_.name) + + LineCoverageData(files) + } + + private val Count = "Cnt" + private val LineNr = "Line" + def textReport(code: CodeBase, file: LineCoverageInFile): Iterable[String] = { + val sourceLines = code.getSource(file.name).getOrElse { + throw new RuntimeException(s"Unable to find file ${file.name} in ${code}") + } + val counts: Map[Int, Long] = file.lines.toMap + + // we output a table with Line, Exec, Source + val lineNrWidth = (file.lines.map(_._1.toString.length) :+ LineNr.length).max + val countWidth = (file.lines.map(_._2.toString.length) :+ Count.length).max + val countBlank = " " * countWidth + val srcWidth = sourceLines.map(_.length).max + + val header = pad(LineNr, lineNrWidth) + " | " + pad(Count, countWidth) + " | " + "Source" + val headerLine = "-" * (lineNrWidth + 3 + countWidth + 3 + srcWidth) + + val body = sourceLines.zipWithIndex.map { case (line, ii) => + val lineNo = ii + 1 // lines are 1-indexed + val lineNoStr = pad(lineNo.toString, lineNrWidth) + val countStr = counts.get(lineNo).map(c => pad(c.toString, countWidth)).getOrElse(countBlank) + lineNoStr + " | " + countStr + " | " + line + } + Seq(header, headerLine) ++ body + } + + private def pad(str: String, to: Int): String = { + assert(str.length <= to) + str.reverse.padTo(to, ' ').reverse + } +} + +case class LineCoverageData(files: List[LineCoverageInFile]) +case class LineCoverageInFile(name: String, lines: List[(Int, Long)]) diff --git a/src/main/scala/chiseltest/coverage/LineCoveragePass.scala b/src/main/scala/chiseltest/coverage/LineCoveragePass.scala new file mode 100644 index 000000000..010062099 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/LineCoveragePass.scala @@ -0,0 +1,108 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.annotations._ +import firrtl2.options.Dependency +import firrtl2.passes.{ExpandWhens, ExpandWhensAndCheck} +import firrtl2.stage.Forms +import firrtl2.stage.TransformManager.TransformDependency +import firrtl2.transforms.DedupModules + +import scala.collection.mutable + +case class LineCoverageAnnotation(target: ReferenceTarget, lines: Coverage.Lines) + extends SingleTargetAnnotation[ReferenceTarget] + with CoverageInfo { + override def duplicate(n: ReferenceTarget) = copy(target = n) +} + +case object SkipLineCoverageAnnotation extends NoTargetAnnotation + +object LineCoveragePass extends Transform { + val Prefix = "l" + + override def prerequisites: Seq[TransformDependency] = Forms.Checks + // we can run after deduplication which should make things faster + override def optionalPrerequisites: Seq[TransformDependency] = Seq(Dependency[DedupModules]) + // line coverage does not work anymore after whens have been expanded + override def optionalPrerequisiteOf: Seq[TransformDependency] = + Seq(Dependency[ExpandWhensAndCheck], Dependency(ExpandWhens)) + override def invalidates(a: Transform): Boolean = false + + override protected def execute(state: CircuitState): CircuitState = { + if (state.annotations.contains(SkipLineCoverageAnnotation)) { + logger.info("[LineCoverage] skipping due to SkipLineCoverage annotation") + return state + } + val newAnnos = mutable.ListBuffer[Annotation]() + val c = CircuitTarget(state.circuit.main) + val ignoreMods = Coverage.collectModulesToIgnore(state) + val circuit = state.circuit.mapModule(onModule(_, c, newAnnos, ignoreMods)) + val annos = newAnnos.toList ++ state.annotations + CircuitState(circuit, annos) + } + + private case class ModuleCtx( + annos: mutable.ListBuffer[Annotation], + namespace: Namespace, + m: ModuleTarget, + clk: ir.Expression) + + private def onModule(m: ir.DefModule, c: CircuitTarget, annos: mutable.ListBuffer[Annotation], ignore: Set[String]) + : ir.DefModule = + m match { + case mod: ir.Module if !ignore(mod.name) => + Builder.findClock(mod, logger) match { + case Some(clock) => + val namespace = Namespace(mod) + namespace.newName(Prefix) + val ctx = ModuleCtx(annos, namespace, c.module(mod.name), clock) + // we always cover the body, even if the module only contains nodes and cover statements + val bodyInfo = onStmt(mod.body, ctx).copy(_2 = true) + val body = addCover(bodyInfo, ctx) + mod.copy(body = body) + case None => + mod + } + case other => other + } + + private def onStmt(s: ir.Statement, ctx: ModuleCtx): (ir.Statement, Boolean, Seq[ir.Info]) = s match { + case c @ ir.Conditionally(_, _, conseq, alt) => + val truInfo = onStmt(conseq, ctx) + val falsInfo = onStmt(alt, ctx) + val doCover = truInfo._2 || falsInfo._2 + val stmt = c.copy(conseq = addCover(truInfo, ctx), alt = addCover(falsInfo, ctx)) + (stmt, doCover, List(c.info)) + case ir.Block(stmts) => + val s = stmts.map(onStmt(_, ctx)) + val block = ir.Block(s.map(_._1)) + val doCover = s.map(_._2).foldLeft(false)(_ || _) + val infos = s.flatMap(_._3) + (block, doCover, infos) + case ir.EmptyStmt => (ir.EmptyStmt, false, List()) + // if there is only a cover statement, we do not explicitly try to cover that line + case v: ir.Verification if v.op == ir.Formal.Cover => (v, false, List(v.info)) + // nodes are always side-effect free, so they should not be covered unless there is another operation in the block + case n: ir.DefNode => (n, false, List(n.info)) + case other: ir.HasInfo => (other, true, List(other.info)) + case other => (other, false, List()) + } + + private def addCover(info: (ir.Statement, Boolean, Seq[ir.Info]), ctx: ModuleCtx): ir.Statement = { + val (stmt, doCover, infos) = info + if (!doCover) { stmt } + else { + val name = ctx.namespace.newName(Prefix) + val lines = Coverage.infosToLines(infos) + ctx.annos.prepend(LineCoverageAnnotation(ctx.m.ref(name), lines)) + val cover = + ir.Verification(ir.Formal.Cover, ir.NoInfo, ctx.clk, Utils.True(), Utils.True(), ir.StringLit(""), name) + ir.Block(cover, stmt) + } + } +} diff --git a/src/main/scala/chiseltest/coverage/ModuleInstancesPass.scala b/src/main/scala/chiseltest/coverage/ModuleInstancesPass.scala index 0c1c87199..da9afc849 100644 --- a/src/main/scala/chiseltest/coverage/ModuleInstancesPass.scala +++ b/src/main/scala/chiseltest/coverage/ModuleInstancesPass.scala @@ -1,11 +1,13 @@ -// SPDX-License-Identifier: Apache-2.0 +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer package chiseltest.coverage +import firrtl2._ import firrtl2.analyses.InstanceKeyGraph import firrtl2.analyses.InstanceKeyGraph.InstanceKey import firrtl2.annotations.NoTargetAnnotation -import firrtl2._ import firrtl2.options.Dependency import firrtl2.passes.InlineInstances import firrtl2.stage.Forms diff --git a/src/main/scala/chiseltest/coverage/RegisterResetAnnotationPass.scala b/src/main/scala/chiseltest/coverage/RegisterResetAnnotationPass.scala new file mode 100644 index 000000000..5add077a0 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/RegisterResetAnnotationPass.scala @@ -0,0 +1,92 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.annotations._ +import firrtl2.options.Dependency +import firrtl2.transforms.{HasDontTouches, RemoveReset} + +import scala.collection.mutable + +case class RegisterResetAnnotation(registers: Seq[ReferenceTarget], reset: ReferenceTarget) + extends MultiTargetAnnotation + with HasDontTouches { + override def targets = Seq(registers, Seq(reset)) + override def dontTouches = List(reset) + + override def duplicate(n: Seq[Seq[Target]]) = n match { + case Seq(t: Seq[_], Seq(r: ReferenceTarget)) => copy(registers = t.map(_.asInstanceOf[ReferenceTarget]), reset = r) + case other => throw new RuntimeException(s"Unexpected argument to duplicate: $other") + } +} + +/** Ensures that all register resets are named signals that will be annotated and not removed. */ +object RegisterResetAnnotationPass extends Transform { + // run on lowered firrtl + override def prerequisites = Seq(Dependency(passes.ExpandWhens), Dependency(passes.LowerTypes)) + override def invalidates(a: Transform) = false + // need to run before synchronous resets are removed + override def optionalPrerequisiteOf = Seq(Dependency(RemoveReset)) + + def findResetsInModule(m: ModuleTarget, annos: Seq[RegisterResetAnnotation]): Map[String, String] = { + annos + .filter(_.reset.module == m.module) + .flatMap { a => + a.registers.map(r => r.ref -> a.reset.ref) + } + .toMap + } + + override def execute(state: CircuitState): CircuitState = { + val newAnnos = mutable.ListBuffer[RegisterResetAnnotation]() + val c = CircuitTarget(state.circuit.main) + val circuit = state.circuit.mapModule(onModule(_, c, newAnnos)) + state.copy(circuit = circuit, annotations = newAnnos.toList ++ state.annotations) + } + + private def onModule(m: ir.DefModule, c: CircuitTarget, annos: mutable.ListBuffer[RegisterResetAnnotation]) + : ir.DefModule = m match { + case mod: ir.Module => + val resets = mutable.ListBuffer[(String, String)]() + val signalNames = mutable.HashMap[String, String]() + val namespace = Namespace(mod) + val newMod = mod.mapStmt(onStmt(_, resets, signalNames, namespace)) + + // create reset annotations + val m = c.module(mod.name) + annos ++= resets.groupBy(_._1).map { case (reset, regs) => + RegisterResetAnnotation(regs.toList.map(r => m.ref(r._2)), m.ref(reset)) + } + + newMod + case other => other + } + + private def onStmt( + s: ir.Statement, + resets: mutable.ListBuffer[(String, String)], + signalNames: mutable.HashMap[String, String], + namespace: Namespace + ): ir.Statement = s match { + case reg: ir.DefRegister => + reg.reset match { + case r: ir.Reference => + resets.append(r.name -> reg.name) + reg + case other => + signalNames.get(other.serialize) match { + case Some(name) => + resets.append(name -> reg.name) + reg.copy(reset = ir.Reference(name, Utils.BoolType, NodeKind, SourceFlow)) + case None => + val node = ir.DefNode(reg.info, namespace.newName("reset"), other) + resets.append(node.name -> reg.name) + ir.Block(node, reg.copy(reset = ir.Reference(node.name, Utils.BoolType, NodeKind, SourceFlow))) + } + } + case other => other.mapStmt(onStmt(_, resets, signalNames, namespace)) + } +} diff --git a/src/main/scala/chiseltest/coverage/ToggleCoverage.scala b/src/main/scala/chiseltest/coverage/ToggleCoverage.scala new file mode 100644 index 000000000..e5851e0b8 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/ToggleCoverage.scala @@ -0,0 +1,70 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.annotations.NoTargetAnnotation +import firrtl2.options.Dependency +import firrtl2.stage.RunFirrtlTransformAnnotation +import firrtl2.stage.TransformManager.TransformDependency + +object ToggleCoverage { + def passes: Seq[TransformDependency] = + Seq(Dependency(ToggleCoveragePass), Dependency(ModuleInstancesPass), Dependency(RemoveKeepClockAndResetAnnotations)) + // TODO: re-enable MemoryToggleCoverage (currently broken b/c we are not allowed to read input ports!) + def all: AnnotationSeq = Seq(PortToggleCoverage, RegisterToggleCoverage, WireToggleCoverage) ++ passAnnos + def ports: AnnotationSeq = Seq(PortToggleCoverage) ++ passAnnos + def registers: AnnotationSeq = Seq(RegisterToggleCoverage) ++ passAnnos + def memories: AnnotationSeq = Seq(MemoryToggleCoverage) ++ passAnnos + def wires: AnnotationSeq = Seq(WireToggleCoverage) ++ passAnnos + private def passAnnos = passes.map(p => RunFirrtlTransformAnnotation(p)) + + def processCoverage(annos: AnnotationSeq): ToggleCoverageData = { + val infos = annos.collect { case a: ToggleCoverageAnnotation => a } + if (infos.isEmpty) return ToggleCoverageData(List()) + val cov = Coverage.collectTestCoverage(annos).toMap + val moduleToInst = Coverage.moduleToInstances(annos) + + val counts = infos.flatMap { info => + moduleToInst(info.target.module).flatMap { inst => + val count = cov(Coverage.path(inst, info.target.ref)) + info.signals.map { signal => + val instance = signal.path.map(_._1.value).mkString(".") + val module = signal.leafModule + val ref = signal.ref + val r = ((instance, module), ref, (info.bit, count)) + println(signal) + println(r) + r + } + } + } + + val byModule = counts.groupBy(_._1).toSeq.sortBy(_._1) + val bySignal = byModule.map { case (k, vs) => + k -> vs.map { case (_, signal, count) => signal -> count } + .groupBy(_._1) + .toSeq + .sortBy(_._1) + .map { case (signal, counts) => signal -> counts.map(_._2) } + } + ToggleCoverageData(bySignal) + } +} + +// instance, module, signal, bit, count +case class ToggleCoverageData(inst: Seq[((String, String), Seq[(String, Seq[(Int, Long)])])]) + +/** enables coverage of all I/O ports in the design */ +case object PortToggleCoverage extends NoTargetAnnotation + +/** enables coverage of all register signals in the design */ +case object RegisterToggleCoverage extends NoTargetAnnotation + +/** enables coverage of all memory port signals in the design */ +case object MemoryToggleCoverage extends NoTargetAnnotation + +/** enables coverage of all wires in the design */ +case object WireToggleCoverage extends NoTargetAnnotation diff --git a/src/main/scala/chiseltest/coverage/ToggleCoveragePass.scala b/src/main/scala/chiseltest/coverage/ToggleCoveragePass.scala new file mode 100644 index 000000000..a8416b673 --- /dev/null +++ b/src/main/scala/chiseltest/coverage/ToggleCoveragePass.scala @@ -0,0 +1,373 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2._ +import firrtl2.analyses.InstanceKeyGraph +import firrtl2.annotations._ +import firrtl2.options.Dependency +import firrtl2.stage.TransformManager.TransformDependency +import firrtl2.transforms.PropagatePresetAnnotations + +import scala.collection.mutable + +object AllEmitters { + def apply(): Seq[TransformDependency] = Seq( + Dependency[LowFirrtlEmitter], + Dependency[VerilogEmitter], + Dependency[SystemVerilogEmitter], + Dependency[MinimumVerilogEmitter] + ) +} + +case object SkipToggleCoverageAnnotation extends NoTargetAnnotation + +case class ToggleCoverageAnnotation(target: ReferenceTarget, signals: List[ReferenceTarget], bit: Int) + extends SingleTargetAnnotation[ReferenceTarget] + with CoverageInfo { + override def duplicate(n: ReferenceTarget) = copy(target = n) +} + +object ToggleCoveragePass extends Transform { + val Prefix = "t" + + override def prerequisites: Seq[TransformDependency] = Seq( + // we want to run after optimization in order to minimize the number of signals that are left over to instrument + Dependency[firrtl2.transforms.ConstantPropagation], + Dependency(firrtl2.passes.CommonSubexpressionElimination), + Dependency[firrtl2.transforms.DeadCodeElimination], + Dependency(KeepClockAndResetPass) + ) + override def optionalPrerequisites = Seq( + // we add our own registers with presets + Dependency[PropagatePresetAnnotations], + // this is to work around a bug where the WiringTransform gets scheduled too late + Dependency[firrtl2.passes.wiring.WiringTransform] + ) + // we want to run before the actual Verilog is emitted + override def optionalPrerequisiteOf = AllEmitters() + override def invalidates(a: Transform): Boolean = false + + private case class Options( + instrumentPorts: Boolean = false, + instrumentRegisters: Boolean = false, + instrumentMemories: Boolean = false, + instrumentWires: Boolean = false, + maxWidth: Int = 200, + resetAware: Boolean = false // reset awareness ensures that toggles during reset are ignored + ) { + def noCoverage: Boolean = !instrumentPorts && !instrumentRegisters && !instrumentMemories && !instrumentWires + } + + private def collectOptions(annos: AnnotationSeq): Options = Options( + instrumentPorts = annos.contains(PortToggleCoverage), + instrumentRegisters = annos.contains(RegisterToggleCoverage), + instrumentMemories = annos.contains(MemoryToggleCoverage), + instrumentWires = annos.contains(WireToggleCoverage) + ) + + override protected def execute(state: CircuitState): CircuitState = { + if (state.annotations.contains(SkipToggleCoverageAnnotation)) { + logger.info("[ToggleCoverage] skipping due to SkipToggleCoverage annotation") + return state + } + + // collect options and modules to ignore + val opt = collectOptions(state.annotations) + if (opt.noCoverage) { + logger.info("[ToggleCoverage] nothing to do since no coverage options were specified") + return state + } + + // collect global alias information + val iGraph = InstanceKeyGraph(state.circuit) + val aliases = AliasAnalysis.findAliases(state.circuit, iGraph) + + // Since modules can be excluded from coverage, this means that we might have to treat more than one + // module as a toplevel module. + val ignoreMods = Coverage.collectModulesToIgnore(state) + val instantiatedInIgnoredModule = + iGraph.getChildInstances.filter { case (name, _) => ignoreMods(name) }.flatMap(_._2.map(_.module)).toSet + val isTop = Set(state.circuit.main) | instantiatedInIgnoredModule + + // we first instrument each module in isolation + val newAnnos = new Annos() + val c = CircuitTarget(state.circuit.main) + val ms = state.circuit.modules.map(m => onModule(m, c, newAnnos, ignoreMods, opt, aliases(m.name), isTop)) + val circuit = state.circuit.copy(modules = ms.map(_._1)) + + // as a second step we add information to our annotations for signals that cross module boundaries + val portAliases = ms.map { case (m, a, _) => m.name -> a }.toMap + resolvePortAliases(c, newAnnos, portAliases, iGraph) + + val annos = newAnnos ++ ms.flatMap(_._3).toList ++ state.annotations + CircuitState(circuit, annos.toSeq) + } + + private def resolvePortAliases( + c: CircuitTarget, + annos: Annos, + iAliases: Map[String, PortAliases], + iGraph: InstanceKeyGraph + ): Unit = { + val signalToAnnoIds: Map[String, Seq[Int]] = + annos.zipWithIndex.flatMap { case (a, i) => a.signals.map(s => s.toString() -> i) } + .groupBy(_._1) + .map { case (k, v) => k -> v.map(_._2).toSeq } + + // make alias table mutable, so that we can propagate aliases up the hierarchy + val aliases = mutable.HashMap[String, PortAliases]() ++ iAliases + + // go through modules top to bottom + val moduleOrderBottomUp = iGraph.moduleOrder.reverseIterator + val childInstances = iGraph.getChildInstances.toMap + + moduleOrderBottomUp.foreach { m => + val mTarget = c.module(m.name) + val localSignalToPort = aliases(m.name).flatMap { case (port, signals) => + signals.map(_.toString() -> port) + }.toMap + // look at all instances in this module and check to see if any of them have declared port aliases + childInstances(m.name).foreach { child => + val as = aliases.getOrElse(child.module, List()) + as.foreach { case (port, signals) => + val portKey = mTarget.ref(child.name).field(port).toString() + signalToAnnoIds.get(portKey) match { + case Some(annoIds) => + annoIds.foreach { aId => + val old = annos(aId) + annos(aId) = old.copy(signals = old.signals ++ signals) + } + case None => + // if there are no annotations for this signal, we know that the signal is actually sampled + // even further up the hierarchy + val localPort = localSignalToPort(portKey) + val prev = aliases.getOrElse(m.name, List()) + aliases(m.name) = (localPort, signals) +: prev + } + } + } + } + } + + private type Annos = mutable.ArrayBuffer[ToggleCoverageAnnotation] + private case class ModuleCtx( + annos: Annos, + namespace: Namespace, + m: ModuleTarget, + en: ir.Reference, + clk: ir.Expression) + + // map from port name to signals associated with that port + private type PortAliases = Seq[(String, Seq[ReferenceTarget])] + + private def onModule( + m: ir.DefModule, + c: CircuitTarget, + annos: Annos, + ignore: Set[String], + opt: Options, + aliases: AliasAnalysis.Aliases, + isTop: String => Boolean + ): (ir.DefModule, PortAliases, Option[Annotation]) = + m match { + case mod: ir.Module if !ignore(mod.name) => + // first we check to see which signals we want to cover + val allSignals = collectSignals(mod) + val signals = filterSignals(allSignals, opt) + + if (signals.isEmpty) { (mod, List(), None) } + else { + Builder.findClock(mod, logger) match { + case None => (mod, List(), None) + case Some(clock) => + val namespace = Namespace(mod) + namespace.newName(Prefix) + // create a module wide signal that indicates whether the toggle coverage is active + val en = ir.Reference(namespace.newName("enToggle"), Utils.BoolType, RegKind, UnknownFlow) + val ctx = ModuleCtx(annos, namespace, c.module(mod.name), en, clock) + val (coverStmts, portAliases) = coverSignals(signals, aliases, ctx, isTop(mod.name)) + if (coverStmts.nonEmpty) { + // create actual hardware to generate enable signal + val (enStmt, enAnno) = buildCoverEnable(ctx, opt.resetAware) + val body = ir.Block(mod.body, enStmt, ir.Block(coverStmts)) + (mod.copy(body = body), portAliases, Some(enAnno)) + } else { (mod, portAliases, None) } + } + } + case other => (other, List(), None) + } + + private type Signals = Seq[Signal] + case class Signal(ref: ir.RefLikeExpression, info: ir.Info) { + def name: String = ref.serialize + } + + private def filterSignals(signals: Signals, opt: Options): Signals = signals.filter { sig => + val tpeCheck = sig.ref.tpe match { + case ir.UIntType(ir.IntWidth(w)) => w <= opt.maxWidth + case ir.SIntType(ir.IntWidth(w)) => w <= opt.maxWidth + // we don't want to instrument clocks or asynchronous signals + case _ => false + } + val kindCheck = getKind(sig.ref) match { + case MemKind => opt.instrumentMemories + case RegKind => opt.instrumentRegisters + case WireKind => opt.instrumentWires + case NodeKind => opt.instrumentWires + case PortKind => opt.instrumentPorts + case InstanceKind => opt.instrumentPorts + case other => throw new NotImplementedError(s"Unexpected signal kind: $other") + } + tpeCheck && kindCheck + } + private def getKind(ref: ir.RefLikeExpression): firrtl2.Kind = ref match { + case ir.Reference(_, _, kind, _) => kind + case ir.SubField(expr, _, _, _) => getKind(expr.asInstanceOf[ir.RefLikeExpression]) + case ir.SubIndex(expr, _, _, _) => getKind(expr.asInstanceOf[ir.RefLikeExpression]) + case ir.SubAccess(expr, _, _, _) => getKind(expr.asInstanceOf[ir.RefLikeExpression]) + } + + private def collectSignals(m: ir.Module): Signals = { + m.ports.map(p => Signal(ir.Reference(p), p.info)) ++ collectSignals(m.body) + } + private def collectSignals(s: ir.Statement): Signals = s match { + case n @ ir.DefNode(_, name, expr) if !isTemp(name) => List(Signal(ir.Reference(n), n.info)) + case w @ ir.DefWire(_, name, _) if !isTemp(name) => List(Signal(ir.Reference(w), w.info)) + case r: ir.DefRegister => List(Signal(ir.Reference(r), r.info)) + case m: ir.DefMemory => memRefs(m) + case i: ir.DefInstance => instRefs(i) + case ir.Block(stmts) => stmts.flatMap(collectSignals) + case ir.Conditionally(_, _, conseq, alt) => List(conseq, alt).flatMap(collectSignals) + case _ => List() + } + private def isTemp(name: String): Boolean = name.startsWith("_") + private def instRefs(i: ir.DefInstance): Signals = { + val iRef = ir.Reference(i) + getFields(iRef.tpe).map { case ir.Field(name, flip, tpe) => + val portRef = ir.SubField(iRef, name, tpe, Utils.to_flow(Utils.to_dir(flip))) + Signal(portRef, i.info) + } + } + private def memRefs(m: ir.DefMemory): Signals = { + val memRef = ir.Reference(m) + getFields(memRef.tpe).flatMap { case ir.Field(name, flip, tpe) => + val portRef = ir.SubField(memRef, name, tpe, Utils.to_flow(Utils.to_dir(flip))) + getFields(tpe).map { case ir.Field(name, flip, tpe) => + val fieldRef = ir.SubField(portRef, name, tpe, Utils.to_flow(Utils.to_dir(flip))) + Signal(fieldRef, m.info) + } + } + } + private def getFields(t: ir.Type): Seq[ir.Field] = t.asInstanceOf[ir.BundleType].fields + + private def buildCoverEnable(ctx: ModuleCtx, resetAware: Boolean): (ir.Statement, Annotation) = { + assert(!resetAware, "TODO: reset aware") + + // we add a simple register in order to disable toggle coverage in the first cycle + val ref = ctx.en + val reg = ir.DefRegister(ir.NoInfo, ref.name, Utils.BoolType, ctx.clk, Utils.False(), Utils.False()) + val next = ir.Connect(ir.NoInfo, ref, Utils.True()) + val presetAnno = PresetRegAnnotation(ctx.m.ref(reg.name)) + + (ir.Block(reg, next), presetAnno) + } + + private def coverSignals(signals: Signals, aliases: AliasAnalysis.Aliases, ctx: ModuleCtx, isTop: Boolean) + : (Seq[ir.Statement], PortAliases) = { + // first we group the signals using the alias information + val signalsByName = signals.map(s => s.name -> s).toMap + val aliased = mutable.HashSet[String]() + val signalGroups: Seq[Signals] = aliases.flatMap { g => + val signalsInGroup = g.filter(n => signalsByName.contains(n)) + if (signalsInGroup.size > 1) { + signalsInGroup.foreach(aliased.add) + val signals: Signals = signalsInGroup.map(signalsByName(_)) + Some(signals) + } else { None } + } + val nonAliasedSignals = signals.filterNot(s => aliased(s.name)).map(s => List(s)) + + val groups = signalGroups ++ nonAliasedSignals + val portAliases = mutable.ListBuffer[(String, Seq[ReferenceTarget])]() + val stmts = groups.flatMap { g => + // see if this group includes a port + val ports = g.filter(s => getKind(s.ref) == PortKind) + val hasPort = ports.nonEmpty + + // if we cover ports, then we might ignore this group as it will get covered in the module above ours + val skipPort = hasPort && !isTop + if (!skipPort) { + // cover one of the signals in the group + val (stmt, names) = addCover(g.head, ctx) + // add annotations for all + addAnno(g, names, ctx) + Some(stmt) + } else { + // We remember the signals that alias with the port so that they can be added to the annotation + // in a module further up the hierarchy. + val signalTargets = g.map(s => refToTarget(ctx.m, s.ref)).toList + portAliases.prepend(ports.head.name -> signalTargets) + None + } + } + + (stmts, portAliases.toList) + } + + private def addAnno(signals: Signals, names: Seq[String], ctx: ModuleCtx): Unit = { + names.zipWithIndex.foreach { case (coverName, bit) => + val sigs = signals.map(s => refToTarget(ctx.m, s.ref)).toList + val anno = ToggleCoverageAnnotation(ctx.m.ref(coverName), sigs, bit) + ctx.annos.prepend(anno) + } + } + + private def refToTarget(m: ModuleTarget, ref: ir.RefLikeExpression): ReferenceTarget = ref match { + case ir.Reference(name, _, _, _) => m.ref(name) + case ir.SubField(ir.Reference(name, _, _, _), field, _, _) => m.ref(name).field(field) + case ir.SubField(ir.SubField(ir.Reference(name, _, _, _), field1, _, _), field2, _, _) => + m.ref(name).field(field1).field(field2) + case other => throw new NotImplementedError(s"Unsupported reference: $other") + } + + private def addCover(signal: Signal, ctx: ModuleCtx): (ir.Statement, Seq[String]) = { + val (prevStmt, prevRef) = buildPrevReg(signal, ctx) + + // TODO: do we want to distinguish the type of toggle? + val width = Builder.getWidth(signal.ref.tpe).toInt + val didToggleName = makeName(signal.ref, ctx.namespace, "_t") + val didToggleNode = ir.DefNode( + signal.info, + didToggleName, + ir.DoPrim(firrtl2.PrimOps.Xor, List(signal.ref, prevRef), List(), ir.UIntType(ir.IntWidth(width))) + ) + val didToggle = ir.Reference(didToggleNode) + + val covers = (0 until width).map { ii => + val name = ctx.namespace.newName(Prefix) + val pred = ir.DoPrim(firrtl2.PrimOps.Bits, List(didToggle), List(ii, ii), Utils.BoolType) + val cover = ir.Verification(ir.Formal.Cover, signal.info, ctx.clk, pred, ctx.en, ir.StringLit(""), name) + (name, cover) + } + + val stmts = prevStmt ++ Seq(didToggleNode) ++ covers.map(_._2) + (ir.Block(stmts), covers.map(_._1)) + } + + private def buildPrevReg(signal: Signal, ctx: ModuleCtx): (Seq[ir.Statement], ir.Reference) = { + // build a register to hold the previous value + val prevName = makeName(signal.ref, ctx.namespace, "_p") + val prevRef = ir.Reference(prevName, signal.ref.tpe, RegKind, UnknownFlow) + val prevReg = + ir.DefRegister(signal.info, prevName, signal.ref.tpe, clock = ctx.clk, reset = Utils.False(), init = prevRef) + val next = ir.Connect(signal.info, prevRef, signal.ref) + (List(prevReg, next), prevRef) + } + + private def makeName(ref: ir.RefLikeExpression, namespace: Namespace, suffix: String): String = { + namespace.newName(ref.serialize.replace('.', '_') + suffix) + } +} diff --git a/src/test/resources/coverage/RiscVMiniTileTester.anno.json b/src/test/resources/coverage/RiscVMiniTileTester.anno.json new file mode 100644 index 000000000..d8e2637a1 --- /dev/null +++ b/src/test/resources/coverage/RiscVMiniTileTester.anno.json @@ -0,0 +1,36 @@ +[ + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"CacheState", + "definition":{ + "Idle":0, + "ReadCache":1, + "WriteCache":2, + "WriteBack":3, + "WriteAck":4, + "RefillReady":5, + "Refill":6 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"TileTester.Cache.state", + "enumTypeName":"CacheState" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"MemArbiterState", + "definition":{ + "Idle":0, + "ICacheRead":1, + "DCacheRead":2, + "DCacheWrite":3, + "DCacheAck":4 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"TileTester.MemArbiter.state", + "enumTypeName":"MemArbiterState" + }, +] \ No newline at end of file diff --git a/src/test/resources/coverage/RiscVMiniTileTester.fir b/src/test/resources/coverage/RiscVMiniTileTester.fir new file mode 100644 index 000000000..77c886e37 --- /dev/null +++ b/src/test/resources/coverage/RiscVMiniTileTester.fir @@ -0,0 +1,7187 @@ +circuit TileTester : + module CSR : + input clock : Clock + input reset : Reset + output io : { flip stall : UInt<1>, flip cmd : UInt<3>, flip in : UInt<32>, out : UInt<32>, flip pc : UInt<32>, flip addr : UInt<32>, flip inst : UInt<32>, flip illegal : UInt<1>, flip st_type : UInt<2>, flip ld_type : UInt<3>, flip pc_check : UInt<1>, expt : UInt<1>, evec : UInt<32>, epc : UInt<32>, host : { flip fromhost : { valid : UInt<1>, bits : UInt<32>}, tohost : UInt<32>}} + + node csr_addr = bits(io.inst, 31, 20) @[CSR.scala 100:25] + node rs1_addr = bits(io.inst, 19, 15) @[CSR.scala 101:25] + reg time : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[CSR.scala 104:25] + reg timeh : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[CSR.scala 105:25] + reg cycle : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[CSR.scala 106:25] + reg cycleh : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[CSR.scala 107:25] + reg instret : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[CSR.scala 108:25] + reg instreth : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[CSR.scala 109:25] + node _T = cat(UInt<2>("h0"), UInt<4>("h0")) @[Cat.scala 30:58] + node mcpuid = cat(_T, UInt<26>("h100100")) @[Cat.scala 30:58] + reg PRV : UInt<2>, clock with : + reset => (reset, UInt<2>("h3")) @[CSR.scala 118:21] + reg PRV1 : UInt<2>, clock with : + reset => (reset, UInt<2>("h3")) @[CSR.scala 119:21] + reg IE : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[CSR.scala 122:20] + reg IE1 : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[CSR.scala 123:20] + node _T_1 = cat(IE1, PRV) @[Cat.scala 30:58] + node _T_2 = cat(_T_1, IE) @[Cat.scala 30:58] + node _T_3 = cat(UInt<1>("h0"), PRV1) @[Cat.scala 30:58] + node _T_4 = cat(UInt<1>("h0"), UInt<2>("h0")) @[Cat.scala 30:58] + node _T_5 = cat(_T_4, _T_3) @[Cat.scala 30:58] + node _T_6 = cat(_T_5, _T_2) @[Cat.scala 30:58] + node _T_7 = cat(UInt<2>("h0"), UInt<2>("h0")) @[Cat.scala 30:58] + node _T_8 = cat(_T_7, UInt<2>("h0")) @[Cat.scala 30:58] + node _T_9 = cat(UInt<5>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_10 = cat(UInt<1>("h0"), UInt<9>("h0")) @[Cat.scala 30:58] + node _T_11 = cat(_T_10, _T_9) @[Cat.scala 30:58] + node _T_12 = cat(_T_11, _T_8) @[Cat.scala 30:58] + node mstatus = cat(_T_12, _T_6) @[Cat.scala 30:58] + reg MTIP : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[CSR.scala 139:21] + reg MTIE : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[CSR.scala 142:21] + reg MSIP : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[CSR.scala 145:21] + reg MSIE : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[CSR.scala 148:21] + node _T_13 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_14 = cat(MSIP, UInt<1>("h0")) @[Cat.scala 30:58] + node _T_15 = cat(_T_14, _T_13) @[Cat.scala 30:58] + node _T_16 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_17 = cat(UInt<24>("h0"), MTIP) @[Cat.scala 30:58] + node _T_18 = cat(_T_17, UInt<1>("h0")) @[Cat.scala 30:58] + node _T_19 = cat(_T_18, _T_16) @[Cat.scala 30:58] + node mip = cat(_T_19, _T_15) @[Cat.scala 30:58] + node _T_20 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_21 = cat(MSIE, UInt<1>("h0")) @[Cat.scala 30:58] + node _T_22 = cat(_T_21, _T_20) @[Cat.scala 30:58] + node _T_23 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_24 = cat(UInt<24>("h0"), MTIE) @[Cat.scala 30:58] + node _T_25 = cat(_T_24, UInt<1>("h0")) @[Cat.scala 30:58] + node _T_26 = cat(_T_25, _T_23) @[Cat.scala 30:58] + node mie = cat(_T_26, _T_22) @[Cat.scala 30:58] + reg mtimecmp : UInt<32>, clock with : + reset => (UInt<1>("h0"), mtimecmp) @[CSR.scala 154:21] + reg mscratch : UInt<32>, clock with : + reset => (UInt<1>("h0"), mscratch) @[CSR.scala 156:21] + reg mepc : UInt<32>, clock with : + reset => (UInt<1>("h0"), mepc) @[CSR.scala 158:17] + reg mcause : UInt<32>, clock with : + reset => (UInt<1>("h0"), mcause) @[CSR.scala 159:19] + reg mbadaddr : UInt<32>, clock with : + reset => (UInt<1>("h0"), mbadaddr) @[CSR.scala 160:21] + reg mtohost : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[CSR.scala 162:24] + reg mfromhost : UInt<32>, clock with : + reset => (UInt<1>("h0"), mfromhost) @[CSR.scala 163:22] + io.host.tohost <= mtohost @[CSR.scala 164:18] + when io.host.fromhost.valid : @[CSR.scala 165:32] + mfromhost <= io.host.fromhost.bits @[CSR.scala 166:15] + node _T_27 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_28 = eq(UInt<12>("hc00"), _T_27) @[Lookup.scala 31:38] + node _T_29 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_30 = eq(UInt<12>("hc01"), _T_29) @[Lookup.scala 31:38] + node _T_31 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_32 = eq(UInt<12>("hc02"), _T_31) @[Lookup.scala 31:38] + node _T_33 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_34 = eq(UInt<12>("hc80"), _T_33) @[Lookup.scala 31:38] + node _T_35 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_36 = eq(UInt<12>("hc81"), _T_35) @[Lookup.scala 31:38] + node _T_37 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_38 = eq(UInt<12>("hc82"), _T_37) @[Lookup.scala 31:38] + node _T_39 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_40 = eq(UInt<12>("h900"), _T_39) @[Lookup.scala 31:38] + node _T_41 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_42 = eq(UInt<12>("h901"), _T_41) @[Lookup.scala 31:38] + node _T_43 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_44 = eq(UInt<12>("h902"), _T_43) @[Lookup.scala 31:38] + node _T_45 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_46 = eq(UInt<12>("h980"), _T_45) @[Lookup.scala 31:38] + node _T_47 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_48 = eq(UInt<12>("h981"), _T_47) @[Lookup.scala 31:38] + node _T_49 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_50 = eq(UInt<12>("h982"), _T_49) @[Lookup.scala 31:38] + node _T_51 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_52 = eq(UInt<12>("hf00"), _T_51) @[Lookup.scala 31:38] + node _T_53 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_54 = eq(UInt<12>("hf01"), _T_53) @[Lookup.scala 31:38] + node _T_55 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_56 = eq(UInt<12>("hf10"), _T_55) @[Lookup.scala 31:38] + node _T_57 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_58 = eq(UInt<10>("h301"), _T_57) @[Lookup.scala 31:38] + node _T_59 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_60 = eq(UInt<10>("h302"), _T_59) @[Lookup.scala 31:38] + node _T_61 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_62 = eq(UInt<10>("h304"), _T_61) @[Lookup.scala 31:38] + node _T_63 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_64 = eq(UInt<10>("h321"), _T_63) @[Lookup.scala 31:38] + node _T_65 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_66 = eq(UInt<11>("h701"), _T_65) @[Lookup.scala 31:38] + node _T_67 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_68 = eq(UInt<11>("h741"), _T_67) @[Lookup.scala 31:38] + node _T_69 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_70 = eq(UInt<10>("h340"), _T_69) @[Lookup.scala 31:38] + node _T_71 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_72 = eq(UInt<10>("h341"), _T_71) @[Lookup.scala 31:38] + node _T_73 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_74 = eq(UInt<10>("h342"), _T_73) @[Lookup.scala 31:38] + node _T_75 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_76 = eq(UInt<10>("h343"), _T_75) @[Lookup.scala 31:38] + node _T_77 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_78 = eq(UInt<10>("h344"), _T_77) @[Lookup.scala 31:38] + node _T_79 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_80 = eq(UInt<11>("h780"), _T_79) @[Lookup.scala 31:38] + node _T_81 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_82 = eq(UInt<11>("h781"), _T_81) @[Lookup.scala 31:38] + node _T_83 = and(csr_addr, UInt<12>("hfff")) @[Lookup.scala 31:38] + node _T_84 = eq(UInt<10>("h300"), _T_83) @[Lookup.scala 31:38] + node _T_85 = mux(_T_84, mstatus, UInt<1>("h0")) @[Lookup.scala 33:37] + node _T_86 = mux(_T_82, mfromhost, _T_85) @[Lookup.scala 33:37] + node _T_87 = mux(_T_80, mtohost, _T_86) @[Lookup.scala 33:37] + node _T_88 = mux(_T_78, mip, _T_87) @[Lookup.scala 33:37] + node _T_89 = mux(_T_76, mbadaddr, _T_88) @[Lookup.scala 33:37] + node _T_90 = mux(_T_74, mcause, _T_89) @[Lookup.scala 33:37] + node _T_91 = mux(_T_72, mepc, _T_90) @[Lookup.scala 33:37] + node _T_92 = mux(_T_70, mscratch, _T_91) @[Lookup.scala 33:37] + node _T_93 = mux(_T_68, timeh, _T_92) @[Lookup.scala 33:37] + node _T_94 = mux(_T_66, time, _T_93) @[Lookup.scala 33:37] + node _T_95 = mux(_T_64, mtimecmp, _T_94) @[Lookup.scala 33:37] + node _T_96 = mux(_T_62, mie, _T_95) @[Lookup.scala 33:37] + node _T_97 = mux(_T_60, UInt<32>("h0"), _T_96) @[Lookup.scala 33:37] + node _T_98 = mux(_T_58, UInt<32>("h100"), _T_97) @[Lookup.scala 33:37] + node _T_99 = mux(_T_56, UInt<32>("h0"), _T_98) @[Lookup.scala 33:37] + node _T_100 = mux(_T_54, UInt<32>("h0"), _T_99) @[Lookup.scala 33:37] + node _T_101 = mux(_T_52, mcpuid, _T_100) @[Lookup.scala 33:37] + node _T_102 = mux(_T_50, instreth, _T_101) @[Lookup.scala 33:37] + node _T_103 = mux(_T_48, timeh, _T_102) @[Lookup.scala 33:37] + node _T_104 = mux(_T_46, cycleh, _T_103) @[Lookup.scala 33:37] + node _T_105 = mux(_T_44, instret, _T_104) @[Lookup.scala 33:37] + node _T_106 = mux(_T_42, time, _T_105) @[Lookup.scala 33:37] + node _T_107 = mux(_T_40, cycle, _T_106) @[Lookup.scala 33:37] + node _T_108 = mux(_T_38, instreth, _T_107) @[Lookup.scala 33:37] + node _T_109 = mux(_T_36, timeh, _T_108) @[Lookup.scala 33:37] + node _T_110 = mux(_T_34, cycleh, _T_109) @[Lookup.scala 33:37] + node _T_111 = mux(_T_32, instret, _T_110) @[Lookup.scala 33:37] + node _T_112 = mux(_T_30, time, _T_111) @[Lookup.scala 33:37] + node _T_113 = mux(_T_28, cycle, _T_112) @[Lookup.scala 33:37] + io.out <= _T_113 @[CSR.scala 201:10] + node _T_114 = bits(csr_addr, 9, 8) @[CSR.scala 203:27] + node privValid = leq(_T_114, PRV) @[CSR.scala 203:34] + node privInst = eq(io.cmd, UInt<3>("h4")) @[CSR.scala 204:26] + node _T_115 = bits(csr_addr, 0, 0) @[CSR.scala 205:40] + node _T_116 = eq(_T_115, UInt<1>("h0")) @[CSR.scala 205:31] + node _T_117 = and(privInst, _T_116) @[CSR.scala 205:28] + node _T_118 = bits(csr_addr, 8, 8) @[CSR.scala 205:56] + node _T_119 = eq(_T_118, UInt<1>("h0")) @[CSR.scala 205:47] + node isEcall = and(_T_117, _T_119) @[CSR.scala 205:44] + node _T_120 = bits(csr_addr, 0, 0) @[CSR.scala 206:40] + node _T_121 = and(privInst, _T_120) @[CSR.scala 206:28] + node _T_122 = bits(csr_addr, 8, 8) @[CSR.scala 206:56] + node _T_123 = eq(_T_122, UInt<1>("h0")) @[CSR.scala 206:47] + node isEbreak = and(_T_121, _T_123) @[CSR.scala 206:44] + node _T_124 = bits(csr_addr, 0, 0) @[CSR.scala 207:40] + node _T_125 = eq(_T_124, UInt<1>("h0")) @[CSR.scala 207:31] + node _T_126 = and(privInst, _T_125) @[CSR.scala 207:28] + node _T_127 = bits(csr_addr, 8, 8) @[CSR.scala 207:56] + node isEret = and(_T_126, _T_127) @[CSR.scala 207:44] + node _T_128 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_129 = eq(UInt<12>("hc00"), _T_128) @[CSR.scala 208:37] + node _T_130 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_131 = eq(UInt<12>("hc01"), _T_130) @[CSR.scala 208:37] + node _T_132 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_133 = eq(UInt<12>("hc02"), _T_132) @[CSR.scala 208:37] + node _T_134 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_135 = eq(UInt<12>("hc80"), _T_134) @[CSR.scala 208:37] + node _T_136 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_137 = eq(UInt<12>("hc81"), _T_136) @[CSR.scala 208:37] + node _T_138 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_139 = eq(UInt<12>("hc82"), _T_138) @[CSR.scala 208:37] + node _T_140 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_141 = eq(UInt<12>("h900"), _T_140) @[CSR.scala 208:37] + node _T_142 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_143 = eq(UInt<12>("h901"), _T_142) @[CSR.scala 208:37] + node _T_144 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_145 = eq(UInt<12>("h902"), _T_144) @[CSR.scala 208:37] + node _T_146 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_147 = eq(UInt<12>("h980"), _T_146) @[CSR.scala 208:37] + node _T_148 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_149 = eq(UInt<12>("h981"), _T_148) @[CSR.scala 208:37] + node _T_150 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_151 = eq(UInt<12>("h982"), _T_150) @[CSR.scala 208:37] + node _T_152 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_153 = eq(UInt<12>("hf00"), _T_152) @[CSR.scala 208:37] + node _T_154 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_155 = eq(UInt<12>("hf01"), _T_154) @[CSR.scala 208:37] + node _T_156 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_157 = eq(UInt<12>("hf10"), _T_156) @[CSR.scala 208:37] + node _T_158 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_159 = eq(UInt<10>("h301"), _T_158) @[CSR.scala 208:37] + node _T_160 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_161 = eq(UInt<10>("h302"), _T_160) @[CSR.scala 208:37] + node _T_162 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_163 = eq(UInt<10>("h304"), _T_162) @[CSR.scala 208:37] + node _T_164 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_165 = eq(UInt<10>("h321"), _T_164) @[CSR.scala 208:37] + node _T_166 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_167 = eq(UInt<11>("h701"), _T_166) @[CSR.scala 208:37] + node _T_168 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_169 = eq(UInt<11>("h741"), _T_168) @[CSR.scala 208:37] + node _T_170 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_171 = eq(UInt<10>("h340"), _T_170) @[CSR.scala 208:37] + node _T_172 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_173 = eq(UInt<10>("h341"), _T_172) @[CSR.scala 208:37] + node _T_174 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_175 = eq(UInt<10>("h342"), _T_174) @[CSR.scala 208:37] + node _T_176 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_177 = eq(UInt<10>("h343"), _T_176) @[CSR.scala 208:37] + node _T_178 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_179 = eq(UInt<10>("h344"), _T_178) @[CSR.scala 208:37] + node _T_180 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_181 = eq(UInt<11>("h780"), _T_180) @[CSR.scala 208:37] + node _T_182 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_183 = eq(UInt<11>("h781"), _T_182) @[CSR.scala 208:37] + node _T_184 = and(csr_addr, UInt<12>("hfff")) @[CSR.scala 208:37] + node _T_185 = eq(UInt<10>("h300"), _T_184) @[CSR.scala 208:37] + node _T_186 = or(_T_129, _T_131) @[CSR.scala 208:61] + node _T_187 = or(_T_186, _T_133) @[CSR.scala 208:61] + node _T_188 = or(_T_187, _T_135) @[CSR.scala 208:61] + node _T_189 = or(_T_188, _T_137) @[CSR.scala 208:61] + node _T_190 = or(_T_189, _T_139) @[CSR.scala 208:61] + node _T_191 = or(_T_190, _T_141) @[CSR.scala 208:61] + node _T_192 = or(_T_191, _T_143) @[CSR.scala 208:61] + node _T_193 = or(_T_192, _T_145) @[CSR.scala 208:61] + node _T_194 = or(_T_193, _T_147) @[CSR.scala 208:61] + node _T_195 = or(_T_194, _T_149) @[CSR.scala 208:61] + node _T_196 = or(_T_195, _T_151) @[CSR.scala 208:61] + node _T_197 = or(_T_196, _T_153) @[CSR.scala 208:61] + node _T_198 = or(_T_197, _T_155) @[CSR.scala 208:61] + node _T_199 = or(_T_198, _T_157) @[CSR.scala 208:61] + node _T_200 = or(_T_199, _T_159) @[CSR.scala 208:61] + node _T_201 = or(_T_200, _T_161) @[CSR.scala 208:61] + node _T_202 = or(_T_201, _T_163) @[CSR.scala 208:61] + node _T_203 = or(_T_202, _T_165) @[CSR.scala 208:61] + node _T_204 = or(_T_203, _T_167) @[CSR.scala 208:61] + node _T_205 = or(_T_204, _T_169) @[CSR.scala 208:61] + node _T_206 = or(_T_205, _T_171) @[CSR.scala 208:61] + node _T_207 = or(_T_206, _T_173) @[CSR.scala 208:61] + node _T_208 = or(_T_207, _T_175) @[CSR.scala 208:61] + node _T_209 = or(_T_208, _T_177) @[CSR.scala 208:61] + node _T_210 = or(_T_209, _T_179) @[CSR.scala 208:61] + node _T_211 = or(_T_210, _T_181) @[CSR.scala 208:61] + node _T_212 = or(_T_211, _T_183) @[CSR.scala 208:61] + node csrValid = or(_T_212, _T_185) @[CSR.scala 208:61] + node _T_213 = bits(csr_addr, 11, 10) @[CSR.scala 209:27] + node _T_214 = andr(_T_213) @[CSR.scala 209:36] + node _T_215 = eq(csr_addr, UInt<12>("h301")) @[CSR.scala 209:53] + node _T_216 = or(_T_214, _T_215) @[CSR.scala 209:41] + node _T_217 = eq(csr_addr, UInt<12>("h302")) @[CSR.scala 209:79] + node csrRO = or(_T_216, _T_217) @[CSR.scala 209:67] + node _T_218 = eq(io.cmd, UInt<3>("h1")) @[CSR.scala 210:26] + node _T_219 = bits(io.cmd, 1, 1) @[CSR.scala 210:45] + node _T_220 = orr(rs1_addr) @[CSR.scala 210:61] + node _T_221 = and(_T_219, _T_220) @[CSR.scala 210:49] + node wen = or(_T_218, _T_221) @[CSR.scala 210:36] + node _T_222 = or(io.out, io.in) @[CSR.scala 213:22] + node _T_223 = not(io.in) @[CSR.scala 214:24] + node _T_224 = and(io.out, _T_223) @[CSR.scala 214:22] + node _T_225 = eq(UInt<3>("h1"), io.cmd) @[Mux.scala 80:60] + node _T_226 = mux(_T_225, io.in, UInt<1>("h0")) @[Mux.scala 80:57] + node _T_227 = eq(UInt<3>("h2"), io.cmd) @[Mux.scala 80:60] + node _T_228 = mux(_T_227, _T_222, _T_226) @[Mux.scala 80:57] + node _T_229 = eq(UInt<3>("h3"), io.cmd) @[Mux.scala 80:60] + node wdata = mux(_T_229, _T_224, _T_228) @[Mux.scala 80:57] + node _T_230 = bits(io.addr, 1, 1) @[CSR.scala 216:44] + node iaddrInvalid = and(io.pc_check, _T_230) @[CSR.scala 216:34] + node _T_231 = bits(io.addr, 1, 0) @[CSR.scala 218:29] + node _T_232 = orr(_T_231) @[CSR.scala 218:36] + node _T_233 = bits(io.addr, 0, 0) @[CSR.scala 218:65] + node _T_234 = bits(io.addr, 0, 0) @[CSR.scala 218:95] + node _T_235 = eq(UInt<3>("h1"), io.ld_type) @[Mux.scala 80:60] + node _T_236 = mux(_T_235, _T_232, UInt<1>("h0")) @[Mux.scala 80:57] + node _T_237 = eq(UInt<3>("h2"), io.ld_type) @[Mux.scala 80:60] + node _T_238 = mux(_T_237, _T_233, _T_236) @[Mux.scala 80:57] + node _T_239 = eq(UInt<3>("h4"), io.ld_type) @[Mux.scala 80:60] + node laddrInvalid = mux(_T_239, _T_234, _T_238) @[Mux.scala 80:57] + node _T_240 = bits(io.addr, 1, 0) @[CSR.scala 220:29] + node _T_241 = orr(_T_240) @[CSR.scala 220:36] + node _T_242 = bits(io.addr, 0, 0) @[CSR.scala 220:65] + node _T_243 = eq(UInt<2>("h1"), io.st_type) @[Mux.scala 80:60] + node _T_244 = mux(_T_243, _T_241, UInt<1>("h0")) @[Mux.scala 80:57] + node _T_245 = eq(UInt<2>("h2"), io.st_type) @[Mux.scala 80:60] + node saddrInvalid = mux(_T_245, _T_242, _T_244) @[Mux.scala 80:57] + node _T_246 = or(io.illegal, iaddrInvalid) @[CSR.scala 221:25] + node _T_247 = or(_T_246, laddrInvalid) @[CSR.scala 221:41] + node _T_248 = or(_T_247, saddrInvalid) @[CSR.scala 221:57] + node _T_249 = bits(io.cmd, 1, 0) @[CSR.scala 222:20] + node _T_250 = orr(_T_249) @[CSR.scala 222:27] + node _T_251 = eq(csrValid, UInt<1>("h0")) @[CSR.scala 222:35] + node _T_252 = eq(privValid, UInt<1>("h0")) @[CSR.scala 222:48] + node _T_253 = or(_T_251, _T_252) @[CSR.scala 222:45] + node _T_254 = and(_T_250, _T_253) @[CSR.scala 222:31] + node _T_255 = or(_T_248, _T_254) @[CSR.scala 221:73] + node _T_256 = and(wen, csrRO) @[CSR.scala 222:67] + node _T_257 = or(_T_255, _T_256) @[CSR.scala 222:60] + node _T_258 = eq(privValid, UInt<1>("h0")) @[CSR.scala 223:27] + node _T_259 = and(privInst, _T_258) @[CSR.scala 223:24] + node _T_260 = or(_T_257, _T_259) @[CSR.scala 222:76] + node _T_261 = or(_T_260, isEcall) @[CSR.scala 223:39] + node _T_262 = or(_T_261, isEbreak) @[CSR.scala 223:50] + io.expt <= _T_262 @[CSR.scala 221:11] + node _T_263 = shl(PRV, 6) @[CSR.scala 224:27] + node _T_264 = add(UInt<32>("h100"), _T_263) @[CSR.scala 224:20] + node _T_265 = tail(_T_264, 1) @[CSR.scala 224:20] + io.evec <= _T_265 @[CSR.scala 224:11] + io.epc <= mepc @[CSR.scala 225:11] + node _T_266 = add(time, UInt<1>("h1")) @[CSR.scala 228:16] + node _T_267 = tail(_T_266, 1) @[CSR.scala 228:16] + time <= _T_267 @[CSR.scala 228:8] + node _T_268 = andr(time) @[CSR.scala 229:13] + when _T_268 : @[CSR.scala 229:19] + node _T_269 = add(timeh, UInt<1>("h1")) @[CSR.scala 229:36] + node _T_270 = tail(_T_269, 1) @[CSR.scala 229:36] + timeh <= _T_270 @[CSR.scala 229:27] + node _T_271 = add(cycle, UInt<1>("h1")) @[CSR.scala 230:18] + node _T_272 = tail(_T_271, 1) @[CSR.scala 230:18] + cycle <= _T_272 @[CSR.scala 230:9] + node _T_273 = andr(cycle) @[CSR.scala 231:14] + when _T_273 : @[CSR.scala 231:20] + node _T_274 = add(cycleh, UInt<1>("h1")) @[CSR.scala 231:39] + node _T_275 = tail(_T_274, 1) @[CSR.scala 231:39] + cycleh <= _T_275 @[CSR.scala 231:29] + node _T_276 = neq(io.inst, UInt<32>("h13")) @[CSR.scala 232:27] + node _T_277 = eq(io.expt, UInt<1>("h0")) @[CSR.scala 232:52] + node _T_278 = or(_T_277, isEcall) @[CSR.scala 232:61] + node _T_279 = or(_T_278, isEbreak) @[CSR.scala 232:72] + node _T_280 = and(_T_276, _T_279) @[CSR.scala 232:48] + node _T_281 = eq(io.stall, UInt<1>("h0")) @[CSR.scala 232:88] + node isInstRet = and(_T_280, _T_281) @[CSR.scala 232:85] + when isInstRet : @[CSR.scala 233:19] + node _T_282 = add(instret, UInt<1>("h1")) @[CSR.scala 233:40] + node _T_283 = tail(_T_282, 1) @[CSR.scala 233:40] + instret <= _T_283 @[CSR.scala 233:29] + node _T_284 = andr(instret) @[CSR.scala 234:29] + node _T_285 = and(isInstRet, _T_284) @[CSR.scala 234:18] + when _T_285 : @[CSR.scala 234:35] + node _T_286 = add(instreth, UInt<1>("h1")) @[CSR.scala 234:58] + node _T_287 = tail(_T_286, 1) @[CSR.scala 234:58] + instreth <= _T_287 @[CSR.scala 234:46] + node _T_288 = eq(io.stall, UInt<1>("h0")) @[CSR.scala 236:8] + when _T_288 : @[CSR.scala 236:19] + when io.expt : @[CSR.scala 237:19] + node _T_289 = shr(io.pc, 2) @[CSR.scala 238:23] + node _T_290 = shl(_T_289, 2) @[CSR.scala 238:28] + mepc <= _T_290 @[CSR.scala 238:14] + node _T_291 = add(UInt<4>("h8"), PRV) @[CSR.scala 242:47] + node _T_292 = tail(_T_291, 1) @[CSR.scala 242:47] + node _T_293 = mux(isEbreak, UInt<2>("h3"), UInt<2>("h2")) @[CSR.scala 243:20] + node _T_294 = mux(isEcall, _T_292, _T_293) @[CSR.scala 242:20] + node _T_295 = mux(saddrInvalid, UInt<3>("h6"), _T_294) @[CSR.scala 241:20] + node _T_296 = mux(laddrInvalid, UInt<3>("h4"), _T_295) @[CSR.scala 240:20] + node _T_297 = mux(iaddrInvalid, UInt<1>("h0"), _T_296) @[CSR.scala 239:20] + mcause <= _T_297 @[CSR.scala 239:14] + PRV <= UInt<2>("h3") @[CSR.scala 244:12] + IE <= UInt<1>("h0") @[CSR.scala 245:12] + PRV1 <= PRV @[CSR.scala 246:12] + IE1 <= IE @[CSR.scala 247:12] + node _T_298 = or(iaddrInvalid, laddrInvalid) @[CSR.scala 248:25] + node _T_299 = or(_T_298, saddrInvalid) @[CSR.scala 248:41] + when _T_299 : @[CSR.scala 248:58] + mbadaddr <= io.addr @[CSR.scala 248:69] + else : + when isEret : @[CSR.scala 249:24] + PRV <= PRV1 @[CSR.scala 250:12] + IE <= IE1 @[CSR.scala 251:12] + PRV1 <= UInt<2>("h0") @[CSR.scala 252:12] + IE1 <= UInt<1>("h1") @[CSR.scala 253:12] + else : + when wen : @[CSR.scala 254:21] + node _T_300 = eq(csr_addr, UInt<12>("h300")) @[CSR.scala 255:21] + when _T_300 : @[CSR.scala 255:38] + node _T_301 = bits(wdata, 5, 4) @[CSR.scala 256:22] + PRV1 <= _T_301 @[CSR.scala 256:14] + node _T_302 = bits(wdata, 3, 3) @[CSR.scala 257:22] + IE1 <= _T_302 @[CSR.scala 257:14] + node _T_303 = bits(wdata, 2, 1) @[CSR.scala 258:22] + PRV <= _T_303 @[CSR.scala 258:14] + node _T_304 = bits(wdata, 0, 0) @[CSR.scala 259:22] + IE <= _T_304 @[CSR.scala 259:14] + else : + node _T_305 = eq(csr_addr, UInt<12>("h344")) @[CSR.scala 261:26] + when _T_305 : @[CSR.scala 261:39] + node _T_306 = bits(wdata, 7, 7) @[CSR.scala 262:22] + MTIP <= _T_306 @[CSR.scala 262:14] + node _T_307 = bits(wdata, 3, 3) @[CSR.scala 263:22] + MSIP <= _T_307 @[CSR.scala 263:14] + else : + node _T_308 = eq(csr_addr, UInt<12>("h304")) @[CSR.scala 265:26] + when _T_308 : @[CSR.scala 265:39] + node _T_309 = bits(wdata, 7, 7) @[CSR.scala 266:22] + MTIE <= _T_309 @[CSR.scala 266:14] + node _T_310 = bits(wdata, 3, 3) @[CSR.scala 267:22] + MSIE <= _T_310 @[CSR.scala 267:14] + else : + node _T_311 = eq(csr_addr, UInt<12>("h701")) @[CSR.scala 269:26] + when _T_311 : @[CSR.scala 269:41] + time <= wdata @[CSR.scala 269:48] + else : + node _T_312 = eq(csr_addr, UInt<12>("h741")) @[CSR.scala 270:26] + when _T_312 : @[CSR.scala 270:42] + timeh <= wdata @[CSR.scala 270:50] + else : + node _T_313 = eq(csr_addr, UInt<12>("h321")) @[CSR.scala 271:26] + when _T_313 : @[CSR.scala 271:44] + mtimecmp <= wdata @[CSR.scala 271:55] + else : + node _T_314 = eq(csr_addr, UInt<12>("h340")) @[CSR.scala 272:26] + when _T_314 : @[CSR.scala 272:44] + mscratch <= wdata @[CSR.scala 272:55] + else : + node _T_315 = eq(csr_addr, UInt<12>("h341")) @[CSR.scala 273:26] + when _T_315 : @[CSR.scala 273:40] + node _T_316 = dshr(wdata, UInt<2>("h2")) @[CSR.scala 273:56] + node _T_317 = dshl(_T_316, UInt<2>("h2")) @[CSR.scala 273:63] + mepc <= _T_317 @[CSR.scala 273:47] + else : + node _T_318 = eq(csr_addr, UInt<12>("h342")) @[CSR.scala 274:26] + when _T_318 : @[CSR.scala 274:42] + node _T_319 = and(wdata, UInt<32>("h8000000f")) @[CSR.scala 274:60] + mcause <= _T_319 @[CSR.scala 274:51] + else : + node _T_320 = eq(csr_addr, UInt<12>("h343")) @[CSR.scala 275:26] + when _T_320 : @[CSR.scala 275:44] + mbadaddr <= wdata @[CSR.scala 275:55] + else : + node _T_321 = eq(csr_addr, UInt<12>("h780")) @[CSR.scala 276:26] + when _T_321 : @[CSR.scala 276:43] + mtohost <= wdata @[CSR.scala 276:53] + else : + node _T_322 = eq(csr_addr, UInt<12>("h781")) @[CSR.scala 277:26] + when _T_322 : @[CSR.scala 277:45] + mfromhost <= wdata @[CSR.scala 277:57] + else : + node _T_323 = eq(csr_addr, UInt<12>("h900")) @[CSR.scala 278:26] + when _T_323 : @[CSR.scala 278:42] + cycle <= wdata @[CSR.scala 278:50] + else : + node _T_324 = eq(csr_addr, UInt<12>("h901")) @[CSR.scala 279:26] + when _T_324 : @[CSR.scala 279:41] + time <= wdata @[CSR.scala 279:48] + else : + node _T_325 = eq(csr_addr, UInt<12>("h902")) @[CSR.scala 280:26] + when _T_325 : @[CSR.scala 280:44] + instret <= wdata @[CSR.scala 280:54] + else : + node _T_326 = eq(csr_addr, UInt<12>("h980")) @[CSR.scala 281:26] + when _T_326 : @[CSR.scala 281:43] + cycleh <= wdata @[CSR.scala 281:52] + else : + node _T_327 = eq(csr_addr, UInt<12>("h981")) @[CSR.scala 282:26] + when _T_327 : @[CSR.scala 282:42] + timeh <= wdata @[CSR.scala 282:50] + else : + node _T_328 = eq(csr_addr, UInt<12>("h982")) @[CSR.scala 283:26] + when _T_328 : @[CSR.scala 283:45] + instreth <= wdata @[CSR.scala 283:56] + + module RegFile : + input clock : Clock + input reset : Reset + output io : { flip raddr1 : UInt<5>, flip raddr2 : UInt<5>, rdata1 : UInt<32>, rdata2 : UInt<32>, flip wen : UInt<1>, flip waddr : UInt<5>, flip wdata : UInt<32>} + + cmem regs : UInt<32> [32] @[RegFile.scala 20:17] + node _T = orr(io.raddr1) @[RegFile.scala 21:30] + infer mport _T_1 = regs[io.raddr1], clock @[RegFile.scala 21:39] + node _T_2 = mux(_T, _T_1, UInt<1>("h0")) @[RegFile.scala 21:19] + io.rdata1 <= _T_2 @[RegFile.scala 21:13] + node _T_3 = orr(io.raddr2) @[RegFile.scala 22:30] + infer mport _T_4 = regs[io.raddr2], clock @[RegFile.scala 22:39] + node _T_5 = mux(_T_3, _T_4, UInt<1>("h0")) @[RegFile.scala 22:19] + io.rdata2 <= _T_5 @[RegFile.scala 22:13] + node _T_6 = orr(io.waddr) @[RegFile.scala 23:26] + node _T_7 = and(io.wen, _T_6) @[RegFile.scala 23:15] + when _T_7 : @[RegFile.scala 23:31] + infer mport _T_8 = regs[io.waddr], clock @[RegFile.scala 24:9] + _T_8 <= io.wdata @[RegFile.scala 24:20] + + module ALUArea : + input clock : Clock + input reset : Reset + output io : { flip A : UInt<32>, flip B : UInt<32>, flip alu_op : UInt<4>, out : UInt<32>, sum : UInt<32>} + + node _T = bits(io.alu_op, 0, 0) @[ALU.scala 64:33] + node _T_1 = sub(UInt<1>("h0"), io.B) @[ALU.scala 64:38] + node _T_2 = tail(_T_1, 1) @[ALU.scala 64:38] + node _T_3 = mux(_T, _T_2, io.B) @[ALU.scala 64:23] + node _T_4 = add(io.A, _T_3) @[ALU.scala 64:18] + node sum = tail(_T_4, 1) @[ALU.scala 64:18] + node _T_5 = bits(io.A, 31, 31) @[ALU.scala 65:21] + node _T_6 = bits(io.B, 31, 31) @[ALU.scala 65:38] + node _T_7 = eq(_T_5, _T_6) @[ALU.scala 65:30] + node _T_8 = bits(sum, 31, 31) @[ALU.scala 65:51] + node _T_9 = bits(io.alu_op, 1, 1) @[ALU.scala 66:26] + node _T_10 = bits(io.B, 31, 31) @[ALU.scala 66:35] + node _T_11 = bits(io.A, 31, 31) @[ALU.scala 66:49] + node _T_12 = mux(_T_9, _T_10, _T_11) @[ALU.scala 66:16] + node cmp = mux(_T_7, _T_8, _T_12) @[ALU.scala 65:16] + node shamt = bits(io.B, 4, 0) @[ALU.scala 67:20] + node _T_13 = bits(io.alu_op, 3, 3) @[ALU.scala 68:29] + node _T_14 = shl(UInt<16>("hffff"), 16) @[Bitwise.scala 102:47] + node _T_15 = xor(UInt<32>("hffffffff"), _T_14) @[Bitwise.scala 102:21] + node _T_16 = shr(io.A, 16) @[Bitwise.scala 103:21] + node _T_17 = and(_T_16, _T_15) @[Bitwise.scala 103:31] + node _T_18 = bits(io.A, 15, 0) @[Bitwise.scala 103:46] + node _T_19 = shl(_T_18, 16) @[Bitwise.scala 103:65] + node _T_20 = not(_T_15) @[Bitwise.scala 103:77] + node _T_21 = and(_T_19, _T_20) @[Bitwise.scala 103:75] + node _T_22 = or(_T_17, _T_21) @[Bitwise.scala 103:39] + node _T_23 = bits(_T_15, 23, 0) @[Bitwise.scala 102:28] + node _T_24 = shl(_T_23, 8) @[Bitwise.scala 102:47] + node _T_25 = xor(_T_15, _T_24) @[Bitwise.scala 102:21] + node _T_26 = shr(_T_22, 8) @[Bitwise.scala 103:21] + node _T_27 = and(_T_26, _T_25) @[Bitwise.scala 103:31] + node _T_28 = bits(_T_22, 23, 0) @[Bitwise.scala 103:46] + node _T_29 = shl(_T_28, 8) @[Bitwise.scala 103:65] + node _T_30 = not(_T_25) @[Bitwise.scala 103:77] + node _T_31 = and(_T_29, _T_30) @[Bitwise.scala 103:75] + node _T_32 = or(_T_27, _T_31) @[Bitwise.scala 103:39] + node _T_33 = bits(_T_25, 27, 0) @[Bitwise.scala 102:28] + node _T_34 = shl(_T_33, 4) @[Bitwise.scala 102:47] + node _T_35 = xor(_T_25, _T_34) @[Bitwise.scala 102:21] + node _T_36 = shr(_T_32, 4) @[Bitwise.scala 103:21] + node _T_37 = and(_T_36, _T_35) @[Bitwise.scala 103:31] + node _T_38 = bits(_T_32, 27, 0) @[Bitwise.scala 103:46] + node _T_39 = shl(_T_38, 4) @[Bitwise.scala 103:65] + node _T_40 = not(_T_35) @[Bitwise.scala 103:77] + node _T_41 = and(_T_39, _T_40) @[Bitwise.scala 103:75] + node _T_42 = or(_T_37, _T_41) @[Bitwise.scala 103:39] + node _T_43 = bits(_T_35, 29, 0) @[Bitwise.scala 102:28] + node _T_44 = shl(_T_43, 2) @[Bitwise.scala 102:47] + node _T_45 = xor(_T_35, _T_44) @[Bitwise.scala 102:21] + node _T_46 = shr(_T_42, 2) @[Bitwise.scala 103:21] + node _T_47 = and(_T_46, _T_45) @[Bitwise.scala 103:31] + node _T_48 = bits(_T_42, 29, 0) @[Bitwise.scala 103:46] + node _T_49 = shl(_T_48, 2) @[Bitwise.scala 103:65] + node _T_50 = not(_T_45) @[Bitwise.scala 103:77] + node _T_51 = and(_T_49, _T_50) @[Bitwise.scala 103:75] + node _T_52 = or(_T_47, _T_51) @[Bitwise.scala 103:39] + node _T_53 = bits(_T_45, 30, 0) @[Bitwise.scala 102:28] + node _T_54 = shl(_T_53, 1) @[Bitwise.scala 102:47] + node _T_55 = xor(_T_45, _T_54) @[Bitwise.scala 102:21] + node _T_56 = shr(_T_52, 1) @[Bitwise.scala 103:21] + node _T_57 = and(_T_56, _T_55) @[Bitwise.scala 103:31] + node _T_58 = bits(_T_52, 30, 0) @[Bitwise.scala 103:46] + node _T_59 = shl(_T_58, 1) @[Bitwise.scala 103:65] + node _T_60 = not(_T_55) @[Bitwise.scala 103:77] + node _T_61 = and(_T_59, _T_60) @[Bitwise.scala 103:75] + node _T_62 = or(_T_57, _T_61) @[Bitwise.scala 103:39] + node shin = mux(_T_13, io.A, _T_62) @[ALU.scala 68:19] + node _T_63 = bits(io.alu_op, 0, 0) @[ALU.scala 69:30] + node _T_64 = bits(shin, 31, 31) @[ALU.scala 69:41] + node _T_65 = and(_T_63, _T_64) @[ALU.scala 69:34] + node _T_66 = cat(_T_65, shin) @[Cat.scala 30:58] + node _T_67 = asSInt(_T_66) @[ALU.scala 69:57] + node _T_68 = dshr(_T_67, shamt) @[ALU.scala 69:64] + node shiftr = bits(_T_68, 31, 0) @[ALU.scala 69:73] + node _T_69 = shl(UInt<16>("hffff"), 16) @[Bitwise.scala 102:47] + node _T_70 = xor(UInt<32>("hffffffff"), _T_69) @[Bitwise.scala 102:21] + node _T_71 = shr(shiftr, 16) @[Bitwise.scala 103:21] + node _T_72 = and(_T_71, _T_70) @[Bitwise.scala 103:31] + node _T_73 = bits(shiftr, 15, 0) @[Bitwise.scala 103:46] + node _T_74 = shl(_T_73, 16) @[Bitwise.scala 103:65] + node _T_75 = not(_T_70) @[Bitwise.scala 103:77] + node _T_76 = and(_T_74, _T_75) @[Bitwise.scala 103:75] + node _T_77 = or(_T_72, _T_76) @[Bitwise.scala 103:39] + node _T_78 = bits(_T_70, 23, 0) @[Bitwise.scala 102:28] + node _T_79 = shl(_T_78, 8) @[Bitwise.scala 102:47] + node _T_80 = xor(_T_70, _T_79) @[Bitwise.scala 102:21] + node _T_81 = shr(_T_77, 8) @[Bitwise.scala 103:21] + node _T_82 = and(_T_81, _T_80) @[Bitwise.scala 103:31] + node _T_83 = bits(_T_77, 23, 0) @[Bitwise.scala 103:46] + node _T_84 = shl(_T_83, 8) @[Bitwise.scala 103:65] + node _T_85 = not(_T_80) @[Bitwise.scala 103:77] + node _T_86 = and(_T_84, _T_85) @[Bitwise.scala 103:75] + node _T_87 = or(_T_82, _T_86) @[Bitwise.scala 103:39] + node _T_88 = bits(_T_80, 27, 0) @[Bitwise.scala 102:28] + node _T_89 = shl(_T_88, 4) @[Bitwise.scala 102:47] + node _T_90 = xor(_T_80, _T_89) @[Bitwise.scala 102:21] + node _T_91 = shr(_T_87, 4) @[Bitwise.scala 103:21] + node _T_92 = and(_T_91, _T_90) @[Bitwise.scala 103:31] + node _T_93 = bits(_T_87, 27, 0) @[Bitwise.scala 103:46] + node _T_94 = shl(_T_93, 4) @[Bitwise.scala 103:65] + node _T_95 = not(_T_90) @[Bitwise.scala 103:77] + node _T_96 = and(_T_94, _T_95) @[Bitwise.scala 103:75] + node _T_97 = or(_T_92, _T_96) @[Bitwise.scala 103:39] + node _T_98 = bits(_T_90, 29, 0) @[Bitwise.scala 102:28] + node _T_99 = shl(_T_98, 2) @[Bitwise.scala 102:47] + node _T_100 = xor(_T_90, _T_99) @[Bitwise.scala 102:21] + node _T_101 = shr(_T_97, 2) @[Bitwise.scala 103:21] + node _T_102 = and(_T_101, _T_100) @[Bitwise.scala 103:31] + node _T_103 = bits(_T_97, 29, 0) @[Bitwise.scala 103:46] + node _T_104 = shl(_T_103, 2) @[Bitwise.scala 103:65] + node _T_105 = not(_T_100) @[Bitwise.scala 103:77] + node _T_106 = and(_T_104, _T_105) @[Bitwise.scala 103:75] + node _T_107 = or(_T_102, _T_106) @[Bitwise.scala 103:39] + node _T_108 = bits(_T_100, 30, 0) @[Bitwise.scala 102:28] + node _T_109 = shl(_T_108, 1) @[Bitwise.scala 102:47] + node _T_110 = xor(_T_100, _T_109) @[Bitwise.scala 102:21] + node _T_111 = shr(_T_107, 1) @[Bitwise.scala 103:21] + node _T_112 = and(_T_111, _T_110) @[Bitwise.scala 103:31] + node _T_113 = bits(_T_107, 30, 0) @[Bitwise.scala 103:46] + node _T_114 = shl(_T_113, 1) @[Bitwise.scala 103:65] + node _T_115 = not(_T_110) @[Bitwise.scala 103:77] + node _T_116 = and(_T_114, _T_115) @[Bitwise.scala 103:75] + node shiftl = or(_T_112, _T_116) @[Bitwise.scala 103:39] + node _T_117 = eq(io.alu_op, UInt<4>("h0")) @[ALU.scala 73:19] + node _T_118 = eq(io.alu_op, UInt<4>("h1")) @[ALU.scala 73:44] + node _T_119 = or(_T_117, _T_118) @[ALU.scala 73:31] + node _T_120 = eq(io.alu_op, UInt<4>("h5")) @[ALU.scala 74:19] + node _T_121 = eq(io.alu_op, UInt<4>("h7")) @[ALU.scala 74:44] + node _T_122 = or(_T_120, _T_121) @[ALU.scala 74:31] + node _T_123 = eq(io.alu_op, UInt<4>("h9")) @[ALU.scala 75:19] + node _T_124 = eq(io.alu_op, UInt<4>("h8")) @[ALU.scala 75:44] + node _T_125 = or(_T_123, _T_124) @[ALU.scala 75:31] + node _T_126 = eq(io.alu_op, UInt<4>("h6")) @[ALU.scala 76:19] + node _T_127 = eq(io.alu_op, UInt<4>("h2")) @[ALU.scala 77:19] + node _T_128 = and(io.A, io.B) @[ALU.scala 77:38] + node _T_129 = eq(io.alu_op, UInt<4>("h3")) @[ALU.scala 78:19] + node _T_130 = or(io.A, io.B) @[ALU.scala 78:38] + node _T_131 = eq(io.alu_op, UInt<4>("h4")) @[ALU.scala 79:19] + node _T_132 = xor(io.A, io.B) @[ALU.scala 79:38] + node _T_133 = eq(io.alu_op, UInt<4>("ha")) @[ALU.scala 80:19] + node _T_134 = mux(_T_133, io.A, io.B) @[ALU.scala 80:8] + node _T_135 = mux(_T_131, _T_132, _T_134) @[ALU.scala 79:8] + node _T_136 = mux(_T_129, _T_130, _T_135) @[ALU.scala 78:8] + node _T_137 = mux(_T_127, _T_128, _T_136) @[ALU.scala 77:8] + node _T_138 = mux(_T_126, shiftl, _T_137) @[ALU.scala 76:8] + node _T_139 = mux(_T_125, shiftr, _T_138) @[ALU.scala 75:8] + node _T_140 = mux(_T_122, cmp, _T_139) @[ALU.scala 74:8] + node out = mux(_T_119, sum, _T_140) @[ALU.scala 73:8] + io.out <= out @[ALU.scala 83:10] + io.sum <= sum @[ALU.scala 84:10] + + module ImmGenWire : + input clock : Clock + input reset : Reset + output io : { flip inst : UInt<32>, flip sel : UInt<3>, out : UInt<32>} + + node _T = bits(io.inst, 31, 20) @[ImmGen.scala 21:21] + node Iimm = asSInt(_T) @[ImmGen.scala 21:30] + node _T_1 = bits(io.inst, 31, 25) @[ImmGen.scala 22:25] + node _T_2 = bits(io.inst, 11, 7) @[ImmGen.scala 22:42] + node _T_3 = cat(_T_1, _T_2) @[Cat.scala 30:58] + node Simm = asSInt(_T_3) @[ImmGen.scala 22:50] + node _T_4 = bits(io.inst, 31, 31) @[ImmGen.scala 23:25] + node _T_5 = bits(io.inst, 7, 7) @[ImmGen.scala 23:38] + node _T_6 = bits(io.inst, 30, 25) @[ImmGen.scala 23:50] + node _T_7 = bits(io.inst, 11, 8) @[ImmGen.scala 23:67] + node _T_8 = cat(_T_7, UInt<1>("h0")) @[Cat.scala 30:58] + node _T_9 = cat(_T_4, _T_5) @[Cat.scala 30:58] + node _T_10 = cat(_T_9, _T_6) @[Cat.scala 30:58] + node _T_11 = cat(_T_10, _T_8) @[Cat.scala 30:58] + node Bimm = asSInt(_T_11) @[ImmGen.scala 23:86] + node _T_12 = bits(io.inst, 31, 12) @[ImmGen.scala 24:25] + node _T_13 = cat(_T_12, UInt<12>("h0")) @[Cat.scala 30:58] + node Uimm = asSInt(_T_13) @[ImmGen.scala 24:46] + node _T_14 = bits(io.inst, 31, 31) @[ImmGen.scala 25:25] + node _T_15 = bits(io.inst, 19, 12) @[ImmGen.scala 25:38] + node _T_16 = bits(io.inst, 20, 20) @[ImmGen.scala 25:55] + node _T_17 = bits(io.inst, 30, 25) @[ImmGen.scala 25:68] + node _T_18 = bits(io.inst, 24, 21) @[ImmGen.scala 25:85] + node _T_19 = cat(_T_17, _T_18) @[Cat.scala 30:58] + node _T_20 = cat(_T_19, UInt<1>("h0")) @[Cat.scala 30:58] + node _T_21 = cat(_T_14, _T_15) @[Cat.scala 30:58] + node _T_22 = cat(_T_21, _T_16) @[Cat.scala 30:58] + node _T_23 = cat(_T_22, _T_20) @[Cat.scala 30:58] + node Jimm = asSInt(_T_23) @[ImmGen.scala 25:105] + node _T_24 = bits(io.inst, 19, 15) @[ImmGen.scala 26:21] + node Zimm = cvt(_T_24) @[ImmGen.scala 26:30] + node _T_25 = and(Iimm, asSInt(UInt<2>("h2"))) @[ImmGen.scala 28:36] + node _T_26 = asSInt(_T_25) @[ImmGen.scala 28:36] + node _T_27 = eq(UInt<3>("h1"), io.sel) @[Mux.scala 80:60] + node _T_28 = mux(_T_27, Iimm, _T_26) @[Mux.scala 80:57] + node _T_29 = eq(UInt<3>("h2"), io.sel) @[Mux.scala 80:60] + node _T_30 = mux(_T_29, Simm, _T_28) @[Mux.scala 80:57] + node _T_31 = eq(UInt<3>("h5"), io.sel) @[Mux.scala 80:60] + node _T_32 = mux(_T_31, Bimm, _T_30) @[Mux.scala 80:57] + node _T_33 = eq(UInt<3>("h3"), io.sel) @[Mux.scala 80:60] + node _T_34 = mux(_T_33, Uimm, _T_32) @[Mux.scala 80:57] + node _T_35 = eq(UInt<3>("h4"), io.sel) @[Mux.scala 80:60] + node _T_36 = mux(_T_35, Jimm, _T_34) @[Mux.scala 80:57] + node _T_37 = eq(UInt<3>("h6"), io.sel) @[Mux.scala 80:60] + node _T_38 = mux(_T_37, Zimm, _T_36) @[Mux.scala 80:57] + node _T_39 = asUInt(_T_38) @[ImmGen.scala 29:100] + io.out <= _T_39 @[ImmGen.scala 28:10] + + module BrCondArea : + input clock : Clock + input reset : Reset + output io : { flip rs1 : UInt<32>, flip rs2 : UInt<32>, flip br_type : UInt<3>, taken : UInt<1>} + + node _T = sub(io.rs1, io.rs2) @[BrCond.scala 37:21] + node diff = tail(_T, 1) @[BrCond.scala 37:21] + node neq = orr(diff) @[BrCond.scala 38:19] + node eq = eq(neq, UInt<1>("h0")) @[BrCond.scala 39:14] + node _T_1 = bits(io.rs1, 31, 31) @[BrCond.scala 40:26] + node _T_2 = bits(io.rs2, 31, 31) @[BrCond.scala 40:45] + node isSameSign = eq(_T_1, _T_2) @[BrCond.scala 40:35] + node _T_3 = bits(diff, 31, 31) @[BrCond.scala 41:34] + node _T_4 = bits(io.rs1, 31, 31) @[BrCond.scala 41:50] + node lt = mux(isSameSign, _T_3, _T_4) @[BrCond.scala 41:17] + node _T_5 = bits(diff, 31, 31) @[BrCond.scala 42:34] + node _T_6 = bits(io.rs2, 31, 31) @[BrCond.scala 42:50] + node ltu = mux(isSameSign, _T_5, _T_6) @[BrCond.scala 42:17] + node ge = eq(lt, UInt<1>("h0")) @[BrCond.scala 43:14] + node geu = eq(ltu, UInt<1>("h0")) @[BrCond.scala 44:14] + node _T_7 = eq(io.br_type, UInt<3>("h3")) @[BrCond.scala 46:18] + node _T_8 = and(_T_7, eq) @[BrCond.scala 46:29] + node _T_9 = eq(io.br_type, UInt<3>("h6")) @[BrCond.scala 47:18] + node _T_10 = and(_T_9, neq) @[BrCond.scala 47:29] + node _T_11 = or(_T_8, _T_10) @[BrCond.scala 46:36] + node _T_12 = eq(io.br_type, UInt<3>("h2")) @[BrCond.scala 48:18] + node _T_13 = and(_T_12, lt) @[BrCond.scala 48:29] + node _T_14 = or(_T_11, _T_13) @[BrCond.scala 47:37] + node _T_15 = eq(io.br_type, UInt<3>("h5")) @[BrCond.scala 49:18] + node _T_16 = and(_T_15, ge) @[BrCond.scala 49:29] + node _T_17 = or(_T_14, _T_16) @[BrCond.scala 48:36] + node _T_18 = eq(io.br_type, UInt<3>("h1")) @[BrCond.scala 50:18] + node _T_19 = and(_T_18, ltu) @[BrCond.scala 50:30] + node _T_20 = or(_T_17, _T_19) @[BrCond.scala 49:36] + node _T_21 = eq(io.br_type, UInt<3>("h4")) @[BrCond.scala 51:18] + node _T_22 = and(_T_21, geu) @[BrCond.scala 51:30] + node _T_23 = or(_T_20, _T_22) @[BrCond.scala 50:38] + io.taken <= _T_23 @[BrCond.scala 45:12] + + module Datapath : + input clock : Clock + input reset : Reset + output io : { host : { flip fromhost : { valid : UInt<1>, bits : UInt<32>}, tohost : UInt<32>}, flip icache : { flip abort : UInt<1>, flip req : { valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, mask : UInt<4>}}, resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip dcache : { flip abort : UInt<1>, flip req : { valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, mask : UInt<4>}}, resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ctrl : { flip inst : UInt<32>, pc_sel : UInt<2>, inst_kill : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<3>, illegal : UInt<1>}} + + inst csr of CSR @[Datapath.scala 23:23] + csr.clock <= clock + csr.reset <= reset + inst regFile of RegFile @[Datapath.scala 24:23] + regFile.clock <= clock + regFile.reset <= reset + inst alu of ALUArea @[Config.scala 13:50] + alu.clock <= clock + alu.reset <= reset + inst immGen of ImmGenWire @[Config.scala 14:50] + immGen.clock <= clock + immGen.reset <= reset + inst brCond of BrCondArea @[Config.scala 15:50] + brCond.clock <= clock + brCond.reset <= reset + reg fe_inst : UInt<32>, clock with : + reset => (reset, UInt<32>("h13")) @[Datapath.scala 32:24] + reg fe_pc : UInt, clock with : + reset => (UInt<1>("h0"), fe_pc) @[Datapath.scala 33:20] + reg ew_inst : UInt<32>, clock with : + reset => (reset, UInt<32>("h13")) @[Datapath.scala 36:24] + reg ew_pc : UInt, clock with : + reset => (UInt<1>("h0"), ew_pc) @[Datapath.scala 37:20] + reg ew_alu : UInt, clock with : + reset => (UInt<1>("h0"), ew_alu) @[Datapath.scala 38:20] + reg csr_in : UInt, clock with : + reset => (UInt<1>("h0"), csr_in) @[Datapath.scala 39:20] + reg st_type : UInt<2>, clock with : + reset => (UInt<1>("h0"), st_type) @[Datapath.scala 42:21] + reg ld_type : UInt<3>, clock with : + reset => (UInt<1>("h0"), ld_type) @[Datapath.scala 43:21] + reg wb_sel : UInt<2>, clock with : + reset => (UInt<1>("h0"), wb_sel) @[Datapath.scala 44:21] + reg wb_en : UInt<1>, clock with : + reset => (UInt<1>("h0"), wb_en) @[Datapath.scala 45:21] + reg csr_cmd : UInt<3>, clock with : + reset => (UInt<1>("h0"), csr_cmd) @[Datapath.scala 46:21] + reg illegal : UInt<1>, clock with : + reset => (UInt<1>("h0"), illegal) @[Datapath.scala 47:21] + reg pc_check : UInt<1>, clock with : + reset => (UInt<1>("h0"), pc_check) @[Datapath.scala 48:21] + node _T = asUInt(reset) @[Datapath.scala 51:31] + reg started : UInt<1>, clock with : + reset => (UInt<1>("h0"), started) @[Datapath.scala 51:24] + started <= _T @[Datapath.scala 51:24] + node _T_1 = eq(io.icache.resp.valid, UInt<1>("h0")) @[Datapath.scala 52:15] + node _T_2 = eq(io.dcache.resp.valid, UInt<1>("h0")) @[Datapath.scala 52:40] + node stall = or(_T_1, _T_2) @[Datapath.scala 52:37] + node _T_3 = sub(UInt<32>("h200"), UInt<32>("h4")) @[Datapath.scala 53:47] + node _T_4 = tail(_T_3, 1) @[Datapath.scala 53:47] + reg pc : UInt, clock with : + reset => (reset, _T_4) @[Datapath.scala 53:21] + node _T_5 = eq(io.ctrl.pc_sel, UInt<2>("h3")) @[Datapath.scala 55:33] + node _T_6 = eq(io.ctrl.pc_sel, UInt<2>("h1")) @[Datapath.scala 56:33] + node _T_7 = or(_T_6, brCond.io.taken) @[Datapath.scala 56:44] + node _T_8 = dshr(alu.io.sum, UInt<1>("h1")) @[Datapath.scala 56:75] + node _T_9 = dshl(_T_8, UInt<1>("h1")) @[Datapath.scala 56:82] + node _T_10 = eq(io.ctrl.pc_sel, UInt<2>("h2")) @[Datapath.scala 57:33] + node _T_11 = add(pc, UInt<3>("h4")) @[Datapath.scala 57:50] + node _T_12 = tail(_T_11, 1) @[Datapath.scala 57:50] + node _T_13 = mux(_T_10, pc, _T_12) @[Datapath.scala 57:17] + node _T_14 = mux(_T_7, _T_9, _T_13) @[Datapath.scala 56:17] + node _T_15 = mux(_T_5, csr.io.epc, _T_14) @[Datapath.scala 55:17] + node _T_16 = mux(csr.io.expt, csr.io.evec, _T_15) @[Datapath.scala 54:32] + node npc = mux(stall, pc, _T_16) @[Datapath.scala 54:17] + node _T_17 = or(started, io.ctrl.inst_kill) @[Datapath.scala 58:26] + node _T_18 = or(_T_17, brCond.io.taken) @[Datapath.scala 58:47] + node _T_19 = or(_T_18, csr.io.expt) @[Datapath.scala 58:66] + node inst = mux(_T_19, UInt<32>("h13"), io.icache.resp.bits.data) @[Datapath.scala 58:17] + pc <= npc @[Datapath.scala 59:27] + io.icache.req.bits.addr <= npc @[Datapath.scala 60:27] + io.icache.req.bits.data <= UInt<1>("h0") @[Datapath.scala 61:27] + io.icache.req.bits.mask <= UInt<1>("h0") @[Datapath.scala 62:27] + node _T_20 = eq(stall, UInt<1>("h0")) @[Datapath.scala 63:30] + io.icache.req.valid <= _T_20 @[Datapath.scala 63:27] + io.icache.abort <= UInt<1>("h0") @[Datapath.scala 64:27] + node _T_21 = eq(stall, UInt<1>("h0")) @[Datapath.scala 67:9] + when _T_21 : @[Datapath.scala 67:17] + fe_pc <= pc @[Datapath.scala 68:13] + fe_inst <= inst @[Datapath.scala 69:13] + io.ctrl.inst <= fe_inst @[Datapath.scala 74:17] + node rd_addr = bits(fe_inst, 11, 7) @[Datapath.scala 77:25] + node rs1_addr = bits(fe_inst, 19, 15) @[Datapath.scala 78:25] + node rs2_addr = bits(fe_inst, 24, 20) @[Datapath.scala 79:25] + regFile.io.raddr1 <= rs1_addr @[Datapath.scala 80:21] + regFile.io.raddr2 <= rs2_addr @[Datapath.scala 81:21] + immGen.io.inst <= fe_inst @[Datapath.scala 84:18] + immGen.io.sel <= io.ctrl.imm_sel @[Datapath.scala 85:18] + node wb_rd_addr = bits(ew_inst, 11, 7) @[Datapath.scala 88:27] + node _T_22 = orr(rs1_addr) @[Datapath.scala 89:37] + node _T_23 = and(wb_en, _T_22) @[Datapath.scala 89:25] + node _T_24 = eq(rs1_addr, wb_rd_addr) @[Datapath.scala 89:54] + node rs1hazard = and(_T_23, _T_24) @[Datapath.scala 89:41] + node _T_25 = orr(rs2_addr) @[Datapath.scala 90:37] + node _T_26 = and(wb_en, _T_25) @[Datapath.scala 90:25] + node _T_27 = eq(rs2_addr, wb_rd_addr) @[Datapath.scala 90:54] + node rs2hazard = and(_T_26, _T_27) @[Datapath.scala 90:41] + node _T_28 = eq(wb_sel, UInt<2>("h0")) @[Datapath.scala 91:24] + node _T_29 = and(_T_28, rs1hazard) @[Datapath.scala 91:35] + node rs1 = mux(_T_29, ew_alu, regFile.io.rdata1) @[Datapath.scala 91:16] + node _T_30 = eq(wb_sel, UInt<2>("h0")) @[Datapath.scala 92:24] + node _T_31 = and(_T_30, rs2hazard) @[Datapath.scala 92:35] + node rs2 = mux(_T_31, ew_alu, regFile.io.rdata2) @[Datapath.scala 92:16] + node _T_32 = eq(io.ctrl.A_sel, UInt<1>("h1")) @[Datapath.scala 95:33] + node _T_33 = mux(_T_32, rs1, fe_pc) @[Datapath.scala 95:18] + alu.io.A <= _T_33 @[Datapath.scala 95:12] + node _T_34 = eq(io.ctrl.B_sel, UInt<1>("h1")) @[Datapath.scala 96:33] + node _T_35 = mux(_T_34, rs2, immGen.io.out) @[Datapath.scala 96:18] + alu.io.B <= _T_35 @[Datapath.scala 96:12] + alu.io.alu_op <= io.ctrl.alu_op @[Datapath.scala 97:17] + brCond.io.rs1 <= rs1 @[Datapath.scala 100:17] + brCond.io.rs2 <= rs2 @[Datapath.scala 101:17] + brCond.io.br_type <= io.ctrl.br_type @[Datapath.scala 102:21] + node _T_36 = mux(stall, ew_alu, alu.io.sum) @[Datapath.scala 105:20] + node _T_37 = dshr(_T_36, UInt<2>("h2")) @[Datapath.scala 105:48] + node daddr = dshl(_T_37, UInt<2>("h2")) @[Datapath.scala 105:55] + node _T_38 = bits(alu.io.sum, 1, 1) @[Datapath.scala 106:28] + node _T_39 = dshl(_T_38, UInt<3>("h4")) @[Datapath.scala 106:32] + node _T_40 = bits(alu.io.sum, 0, 0) @[Datapath.scala 106:60] + node _T_41 = dshl(_T_40, UInt<2>("h3")) @[Datapath.scala 106:64] + node woffset = or(_T_39, _T_41) @[Datapath.scala 106:47] + node _T_42 = eq(stall, UInt<1>("h0")) @[Datapath.scala 107:30] + node _T_43 = orr(io.ctrl.st_type) @[Datapath.scala 107:57] + node _T_44 = orr(io.ctrl.ld_type) @[Datapath.scala 107:80] + node _T_45 = or(_T_43, _T_44) @[Datapath.scala 107:61] + node _T_46 = and(_T_42, _T_45) @[Datapath.scala 107:37] + io.dcache.req.valid <= _T_46 @[Datapath.scala 107:27] + io.dcache.req.bits.addr <= daddr @[Datapath.scala 108:27] + node _T_47 = dshl(rs2, woffset) @[Datapath.scala 109:34] + io.dcache.req.bits.data <= _T_47 @[Datapath.scala 109:27] + node _T_48 = mux(stall, st_type, io.ctrl.st_type) @[Datapath.scala 110:43] + node _T_49 = bits(alu.io.sum, 1, 0) @[Datapath.scala 113:36] + node _T_50 = dshl(UInt<2>("h3"), _T_49) @[Datapath.scala 113:23] + node _T_51 = bits(alu.io.sum, 1, 0) @[Datapath.scala 114:36] + node _T_52 = dshl(UInt<1>("h1"), _T_51) @[Datapath.scala 114:23] + node _T_53 = eq(UInt<2>("h1"), _T_48) @[Mux.scala 80:60] + node _T_54 = mux(_T_53, UInt<4>("hf"), UInt<1>("h0")) @[Mux.scala 80:57] + node _T_55 = eq(UInt<2>("h2"), _T_48) @[Mux.scala 80:60] + node _T_56 = mux(_T_55, _T_50, _T_54) @[Mux.scala 80:57] + node _T_57 = eq(UInt<2>("h3"), _T_48) @[Mux.scala 80:60] + node _T_58 = mux(_T_57, _T_52, _T_56) @[Mux.scala 80:57] + io.dcache.req.bits.mask <= _T_58 @[Datapath.scala 110:27] + node _T_59 = asUInt(reset) @[Datapath.scala 117:14] + node _T_60 = eq(stall, UInt<1>("h0")) @[Datapath.scala 117:24] + node _T_61 = and(_T_60, csr.io.expt) @[Datapath.scala 117:31] + node _T_62 = or(_T_59, _T_61) @[Datapath.scala 117:21] + when _T_62 : @[Datapath.scala 117:47] + st_type <= UInt<1>("h0") @[Datapath.scala 118:15] + ld_type <= UInt<1>("h0") @[Datapath.scala 119:15] + wb_en <= UInt<1>("h0") @[Datapath.scala 120:15] + csr_cmd <= UInt<1>("h0") @[Datapath.scala 121:15] + illegal <= UInt<1>("h0") @[Datapath.scala 122:15] + pc_check <= UInt<1>("h0") @[Datapath.scala 123:15] + else : + node _T_63 = eq(stall, UInt<1>("h0")) @[Datapath.scala 124:14] + node _T_64 = eq(csr.io.expt, UInt<1>("h0")) @[Datapath.scala 124:24] + node _T_65 = and(_T_63, _T_64) @[Datapath.scala 124:21] + when _T_65 : @[Datapath.scala 124:38] + ew_pc <= fe_pc @[Datapath.scala 125:15] + ew_inst <= fe_inst @[Datapath.scala 126:15] + ew_alu <= alu.io.out @[Datapath.scala 127:15] + node _T_66 = eq(io.ctrl.imm_sel, UInt<3>("h6")) @[Datapath.scala 128:38] + node _T_67 = mux(_T_66, immGen.io.out, rs1) @[Datapath.scala 128:21] + csr_in <= _T_67 @[Datapath.scala 128:15] + st_type <= io.ctrl.st_type @[Datapath.scala 129:15] + ld_type <= io.ctrl.ld_type @[Datapath.scala 130:15] + wb_sel <= io.ctrl.wb_sel @[Datapath.scala 131:15] + wb_en <= io.ctrl.wb_en @[Datapath.scala 132:15] + csr_cmd <= io.ctrl.csr_cmd @[Datapath.scala 133:15] + illegal <= io.ctrl.illegal @[Datapath.scala 134:15] + node _T_68 = eq(io.ctrl.pc_sel, UInt<2>("h1")) @[Datapath.scala 135:33] + pc_check <= _T_68 @[Datapath.scala 135:15] + node _T_69 = bits(ew_alu, 1, 1) @[Datapath.scala 139:24] + node _T_70 = dshl(_T_69, UInt<3>("h4")) @[Datapath.scala 139:28] + node _T_71 = bits(ew_alu, 0, 0) @[Datapath.scala 139:52] + node _T_72 = dshl(_T_71, UInt<2>("h3")) @[Datapath.scala 139:56] + node loffset = or(_T_70, _T_72) @[Datapath.scala 139:43] + node lshift = dshr(io.dcache.resp.bits.data, loffset) @[Datapath.scala 140:42] + node _T_73 = cvt(io.dcache.resp.bits.data) @[Datapath.scala 141:61] + node _T_74 = bits(lshift, 15, 0) @[Datapath.scala 142:21] + node _T_75 = asSInt(_T_74) @[Datapath.scala 142:29] + node _T_76 = bits(lshift, 7, 0) @[Datapath.scala 142:53] + node _T_77 = asSInt(_T_76) @[Datapath.scala 142:60] + node _T_78 = bits(lshift, 15, 0) @[Datapath.scala 143:21] + node _T_79 = cvt(_T_78) @[Datapath.scala 143:29] + node _T_80 = bits(lshift, 7, 0) @[Datapath.scala 143:53] + node _T_81 = cvt(_T_80) @[Datapath.scala 143:60] + node _T_82 = eq(UInt<3>("h2"), ld_type) @[Mux.scala 80:60] + node _T_83 = mux(_T_82, _T_75, _T_73) @[Mux.scala 80:57] + node _T_84 = eq(UInt<3>("h3"), ld_type) @[Mux.scala 80:60] + node _T_85 = mux(_T_84, _T_77, _T_83) @[Mux.scala 80:57] + node _T_86 = eq(UInt<3>("h4"), ld_type) @[Mux.scala 80:60] + node _T_87 = mux(_T_86, _T_79, _T_85) @[Mux.scala 80:57] + node _T_88 = eq(UInt<3>("h5"), ld_type) @[Mux.scala 80:60] + node load = mux(_T_88, _T_81, _T_87) @[Mux.scala 80:57] + csr.io.stall <= stall @[Datapath.scala 146:19] + csr.io.in <= csr_in @[Datapath.scala 147:19] + csr.io.cmd <= csr_cmd @[Datapath.scala 148:19] + csr.io.inst <= ew_inst @[Datapath.scala 149:19] + csr.io.pc <= ew_pc @[Datapath.scala 150:19] + csr.io.addr <= ew_alu @[Datapath.scala 151:19] + csr.io.illegal <= illegal @[Datapath.scala 152:19] + csr.io.pc_check <= pc_check @[Datapath.scala 153:19] + csr.io.ld_type <= ld_type @[Datapath.scala 154:19] + csr.io.st_type <= st_type @[Datapath.scala 155:19] + io.host.tohost <= csr.io.host.tohost @[Datapath.scala 156:11] + csr.io.host.fromhost.bits <= io.host.fromhost.bits @[Datapath.scala 156:11] + csr.io.host.fromhost.valid <= io.host.fromhost.valid @[Datapath.scala 156:11] + node _T_89 = cvt(ew_alu) @[Datapath.scala 159:43] + node _T_90 = add(ew_pc, UInt<3>("h4")) @[Datapath.scala 161:22] + node _T_91 = tail(_T_90, 1) @[Datapath.scala 161:22] + node _T_92 = cvt(_T_91) @[Datapath.scala 161:29] + node _T_93 = cvt(csr.io.out) @[Datapath.scala 162:26] + node _T_94 = eq(UInt<2>("h1"), wb_sel) @[Mux.scala 80:60] + node _T_95 = mux(_T_94, load, _T_89) @[Mux.scala 80:57] + node _T_96 = eq(UInt<2>("h2"), wb_sel) @[Mux.scala 80:60] + node _T_97 = mux(_T_96, _T_92, _T_95) @[Mux.scala 80:57] + node _T_98 = eq(UInt<2>("h3"), wb_sel) @[Mux.scala 80:60] + node _T_99 = mux(_T_98, _T_93, _T_97) @[Mux.scala 80:57] + node regWrite = asUInt(_T_99) @[Datapath.scala 162:34] + node _T_100 = eq(stall, UInt<1>("h0")) @[Datapath.scala 164:32] + node _T_101 = and(wb_en, _T_100) @[Datapath.scala 164:29] + node _T_102 = eq(csr.io.expt, UInt<1>("h0")) @[Datapath.scala 164:42] + node _T_103 = and(_T_101, _T_102) @[Datapath.scala 164:39] + regFile.io.wen <= _T_103 @[Datapath.scala 164:20] + regFile.io.waddr <= wb_rd_addr @[Datapath.scala 165:20] + regFile.io.wdata <= regWrite @[Datapath.scala 166:20] + io.dcache.abort <= csr.io.expt @[Datapath.scala 169:19] + + module Control : + input clock : Clock + input reset : Reset + output io : { flip inst : UInt<32>, pc_sel : UInt<2>, inst_kill : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<3>, illegal : UInt<1>} + + node _T = and(io.inst, UInt<7>("h7f")) @[Lookup.scala 31:38] + node _T_1 = eq(UInt<6>("h37"), _T) @[Lookup.scala 31:38] + node _T_2 = and(io.inst, UInt<7>("h7f")) @[Lookup.scala 31:38] + node _T_3 = eq(UInt<5>("h17"), _T_2) @[Lookup.scala 31:38] + node _T_4 = and(io.inst, UInt<7>("h7f")) @[Lookup.scala 31:38] + node _T_5 = eq(UInt<7>("h6f"), _T_4) @[Lookup.scala 31:38] + node _T_6 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_7 = eq(UInt<7>("h67"), _T_6) @[Lookup.scala 31:38] + node _T_8 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_9 = eq(UInt<7>("h63"), _T_8) @[Lookup.scala 31:38] + node _T_10 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_11 = eq(UInt<13>("h1063"), _T_10) @[Lookup.scala 31:38] + node _T_12 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_13 = eq(UInt<15>("h4063"), _T_12) @[Lookup.scala 31:38] + node _T_14 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_15 = eq(UInt<15>("h5063"), _T_14) @[Lookup.scala 31:38] + node _T_16 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_17 = eq(UInt<15>("h6063"), _T_16) @[Lookup.scala 31:38] + node _T_18 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_19 = eq(UInt<15>("h7063"), _T_18) @[Lookup.scala 31:38] + node _T_20 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_21 = eq(UInt<2>("h3"), _T_20) @[Lookup.scala 31:38] + node _T_22 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_23 = eq(UInt<13>("h1003"), _T_22) @[Lookup.scala 31:38] + node _T_24 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_25 = eq(UInt<14>("h2003"), _T_24) @[Lookup.scala 31:38] + node _T_26 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_27 = eq(UInt<15>("h4003"), _T_26) @[Lookup.scala 31:38] + node _T_28 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_29 = eq(UInt<15>("h5003"), _T_28) @[Lookup.scala 31:38] + node _T_30 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_31 = eq(UInt<6>("h23"), _T_30) @[Lookup.scala 31:38] + node _T_32 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_33 = eq(UInt<13>("h1023"), _T_32) @[Lookup.scala 31:38] + node _T_34 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_35 = eq(UInt<14>("h2023"), _T_34) @[Lookup.scala 31:38] + node _T_36 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_37 = eq(UInt<5>("h13"), _T_36) @[Lookup.scala 31:38] + node _T_38 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_39 = eq(UInt<14>("h2013"), _T_38) @[Lookup.scala 31:38] + node _T_40 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_41 = eq(UInt<14>("h3013"), _T_40) @[Lookup.scala 31:38] + node _T_42 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_43 = eq(UInt<15>("h4013"), _T_42) @[Lookup.scala 31:38] + node _T_44 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_45 = eq(UInt<15>("h6013"), _T_44) @[Lookup.scala 31:38] + node _T_46 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_47 = eq(UInt<15>("h7013"), _T_46) @[Lookup.scala 31:38] + node _T_48 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_49 = eq(UInt<13>("h1013"), _T_48) @[Lookup.scala 31:38] + node _T_50 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_51 = eq(UInt<15>("h5013"), _T_50) @[Lookup.scala 31:38] + node _T_52 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_53 = eq(UInt<31>("h40005013"), _T_52) @[Lookup.scala 31:38] + node _T_54 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_55 = eq(UInt<6>("h33"), _T_54) @[Lookup.scala 31:38] + node _T_56 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_57 = eq(UInt<31>("h40000033"), _T_56) @[Lookup.scala 31:38] + node _T_58 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_59 = eq(UInt<13>("h1033"), _T_58) @[Lookup.scala 31:38] + node _T_60 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_61 = eq(UInt<14>("h2033"), _T_60) @[Lookup.scala 31:38] + node _T_62 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_63 = eq(UInt<14>("h3033"), _T_62) @[Lookup.scala 31:38] + node _T_64 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_65 = eq(UInt<15>("h4033"), _T_64) @[Lookup.scala 31:38] + node _T_66 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_67 = eq(UInt<15>("h5033"), _T_66) @[Lookup.scala 31:38] + node _T_68 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_69 = eq(UInt<31>("h40005033"), _T_68) @[Lookup.scala 31:38] + node _T_70 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_71 = eq(UInt<15>("h6033"), _T_70) @[Lookup.scala 31:38] + node _T_72 = and(io.inst, UInt<32>("hfe00707f")) @[Lookup.scala 31:38] + node _T_73 = eq(UInt<15>("h7033"), _T_72) @[Lookup.scala 31:38] + node _T_74 = and(io.inst, UInt<32>("hf00fffff")) @[Lookup.scala 31:38] + node _T_75 = eq(UInt<4>("hf"), _T_74) @[Lookup.scala 31:38] + node _T_76 = and(io.inst, UInt<32>("hffffffff")) @[Lookup.scala 31:38] + node _T_77 = eq(UInt<13>("h100f"), _T_76) @[Lookup.scala 31:38] + node _T_78 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_79 = eq(UInt<13>("h1073"), _T_78) @[Lookup.scala 31:38] + node _T_80 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_81 = eq(UInt<14>("h2073"), _T_80) @[Lookup.scala 31:38] + node _T_82 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_83 = eq(UInt<14>("h3073"), _T_82) @[Lookup.scala 31:38] + node _T_84 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_85 = eq(UInt<15>("h5073"), _T_84) @[Lookup.scala 31:38] + node _T_86 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_87 = eq(UInt<15>("h6073"), _T_86) @[Lookup.scala 31:38] + node _T_88 = and(io.inst, UInt<15>("h707f")) @[Lookup.scala 31:38] + node _T_89 = eq(UInt<15>("h7073"), _T_88) @[Lookup.scala 31:38] + node _T_90 = and(io.inst, UInt<32>("hffffffff")) @[Lookup.scala 31:38] + node _T_91 = eq(UInt<7>("h73"), _T_90) @[Lookup.scala 31:38] + node _T_92 = and(io.inst, UInt<32>("hffffffff")) @[Lookup.scala 31:38] + node _T_93 = eq(UInt<21>("h100073"), _T_92) @[Lookup.scala 31:38] + node _T_94 = and(io.inst, UInt<32>("hffffffff")) @[Lookup.scala 31:38] + node _T_95 = eq(UInt<29>("h10000073"), _T_94) @[Lookup.scala 31:38] + node _T_96 = and(io.inst, UInt<32>("hffffffff")) @[Lookup.scala 31:38] + node _T_97 = eq(UInt<29>("h10200073"), _T_96) @[Lookup.scala 31:38] + node _T_98 = mux(_T_97, UInt<2>("h0"), UInt<2>("h0")) @[Lookup.scala 33:37] + node _T_99 = mux(_T_95, UInt<2>("h3"), _T_98) @[Lookup.scala 33:37] + node _T_100 = mux(_T_93, UInt<2>("h0"), _T_99) @[Lookup.scala 33:37] + node _T_101 = mux(_T_91, UInt<2>("h0"), _T_100) @[Lookup.scala 33:37] + node _T_102 = mux(_T_89, UInt<2>("h2"), _T_101) @[Lookup.scala 33:37] + node _T_103 = mux(_T_87, UInt<2>("h2"), _T_102) @[Lookup.scala 33:37] + node _T_104 = mux(_T_85, UInt<2>("h2"), _T_103) @[Lookup.scala 33:37] + node _T_105 = mux(_T_83, UInt<2>("h2"), _T_104) @[Lookup.scala 33:37] + node _T_106 = mux(_T_81, UInt<2>("h2"), _T_105) @[Lookup.scala 33:37] + node _T_107 = mux(_T_79, UInt<2>("h2"), _T_106) @[Lookup.scala 33:37] + node _T_108 = mux(_T_77, UInt<2>("h2"), _T_107) @[Lookup.scala 33:37] + node _T_109 = mux(_T_75, UInt<2>("h0"), _T_108) @[Lookup.scala 33:37] + node _T_110 = mux(_T_73, UInt<2>("h0"), _T_109) @[Lookup.scala 33:37] + node _T_111 = mux(_T_71, UInt<2>("h0"), _T_110) @[Lookup.scala 33:37] + node _T_112 = mux(_T_69, UInt<2>("h0"), _T_111) @[Lookup.scala 33:37] + node _T_113 = mux(_T_67, UInt<2>("h0"), _T_112) @[Lookup.scala 33:37] + node _T_114 = mux(_T_65, UInt<2>("h0"), _T_113) @[Lookup.scala 33:37] + node _T_115 = mux(_T_63, UInt<2>("h0"), _T_114) @[Lookup.scala 33:37] + node _T_116 = mux(_T_61, UInt<2>("h0"), _T_115) @[Lookup.scala 33:37] + node _T_117 = mux(_T_59, UInt<2>("h0"), _T_116) @[Lookup.scala 33:37] + node _T_118 = mux(_T_57, UInt<2>("h0"), _T_117) @[Lookup.scala 33:37] + node _T_119 = mux(_T_55, UInt<2>("h0"), _T_118) @[Lookup.scala 33:37] + node _T_120 = mux(_T_53, UInt<2>("h0"), _T_119) @[Lookup.scala 33:37] + node _T_121 = mux(_T_51, UInt<2>("h0"), _T_120) @[Lookup.scala 33:37] + node _T_122 = mux(_T_49, UInt<2>("h0"), _T_121) @[Lookup.scala 33:37] + node _T_123 = mux(_T_47, UInt<2>("h0"), _T_122) @[Lookup.scala 33:37] + node _T_124 = mux(_T_45, UInt<2>("h0"), _T_123) @[Lookup.scala 33:37] + node _T_125 = mux(_T_43, UInt<2>("h0"), _T_124) @[Lookup.scala 33:37] + node _T_126 = mux(_T_41, UInt<2>("h0"), _T_125) @[Lookup.scala 33:37] + node _T_127 = mux(_T_39, UInt<2>("h0"), _T_126) @[Lookup.scala 33:37] + node _T_128 = mux(_T_37, UInt<2>("h0"), _T_127) @[Lookup.scala 33:37] + node _T_129 = mux(_T_35, UInt<2>("h0"), _T_128) @[Lookup.scala 33:37] + node _T_130 = mux(_T_33, UInt<2>("h0"), _T_129) @[Lookup.scala 33:37] + node _T_131 = mux(_T_31, UInt<2>("h0"), _T_130) @[Lookup.scala 33:37] + node _T_132 = mux(_T_29, UInt<2>("h2"), _T_131) @[Lookup.scala 33:37] + node _T_133 = mux(_T_27, UInt<2>("h2"), _T_132) @[Lookup.scala 33:37] + node _T_134 = mux(_T_25, UInt<2>("h2"), _T_133) @[Lookup.scala 33:37] + node _T_135 = mux(_T_23, UInt<2>("h2"), _T_134) @[Lookup.scala 33:37] + node _T_136 = mux(_T_21, UInt<2>("h2"), _T_135) @[Lookup.scala 33:37] + node _T_137 = mux(_T_19, UInt<2>("h0"), _T_136) @[Lookup.scala 33:37] + node _T_138 = mux(_T_17, UInt<2>("h0"), _T_137) @[Lookup.scala 33:37] + node _T_139 = mux(_T_15, UInt<2>("h0"), _T_138) @[Lookup.scala 33:37] + node _T_140 = mux(_T_13, UInt<2>("h0"), _T_139) @[Lookup.scala 33:37] + node _T_141 = mux(_T_11, UInt<2>("h0"), _T_140) @[Lookup.scala 33:37] + node _T_142 = mux(_T_9, UInt<2>("h0"), _T_141) @[Lookup.scala 33:37] + node _T_143 = mux(_T_7, UInt<2>("h1"), _T_142) @[Lookup.scala 33:37] + node _T_144 = mux(_T_5, UInt<2>("h1"), _T_143) @[Lookup.scala 33:37] + node _T_145 = mux(_T_3, UInt<2>("h0"), _T_144) @[Lookup.scala 33:37] + node ctrlSignals_0 = mux(_T_1, UInt<2>("h0"), _T_145) @[Lookup.scala 33:37] + node _T_146 = mux(_T_97, UInt<1>("h0"), UInt<1>("h0")) @[Lookup.scala 33:37] + node _T_147 = mux(_T_95, UInt<1>("h0"), _T_146) @[Lookup.scala 33:37] + node _T_148 = mux(_T_93, UInt<1>("h0"), _T_147) @[Lookup.scala 33:37] + node _T_149 = mux(_T_91, UInt<1>("h0"), _T_148) @[Lookup.scala 33:37] + node _T_150 = mux(_T_89, UInt<1>("h0"), _T_149) @[Lookup.scala 33:37] + node _T_151 = mux(_T_87, UInt<1>("h0"), _T_150) @[Lookup.scala 33:37] + node _T_152 = mux(_T_85, UInt<1>("h0"), _T_151) @[Lookup.scala 33:37] + node _T_153 = mux(_T_83, UInt<1>("h1"), _T_152) @[Lookup.scala 33:37] + node _T_154 = mux(_T_81, UInt<1>("h1"), _T_153) @[Lookup.scala 33:37] + node _T_155 = mux(_T_79, UInt<1>("h1"), _T_154) @[Lookup.scala 33:37] + node _T_156 = mux(_T_77, UInt<1>("h0"), _T_155) @[Lookup.scala 33:37] + node _T_157 = mux(_T_75, UInt<1>("h0"), _T_156) @[Lookup.scala 33:37] + node _T_158 = mux(_T_73, UInt<1>("h1"), _T_157) @[Lookup.scala 33:37] + node _T_159 = mux(_T_71, UInt<1>("h1"), _T_158) @[Lookup.scala 33:37] + node _T_160 = mux(_T_69, UInt<1>("h1"), _T_159) @[Lookup.scala 33:37] + node _T_161 = mux(_T_67, UInt<1>("h1"), _T_160) @[Lookup.scala 33:37] + node _T_162 = mux(_T_65, UInt<1>("h1"), _T_161) @[Lookup.scala 33:37] + node _T_163 = mux(_T_63, UInt<1>("h1"), _T_162) @[Lookup.scala 33:37] + node _T_164 = mux(_T_61, UInt<1>("h1"), _T_163) @[Lookup.scala 33:37] + node _T_165 = mux(_T_59, UInt<1>("h1"), _T_164) @[Lookup.scala 33:37] + node _T_166 = mux(_T_57, UInt<1>("h1"), _T_165) @[Lookup.scala 33:37] + node _T_167 = mux(_T_55, UInt<1>("h1"), _T_166) @[Lookup.scala 33:37] + node _T_168 = mux(_T_53, UInt<1>("h1"), _T_167) @[Lookup.scala 33:37] + node _T_169 = mux(_T_51, UInt<1>("h1"), _T_168) @[Lookup.scala 33:37] + node _T_170 = mux(_T_49, UInt<1>("h1"), _T_169) @[Lookup.scala 33:37] + node _T_171 = mux(_T_47, UInt<1>("h1"), _T_170) @[Lookup.scala 33:37] + node _T_172 = mux(_T_45, UInt<1>("h1"), _T_171) @[Lookup.scala 33:37] + node _T_173 = mux(_T_43, UInt<1>("h1"), _T_172) @[Lookup.scala 33:37] + node _T_174 = mux(_T_41, UInt<1>("h1"), _T_173) @[Lookup.scala 33:37] + node _T_175 = mux(_T_39, UInt<1>("h1"), _T_174) @[Lookup.scala 33:37] + node _T_176 = mux(_T_37, UInt<1>("h1"), _T_175) @[Lookup.scala 33:37] + node _T_177 = mux(_T_35, UInt<1>("h1"), _T_176) @[Lookup.scala 33:37] + node _T_178 = mux(_T_33, UInt<1>("h1"), _T_177) @[Lookup.scala 33:37] + node _T_179 = mux(_T_31, UInt<1>("h1"), _T_178) @[Lookup.scala 33:37] + node _T_180 = mux(_T_29, UInt<1>("h1"), _T_179) @[Lookup.scala 33:37] + node _T_181 = mux(_T_27, UInt<1>("h1"), _T_180) @[Lookup.scala 33:37] + node _T_182 = mux(_T_25, UInt<1>("h1"), _T_181) @[Lookup.scala 33:37] + node _T_183 = mux(_T_23, UInt<1>("h1"), _T_182) @[Lookup.scala 33:37] + node _T_184 = mux(_T_21, UInt<1>("h1"), _T_183) @[Lookup.scala 33:37] + node _T_185 = mux(_T_19, UInt<1>("h0"), _T_184) @[Lookup.scala 33:37] + node _T_186 = mux(_T_17, UInt<1>("h0"), _T_185) @[Lookup.scala 33:37] + node _T_187 = mux(_T_15, UInt<1>("h0"), _T_186) @[Lookup.scala 33:37] + node _T_188 = mux(_T_13, UInt<1>("h0"), _T_187) @[Lookup.scala 33:37] + node _T_189 = mux(_T_11, UInt<1>("h0"), _T_188) @[Lookup.scala 33:37] + node _T_190 = mux(_T_9, UInt<1>("h0"), _T_189) @[Lookup.scala 33:37] + node _T_191 = mux(_T_7, UInt<1>("h1"), _T_190) @[Lookup.scala 33:37] + node _T_192 = mux(_T_5, UInt<1>("h0"), _T_191) @[Lookup.scala 33:37] + node _T_193 = mux(_T_3, UInt<1>("h0"), _T_192) @[Lookup.scala 33:37] + node ctrlSignals_1 = mux(_T_1, UInt<1>("h0"), _T_193) @[Lookup.scala 33:37] + node _T_194 = mux(_T_97, UInt<1>("h0"), UInt<1>("h0")) @[Lookup.scala 33:37] + node _T_195 = mux(_T_95, UInt<1>("h0"), _T_194) @[Lookup.scala 33:37] + node _T_196 = mux(_T_93, UInt<1>("h0"), _T_195) @[Lookup.scala 33:37] + node _T_197 = mux(_T_91, UInt<1>("h0"), _T_196) @[Lookup.scala 33:37] + node _T_198 = mux(_T_89, UInt<1>("h0"), _T_197) @[Lookup.scala 33:37] + node _T_199 = mux(_T_87, UInt<1>("h0"), _T_198) @[Lookup.scala 33:37] + node _T_200 = mux(_T_85, UInt<1>("h0"), _T_199) @[Lookup.scala 33:37] + node _T_201 = mux(_T_83, UInt<1>("h0"), _T_200) @[Lookup.scala 33:37] + node _T_202 = mux(_T_81, UInt<1>("h0"), _T_201) @[Lookup.scala 33:37] + node _T_203 = mux(_T_79, UInt<1>("h0"), _T_202) @[Lookup.scala 33:37] + node _T_204 = mux(_T_77, UInt<1>("h0"), _T_203) @[Lookup.scala 33:37] + node _T_205 = mux(_T_75, UInt<1>("h0"), _T_204) @[Lookup.scala 33:37] + node _T_206 = mux(_T_73, UInt<1>("h1"), _T_205) @[Lookup.scala 33:37] + node _T_207 = mux(_T_71, UInt<1>("h1"), _T_206) @[Lookup.scala 33:37] + node _T_208 = mux(_T_69, UInt<1>("h1"), _T_207) @[Lookup.scala 33:37] + node _T_209 = mux(_T_67, UInt<1>("h1"), _T_208) @[Lookup.scala 33:37] + node _T_210 = mux(_T_65, UInt<1>("h1"), _T_209) @[Lookup.scala 33:37] + node _T_211 = mux(_T_63, UInt<1>("h1"), _T_210) @[Lookup.scala 33:37] + node _T_212 = mux(_T_61, UInt<1>("h1"), _T_211) @[Lookup.scala 33:37] + node _T_213 = mux(_T_59, UInt<1>("h1"), _T_212) @[Lookup.scala 33:37] + node _T_214 = mux(_T_57, UInt<1>("h1"), _T_213) @[Lookup.scala 33:37] + node _T_215 = mux(_T_55, UInt<1>("h1"), _T_214) @[Lookup.scala 33:37] + node _T_216 = mux(_T_53, UInt<1>("h0"), _T_215) @[Lookup.scala 33:37] + node _T_217 = mux(_T_51, UInt<1>("h0"), _T_216) @[Lookup.scala 33:37] + node _T_218 = mux(_T_49, UInt<1>("h0"), _T_217) @[Lookup.scala 33:37] + node _T_219 = mux(_T_47, UInt<1>("h0"), _T_218) @[Lookup.scala 33:37] + node _T_220 = mux(_T_45, UInt<1>("h0"), _T_219) @[Lookup.scala 33:37] + node _T_221 = mux(_T_43, UInt<1>("h0"), _T_220) @[Lookup.scala 33:37] + node _T_222 = mux(_T_41, UInt<1>("h0"), _T_221) @[Lookup.scala 33:37] + node _T_223 = mux(_T_39, UInt<1>("h0"), _T_222) @[Lookup.scala 33:37] + node _T_224 = mux(_T_37, UInt<1>("h0"), _T_223) @[Lookup.scala 33:37] + node _T_225 = mux(_T_35, UInt<1>("h0"), _T_224) @[Lookup.scala 33:37] + node _T_226 = mux(_T_33, UInt<1>("h0"), _T_225) @[Lookup.scala 33:37] + node _T_227 = mux(_T_31, UInt<1>("h0"), _T_226) @[Lookup.scala 33:37] + node _T_228 = mux(_T_29, UInt<1>("h0"), _T_227) @[Lookup.scala 33:37] + node _T_229 = mux(_T_27, UInt<1>("h0"), _T_228) @[Lookup.scala 33:37] + node _T_230 = mux(_T_25, UInt<1>("h0"), _T_229) @[Lookup.scala 33:37] + node _T_231 = mux(_T_23, UInt<1>("h0"), _T_230) @[Lookup.scala 33:37] + node _T_232 = mux(_T_21, UInt<1>("h0"), _T_231) @[Lookup.scala 33:37] + node _T_233 = mux(_T_19, UInt<1>("h0"), _T_232) @[Lookup.scala 33:37] + node _T_234 = mux(_T_17, UInt<1>("h0"), _T_233) @[Lookup.scala 33:37] + node _T_235 = mux(_T_15, UInt<1>("h0"), _T_234) @[Lookup.scala 33:37] + node _T_236 = mux(_T_13, UInt<1>("h0"), _T_235) @[Lookup.scala 33:37] + node _T_237 = mux(_T_11, UInt<1>("h0"), _T_236) @[Lookup.scala 33:37] + node _T_238 = mux(_T_9, UInt<1>("h0"), _T_237) @[Lookup.scala 33:37] + node _T_239 = mux(_T_7, UInt<1>("h0"), _T_238) @[Lookup.scala 33:37] + node _T_240 = mux(_T_5, UInt<1>("h0"), _T_239) @[Lookup.scala 33:37] + node _T_241 = mux(_T_3, UInt<1>("h0"), _T_240) @[Lookup.scala 33:37] + node ctrlSignals_2 = mux(_T_1, UInt<1>("h0"), _T_241) @[Lookup.scala 33:37] + node _T_242 = mux(_T_97, UInt<3>("h0"), UInt<3>("h0")) @[Lookup.scala 33:37] + node _T_243 = mux(_T_95, UInt<3>("h0"), _T_242) @[Lookup.scala 33:37] + node _T_244 = mux(_T_93, UInt<3>("h0"), _T_243) @[Lookup.scala 33:37] + node _T_245 = mux(_T_91, UInt<3>("h0"), _T_244) @[Lookup.scala 33:37] + node _T_246 = mux(_T_89, UInt<3>("h6"), _T_245) @[Lookup.scala 33:37] + node _T_247 = mux(_T_87, UInt<3>("h6"), _T_246) @[Lookup.scala 33:37] + node _T_248 = mux(_T_85, UInt<3>("h6"), _T_247) @[Lookup.scala 33:37] + node _T_249 = mux(_T_83, UInt<3>("h0"), _T_248) @[Lookup.scala 33:37] + node _T_250 = mux(_T_81, UInt<3>("h0"), _T_249) @[Lookup.scala 33:37] + node _T_251 = mux(_T_79, UInt<3>("h0"), _T_250) @[Lookup.scala 33:37] + node _T_252 = mux(_T_77, UInt<3>("h0"), _T_251) @[Lookup.scala 33:37] + node _T_253 = mux(_T_75, UInt<3>("h0"), _T_252) @[Lookup.scala 33:37] + node _T_254 = mux(_T_73, UInt<3>("h0"), _T_253) @[Lookup.scala 33:37] + node _T_255 = mux(_T_71, UInt<3>("h0"), _T_254) @[Lookup.scala 33:37] + node _T_256 = mux(_T_69, UInt<3>("h0"), _T_255) @[Lookup.scala 33:37] + node _T_257 = mux(_T_67, UInt<3>("h0"), _T_256) @[Lookup.scala 33:37] + node _T_258 = mux(_T_65, UInt<3>("h0"), _T_257) @[Lookup.scala 33:37] + node _T_259 = mux(_T_63, UInt<3>("h0"), _T_258) @[Lookup.scala 33:37] + node _T_260 = mux(_T_61, UInt<3>("h0"), _T_259) @[Lookup.scala 33:37] + node _T_261 = mux(_T_59, UInt<3>("h0"), _T_260) @[Lookup.scala 33:37] + node _T_262 = mux(_T_57, UInt<3>("h0"), _T_261) @[Lookup.scala 33:37] + node _T_263 = mux(_T_55, UInt<3>("h0"), _T_262) @[Lookup.scala 33:37] + node _T_264 = mux(_T_53, UInt<3>("h1"), _T_263) @[Lookup.scala 33:37] + node _T_265 = mux(_T_51, UInt<3>("h1"), _T_264) @[Lookup.scala 33:37] + node _T_266 = mux(_T_49, UInt<3>("h1"), _T_265) @[Lookup.scala 33:37] + node _T_267 = mux(_T_47, UInt<3>("h1"), _T_266) @[Lookup.scala 33:37] + node _T_268 = mux(_T_45, UInt<3>("h1"), _T_267) @[Lookup.scala 33:37] + node _T_269 = mux(_T_43, UInt<3>("h1"), _T_268) @[Lookup.scala 33:37] + node _T_270 = mux(_T_41, UInt<3>("h1"), _T_269) @[Lookup.scala 33:37] + node _T_271 = mux(_T_39, UInt<3>("h1"), _T_270) @[Lookup.scala 33:37] + node _T_272 = mux(_T_37, UInt<3>("h1"), _T_271) @[Lookup.scala 33:37] + node _T_273 = mux(_T_35, UInt<3>("h2"), _T_272) @[Lookup.scala 33:37] + node _T_274 = mux(_T_33, UInt<3>("h2"), _T_273) @[Lookup.scala 33:37] + node _T_275 = mux(_T_31, UInt<3>("h2"), _T_274) @[Lookup.scala 33:37] + node _T_276 = mux(_T_29, UInt<3>("h1"), _T_275) @[Lookup.scala 33:37] + node _T_277 = mux(_T_27, UInt<3>("h1"), _T_276) @[Lookup.scala 33:37] + node _T_278 = mux(_T_25, UInt<3>("h1"), _T_277) @[Lookup.scala 33:37] + node _T_279 = mux(_T_23, UInt<3>("h1"), _T_278) @[Lookup.scala 33:37] + node _T_280 = mux(_T_21, UInt<3>("h1"), _T_279) @[Lookup.scala 33:37] + node _T_281 = mux(_T_19, UInt<3>("h5"), _T_280) @[Lookup.scala 33:37] + node _T_282 = mux(_T_17, UInt<3>("h5"), _T_281) @[Lookup.scala 33:37] + node _T_283 = mux(_T_15, UInt<3>("h5"), _T_282) @[Lookup.scala 33:37] + node _T_284 = mux(_T_13, UInt<3>("h5"), _T_283) @[Lookup.scala 33:37] + node _T_285 = mux(_T_11, UInt<3>("h5"), _T_284) @[Lookup.scala 33:37] + node _T_286 = mux(_T_9, UInt<3>("h5"), _T_285) @[Lookup.scala 33:37] + node _T_287 = mux(_T_7, UInt<3>("h1"), _T_286) @[Lookup.scala 33:37] + node _T_288 = mux(_T_5, UInt<3>("h4"), _T_287) @[Lookup.scala 33:37] + node _T_289 = mux(_T_3, UInt<3>("h3"), _T_288) @[Lookup.scala 33:37] + node ctrlSignals_3 = mux(_T_1, UInt<3>("h3"), _T_289) @[Lookup.scala 33:37] + node _T_290 = mux(_T_97, UInt<4>("hf"), UInt<4>("hf")) @[Lookup.scala 33:37] + node _T_291 = mux(_T_95, UInt<4>("hf"), _T_290) @[Lookup.scala 33:37] + node _T_292 = mux(_T_93, UInt<4>("hf"), _T_291) @[Lookup.scala 33:37] + node _T_293 = mux(_T_91, UInt<4>("hf"), _T_292) @[Lookup.scala 33:37] + node _T_294 = mux(_T_89, UInt<4>("hf"), _T_293) @[Lookup.scala 33:37] + node _T_295 = mux(_T_87, UInt<4>("hf"), _T_294) @[Lookup.scala 33:37] + node _T_296 = mux(_T_85, UInt<4>("hf"), _T_295) @[Lookup.scala 33:37] + node _T_297 = mux(_T_83, UInt<4>("ha"), _T_296) @[Lookup.scala 33:37] + node _T_298 = mux(_T_81, UInt<4>("ha"), _T_297) @[Lookup.scala 33:37] + node _T_299 = mux(_T_79, UInt<4>("ha"), _T_298) @[Lookup.scala 33:37] + node _T_300 = mux(_T_77, UInt<4>("hf"), _T_299) @[Lookup.scala 33:37] + node _T_301 = mux(_T_75, UInt<4>("hf"), _T_300) @[Lookup.scala 33:37] + node _T_302 = mux(_T_73, UInt<4>("h2"), _T_301) @[Lookup.scala 33:37] + node _T_303 = mux(_T_71, UInt<4>("h3"), _T_302) @[Lookup.scala 33:37] + node _T_304 = mux(_T_69, UInt<4>("h9"), _T_303) @[Lookup.scala 33:37] + node _T_305 = mux(_T_67, UInt<4>("h8"), _T_304) @[Lookup.scala 33:37] + node _T_306 = mux(_T_65, UInt<4>("h4"), _T_305) @[Lookup.scala 33:37] + node _T_307 = mux(_T_63, UInt<4>("h7"), _T_306) @[Lookup.scala 33:37] + node _T_308 = mux(_T_61, UInt<4>("h5"), _T_307) @[Lookup.scala 33:37] + node _T_309 = mux(_T_59, UInt<4>("h6"), _T_308) @[Lookup.scala 33:37] + node _T_310 = mux(_T_57, UInt<4>("h1"), _T_309) @[Lookup.scala 33:37] + node _T_311 = mux(_T_55, UInt<4>("h0"), _T_310) @[Lookup.scala 33:37] + node _T_312 = mux(_T_53, UInt<4>("h9"), _T_311) @[Lookup.scala 33:37] + node _T_313 = mux(_T_51, UInt<4>("h8"), _T_312) @[Lookup.scala 33:37] + node _T_314 = mux(_T_49, UInt<4>("h6"), _T_313) @[Lookup.scala 33:37] + node _T_315 = mux(_T_47, UInt<4>("h2"), _T_314) @[Lookup.scala 33:37] + node _T_316 = mux(_T_45, UInt<4>("h3"), _T_315) @[Lookup.scala 33:37] + node _T_317 = mux(_T_43, UInt<4>("h4"), _T_316) @[Lookup.scala 33:37] + node _T_318 = mux(_T_41, UInt<4>("h7"), _T_317) @[Lookup.scala 33:37] + node _T_319 = mux(_T_39, UInt<4>("h5"), _T_318) @[Lookup.scala 33:37] + node _T_320 = mux(_T_37, UInt<4>("h0"), _T_319) @[Lookup.scala 33:37] + node _T_321 = mux(_T_35, UInt<4>("h0"), _T_320) @[Lookup.scala 33:37] + node _T_322 = mux(_T_33, UInt<4>("h0"), _T_321) @[Lookup.scala 33:37] + node _T_323 = mux(_T_31, UInt<4>("h0"), _T_322) @[Lookup.scala 33:37] + node _T_324 = mux(_T_29, UInt<4>("h0"), _T_323) @[Lookup.scala 33:37] + node _T_325 = mux(_T_27, UInt<4>("h0"), _T_324) @[Lookup.scala 33:37] + node _T_326 = mux(_T_25, UInt<4>("h0"), _T_325) @[Lookup.scala 33:37] + node _T_327 = mux(_T_23, UInt<4>("h0"), _T_326) @[Lookup.scala 33:37] + node _T_328 = mux(_T_21, UInt<4>("h0"), _T_327) @[Lookup.scala 33:37] + node _T_329 = mux(_T_19, UInt<4>("h0"), _T_328) @[Lookup.scala 33:37] + node _T_330 = mux(_T_17, UInt<4>("h0"), _T_329) @[Lookup.scala 33:37] + node _T_331 = mux(_T_15, UInt<4>("h0"), _T_330) @[Lookup.scala 33:37] + node _T_332 = mux(_T_13, UInt<4>("h0"), _T_331) @[Lookup.scala 33:37] + node _T_333 = mux(_T_11, UInt<4>("h0"), _T_332) @[Lookup.scala 33:37] + node _T_334 = mux(_T_9, UInt<4>("h0"), _T_333) @[Lookup.scala 33:37] + node _T_335 = mux(_T_7, UInt<4>("h0"), _T_334) @[Lookup.scala 33:37] + node _T_336 = mux(_T_5, UInt<4>("h0"), _T_335) @[Lookup.scala 33:37] + node _T_337 = mux(_T_3, UInt<4>("h0"), _T_336) @[Lookup.scala 33:37] + node ctrlSignals_4 = mux(_T_1, UInt<4>("hb"), _T_337) @[Lookup.scala 33:37] + node _T_338 = mux(_T_97, UInt<3>("h0"), UInt<3>("h0")) @[Lookup.scala 33:37] + node _T_339 = mux(_T_95, UInt<3>("h0"), _T_338) @[Lookup.scala 33:37] + node _T_340 = mux(_T_93, UInt<3>("h0"), _T_339) @[Lookup.scala 33:37] + node _T_341 = mux(_T_91, UInt<3>("h0"), _T_340) @[Lookup.scala 33:37] + node _T_342 = mux(_T_89, UInt<3>("h0"), _T_341) @[Lookup.scala 33:37] + node _T_343 = mux(_T_87, UInt<3>("h0"), _T_342) @[Lookup.scala 33:37] + node _T_344 = mux(_T_85, UInt<3>("h0"), _T_343) @[Lookup.scala 33:37] + node _T_345 = mux(_T_83, UInt<3>("h0"), _T_344) @[Lookup.scala 33:37] + node _T_346 = mux(_T_81, UInt<3>("h0"), _T_345) @[Lookup.scala 33:37] + node _T_347 = mux(_T_79, UInt<3>("h0"), _T_346) @[Lookup.scala 33:37] + node _T_348 = mux(_T_77, UInt<3>("h0"), _T_347) @[Lookup.scala 33:37] + node _T_349 = mux(_T_75, UInt<3>("h0"), _T_348) @[Lookup.scala 33:37] + node _T_350 = mux(_T_73, UInt<3>("h0"), _T_349) @[Lookup.scala 33:37] + node _T_351 = mux(_T_71, UInt<3>("h0"), _T_350) @[Lookup.scala 33:37] + node _T_352 = mux(_T_69, UInt<3>("h0"), _T_351) @[Lookup.scala 33:37] + node _T_353 = mux(_T_67, UInt<3>("h0"), _T_352) @[Lookup.scala 33:37] + node _T_354 = mux(_T_65, UInt<3>("h0"), _T_353) @[Lookup.scala 33:37] + node _T_355 = mux(_T_63, UInt<3>("h0"), _T_354) @[Lookup.scala 33:37] + node _T_356 = mux(_T_61, UInt<3>("h0"), _T_355) @[Lookup.scala 33:37] + node _T_357 = mux(_T_59, UInt<3>("h0"), _T_356) @[Lookup.scala 33:37] + node _T_358 = mux(_T_57, UInt<3>("h0"), _T_357) @[Lookup.scala 33:37] + node _T_359 = mux(_T_55, UInt<3>("h0"), _T_358) @[Lookup.scala 33:37] + node _T_360 = mux(_T_53, UInt<3>("h0"), _T_359) @[Lookup.scala 33:37] + node _T_361 = mux(_T_51, UInt<3>("h0"), _T_360) @[Lookup.scala 33:37] + node _T_362 = mux(_T_49, UInt<3>("h0"), _T_361) @[Lookup.scala 33:37] + node _T_363 = mux(_T_47, UInt<3>("h0"), _T_362) @[Lookup.scala 33:37] + node _T_364 = mux(_T_45, UInt<3>("h0"), _T_363) @[Lookup.scala 33:37] + node _T_365 = mux(_T_43, UInt<3>("h0"), _T_364) @[Lookup.scala 33:37] + node _T_366 = mux(_T_41, UInt<3>("h0"), _T_365) @[Lookup.scala 33:37] + node _T_367 = mux(_T_39, UInt<3>("h0"), _T_366) @[Lookup.scala 33:37] + node _T_368 = mux(_T_37, UInt<3>("h0"), _T_367) @[Lookup.scala 33:37] + node _T_369 = mux(_T_35, UInt<3>("h0"), _T_368) @[Lookup.scala 33:37] + node _T_370 = mux(_T_33, UInt<3>("h0"), _T_369) @[Lookup.scala 33:37] + node _T_371 = mux(_T_31, UInt<3>("h0"), _T_370) @[Lookup.scala 33:37] + node _T_372 = mux(_T_29, UInt<3>("h0"), _T_371) @[Lookup.scala 33:37] + node _T_373 = mux(_T_27, UInt<3>("h0"), _T_372) @[Lookup.scala 33:37] + node _T_374 = mux(_T_25, UInt<3>("h0"), _T_373) @[Lookup.scala 33:37] + node _T_375 = mux(_T_23, UInt<3>("h0"), _T_374) @[Lookup.scala 33:37] + node _T_376 = mux(_T_21, UInt<3>("h0"), _T_375) @[Lookup.scala 33:37] + node _T_377 = mux(_T_19, UInt<3>("h4"), _T_376) @[Lookup.scala 33:37] + node _T_378 = mux(_T_17, UInt<3>("h1"), _T_377) @[Lookup.scala 33:37] + node _T_379 = mux(_T_15, UInt<3>("h5"), _T_378) @[Lookup.scala 33:37] + node _T_380 = mux(_T_13, UInt<3>("h2"), _T_379) @[Lookup.scala 33:37] + node _T_381 = mux(_T_11, UInt<3>("h6"), _T_380) @[Lookup.scala 33:37] + node _T_382 = mux(_T_9, UInt<3>("h3"), _T_381) @[Lookup.scala 33:37] + node _T_383 = mux(_T_7, UInt<3>("h0"), _T_382) @[Lookup.scala 33:37] + node _T_384 = mux(_T_5, UInt<3>("h0"), _T_383) @[Lookup.scala 33:37] + node _T_385 = mux(_T_3, UInt<3>("h0"), _T_384) @[Lookup.scala 33:37] + node ctrlSignals_5 = mux(_T_1, UInt<3>("h0"), _T_385) @[Lookup.scala 33:37] + node _T_386 = mux(_T_97, UInt<1>("h0"), UInt<1>("h0")) @[Lookup.scala 33:37] + node _T_387 = mux(_T_95, UInt<1>("h1"), _T_386) @[Lookup.scala 33:37] + node _T_388 = mux(_T_93, UInt<1>("h0"), _T_387) @[Lookup.scala 33:37] + node _T_389 = mux(_T_91, UInt<1>("h0"), _T_388) @[Lookup.scala 33:37] + node _T_390 = mux(_T_89, UInt<1>("h1"), _T_389) @[Lookup.scala 33:37] + node _T_391 = mux(_T_87, UInt<1>("h1"), _T_390) @[Lookup.scala 33:37] + node _T_392 = mux(_T_85, UInt<1>("h1"), _T_391) @[Lookup.scala 33:37] + node _T_393 = mux(_T_83, UInt<1>("h1"), _T_392) @[Lookup.scala 33:37] + node _T_394 = mux(_T_81, UInt<1>("h1"), _T_393) @[Lookup.scala 33:37] + node _T_395 = mux(_T_79, UInt<1>("h1"), _T_394) @[Lookup.scala 33:37] + node _T_396 = mux(_T_77, UInt<1>("h1"), _T_395) @[Lookup.scala 33:37] + node _T_397 = mux(_T_75, UInt<1>("h0"), _T_396) @[Lookup.scala 33:37] + node _T_398 = mux(_T_73, UInt<1>("h0"), _T_397) @[Lookup.scala 33:37] + node _T_399 = mux(_T_71, UInt<1>("h0"), _T_398) @[Lookup.scala 33:37] + node _T_400 = mux(_T_69, UInt<1>("h0"), _T_399) @[Lookup.scala 33:37] + node _T_401 = mux(_T_67, UInt<1>("h0"), _T_400) @[Lookup.scala 33:37] + node _T_402 = mux(_T_65, UInt<1>("h0"), _T_401) @[Lookup.scala 33:37] + node _T_403 = mux(_T_63, UInt<1>("h0"), _T_402) @[Lookup.scala 33:37] + node _T_404 = mux(_T_61, UInt<1>("h0"), _T_403) @[Lookup.scala 33:37] + node _T_405 = mux(_T_59, UInt<1>("h0"), _T_404) @[Lookup.scala 33:37] + node _T_406 = mux(_T_57, UInt<1>("h0"), _T_405) @[Lookup.scala 33:37] + node _T_407 = mux(_T_55, UInt<1>("h0"), _T_406) @[Lookup.scala 33:37] + node _T_408 = mux(_T_53, UInt<1>("h0"), _T_407) @[Lookup.scala 33:37] + node _T_409 = mux(_T_51, UInt<1>("h0"), _T_408) @[Lookup.scala 33:37] + node _T_410 = mux(_T_49, UInt<1>("h0"), _T_409) @[Lookup.scala 33:37] + node _T_411 = mux(_T_47, UInt<1>("h0"), _T_410) @[Lookup.scala 33:37] + node _T_412 = mux(_T_45, UInt<1>("h0"), _T_411) @[Lookup.scala 33:37] + node _T_413 = mux(_T_43, UInt<1>("h0"), _T_412) @[Lookup.scala 33:37] + node _T_414 = mux(_T_41, UInt<1>("h0"), _T_413) @[Lookup.scala 33:37] + node _T_415 = mux(_T_39, UInt<1>("h0"), _T_414) @[Lookup.scala 33:37] + node _T_416 = mux(_T_37, UInt<1>("h0"), _T_415) @[Lookup.scala 33:37] + node _T_417 = mux(_T_35, UInt<1>("h0"), _T_416) @[Lookup.scala 33:37] + node _T_418 = mux(_T_33, UInt<1>("h0"), _T_417) @[Lookup.scala 33:37] + node _T_419 = mux(_T_31, UInt<1>("h0"), _T_418) @[Lookup.scala 33:37] + node _T_420 = mux(_T_29, UInt<1>("h1"), _T_419) @[Lookup.scala 33:37] + node _T_421 = mux(_T_27, UInt<1>("h1"), _T_420) @[Lookup.scala 33:37] + node _T_422 = mux(_T_25, UInt<1>("h1"), _T_421) @[Lookup.scala 33:37] + node _T_423 = mux(_T_23, UInt<1>("h1"), _T_422) @[Lookup.scala 33:37] + node _T_424 = mux(_T_21, UInt<1>("h1"), _T_423) @[Lookup.scala 33:37] + node _T_425 = mux(_T_19, UInt<1>("h0"), _T_424) @[Lookup.scala 33:37] + node _T_426 = mux(_T_17, UInt<1>("h0"), _T_425) @[Lookup.scala 33:37] + node _T_427 = mux(_T_15, UInt<1>("h0"), _T_426) @[Lookup.scala 33:37] + node _T_428 = mux(_T_13, UInt<1>("h0"), _T_427) @[Lookup.scala 33:37] + node _T_429 = mux(_T_11, UInt<1>("h0"), _T_428) @[Lookup.scala 33:37] + node _T_430 = mux(_T_9, UInt<1>("h0"), _T_429) @[Lookup.scala 33:37] + node _T_431 = mux(_T_7, UInt<1>("h1"), _T_430) @[Lookup.scala 33:37] + node _T_432 = mux(_T_5, UInt<1>("h1"), _T_431) @[Lookup.scala 33:37] + node _T_433 = mux(_T_3, UInt<1>("h0"), _T_432) @[Lookup.scala 33:37] + node ctrlSignals_6 = mux(_T_1, UInt<1>("h0"), _T_433) @[Lookup.scala 33:37] + node _T_434 = mux(_T_97, UInt<2>("h0"), UInt<2>("h0")) @[Lookup.scala 33:37] + node _T_435 = mux(_T_95, UInt<2>("h0"), _T_434) @[Lookup.scala 33:37] + node _T_436 = mux(_T_93, UInt<2>("h0"), _T_435) @[Lookup.scala 33:37] + node _T_437 = mux(_T_91, UInt<2>("h0"), _T_436) @[Lookup.scala 33:37] + node _T_438 = mux(_T_89, UInt<2>("h0"), _T_437) @[Lookup.scala 33:37] + node _T_439 = mux(_T_87, UInt<2>("h0"), _T_438) @[Lookup.scala 33:37] + node _T_440 = mux(_T_85, UInt<2>("h0"), _T_439) @[Lookup.scala 33:37] + node _T_441 = mux(_T_83, UInt<2>("h0"), _T_440) @[Lookup.scala 33:37] + node _T_442 = mux(_T_81, UInt<2>("h0"), _T_441) @[Lookup.scala 33:37] + node _T_443 = mux(_T_79, UInt<2>("h0"), _T_442) @[Lookup.scala 33:37] + node _T_444 = mux(_T_77, UInt<2>("h0"), _T_443) @[Lookup.scala 33:37] + node _T_445 = mux(_T_75, UInt<2>("h0"), _T_444) @[Lookup.scala 33:37] + node _T_446 = mux(_T_73, UInt<2>("h0"), _T_445) @[Lookup.scala 33:37] + node _T_447 = mux(_T_71, UInt<2>("h0"), _T_446) @[Lookup.scala 33:37] + node _T_448 = mux(_T_69, UInt<2>("h0"), _T_447) @[Lookup.scala 33:37] + node _T_449 = mux(_T_67, UInt<2>("h0"), _T_448) @[Lookup.scala 33:37] + node _T_450 = mux(_T_65, UInt<2>("h0"), _T_449) @[Lookup.scala 33:37] + node _T_451 = mux(_T_63, UInt<2>("h0"), _T_450) @[Lookup.scala 33:37] + node _T_452 = mux(_T_61, UInt<2>("h0"), _T_451) @[Lookup.scala 33:37] + node _T_453 = mux(_T_59, UInt<2>("h0"), _T_452) @[Lookup.scala 33:37] + node _T_454 = mux(_T_57, UInt<2>("h0"), _T_453) @[Lookup.scala 33:37] + node _T_455 = mux(_T_55, UInt<2>("h0"), _T_454) @[Lookup.scala 33:37] + node _T_456 = mux(_T_53, UInt<2>("h0"), _T_455) @[Lookup.scala 33:37] + node _T_457 = mux(_T_51, UInt<2>("h0"), _T_456) @[Lookup.scala 33:37] + node _T_458 = mux(_T_49, UInt<2>("h0"), _T_457) @[Lookup.scala 33:37] + node _T_459 = mux(_T_47, UInt<2>("h0"), _T_458) @[Lookup.scala 33:37] + node _T_460 = mux(_T_45, UInt<2>("h0"), _T_459) @[Lookup.scala 33:37] + node _T_461 = mux(_T_43, UInt<2>("h0"), _T_460) @[Lookup.scala 33:37] + node _T_462 = mux(_T_41, UInt<2>("h0"), _T_461) @[Lookup.scala 33:37] + node _T_463 = mux(_T_39, UInt<2>("h0"), _T_462) @[Lookup.scala 33:37] + node _T_464 = mux(_T_37, UInt<2>("h0"), _T_463) @[Lookup.scala 33:37] + node _T_465 = mux(_T_35, UInt<2>("h1"), _T_464) @[Lookup.scala 33:37] + node _T_466 = mux(_T_33, UInt<2>("h2"), _T_465) @[Lookup.scala 33:37] + node _T_467 = mux(_T_31, UInt<2>("h3"), _T_466) @[Lookup.scala 33:37] + node _T_468 = mux(_T_29, UInt<2>("h0"), _T_467) @[Lookup.scala 33:37] + node _T_469 = mux(_T_27, UInt<2>("h0"), _T_468) @[Lookup.scala 33:37] + node _T_470 = mux(_T_25, UInt<2>("h0"), _T_469) @[Lookup.scala 33:37] + node _T_471 = mux(_T_23, UInt<2>("h0"), _T_470) @[Lookup.scala 33:37] + node _T_472 = mux(_T_21, UInt<2>("h0"), _T_471) @[Lookup.scala 33:37] + node _T_473 = mux(_T_19, UInt<2>("h0"), _T_472) @[Lookup.scala 33:37] + node _T_474 = mux(_T_17, UInt<2>("h0"), _T_473) @[Lookup.scala 33:37] + node _T_475 = mux(_T_15, UInt<2>("h0"), _T_474) @[Lookup.scala 33:37] + node _T_476 = mux(_T_13, UInt<2>("h0"), _T_475) @[Lookup.scala 33:37] + node _T_477 = mux(_T_11, UInt<2>("h0"), _T_476) @[Lookup.scala 33:37] + node _T_478 = mux(_T_9, UInt<2>("h0"), _T_477) @[Lookup.scala 33:37] + node _T_479 = mux(_T_7, UInt<2>("h0"), _T_478) @[Lookup.scala 33:37] + node _T_480 = mux(_T_5, UInt<2>("h0"), _T_479) @[Lookup.scala 33:37] + node _T_481 = mux(_T_3, UInt<2>("h0"), _T_480) @[Lookup.scala 33:37] + node ctrlSignals_7 = mux(_T_1, UInt<2>("h0"), _T_481) @[Lookup.scala 33:37] + node _T_482 = mux(_T_97, UInt<3>("h0"), UInt<3>("h0")) @[Lookup.scala 33:37] + node _T_483 = mux(_T_95, UInt<3>("h0"), _T_482) @[Lookup.scala 33:37] + node _T_484 = mux(_T_93, UInt<3>("h0"), _T_483) @[Lookup.scala 33:37] + node _T_485 = mux(_T_91, UInt<3>("h0"), _T_484) @[Lookup.scala 33:37] + node _T_486 = mux(_T_89, UInt<3>("h0"), _T_485) @[Lookup.scala 33:37] + node _T_487 = mux(_T_87, UInt<3>("h0"), _T_486) @[Lookup.scala 33:37] + node _T_488 = mux(_T_85, UInt<3>("h0"), _T_487) @[Lookup.scala 33:37] + node _T_489 = mux(_T_83, UInt<3>("h0"), _T_488) @[Lookup.scala 33:37] + node _T_490 = mux(_T_81, UInt<3>("h0"), _T_489) @[Lookup.scala 33:37] + node _T_491 = mux(_T_79, UInt<3>("h0"), _T_490) @[Lookup.scala 33:37] + node _T_492 = mux(_T_77, UInt<3>("h0"), _T_491) @[Lookup.scala 33:37] + node _T_493 = mux(_T_75, UInt<3>("h0"), _T_492) @[Lookup.scala 33:37] + node _T_494 = mux(_T_73, UInt<3>("h0"), _T_493) @[Lookup.scala 33:37] + node _T_495 = mux(_T_71, UInt<3>("h0"), _T_494) @[Lookup.scala 33:37] + node _T_496 = mux(_T_69, UInt<3>("h0"), _T_495) @[Lookup.scala 33:37] + node _T_497 = mux(_T_67, UInt<3>("h0"), _T_496) @[Lookup.scala 33:37] + node _T_498 = mux(_T_65, UInt<3>("h0"), _T_497) @[Lookup.scala 33:37] + node _T_499 = mux(_T_63, UInt<3>("h0"), _T_498) @[Lookup.scala 33:37] + node _T_500 = mux(_T_61, UInt<3>("h0"), _T_499) @[Lookup.scala 33:37] + node _T_501 = mux(_T_59, UInt<3>("h0"), _T_500) @[Lookup.scala 33:37] + node _T_502 = mux(_T_57, UInt<3>("h0"), _T_501) @[Lookup.scala 33:37] + node _T_503 = mux(_T_55, UInt<3>("h0"), _T_502) @[Lookup.scala 33:37] + node _T_504 = mux(_T_53, UInt<3>("h0"), _T_503) @[Lookup.scala 33:37] + node _T_505 = mux(_T_51, UInt<3>("h0"), _T_504) @[Lookup.scala 33:37] + node _T_506 = mux(_T_49, UInt<3>("h0"), _T_505) @[Lookup.scala 33:37] + node _T_507 = mux(_T_47, UInt<3>("h0"), _T_506) @[Lookup.scala 33:37] + node _T_508 = mux(_T_45, UInt<3>("h0"), _T_507) @[Lookup.scala 33:37] + node _T_509 = mux(_T_43, UInt<3>("h0"), _T_508) @[Lookup.scala 33:37] + node _T_510 = mux(_T_41, UInt<3>("h0"), _T_509) @[Lookup.scala 33:37] + node _T_511 = mux(_T_39, UInt<3>("h0"), _T_510) @[Lookup.scala 33:37] + node _T_512 = mux(_T_37, UInt<3>("h0"), _T_511) @[Lookup.scala 33:37] + node _T_513 = mux(_T_35, UInt<3>("h0"), _T_512) @[Lookup.scala 33:37] + node _T_514 = mux(_T_33, UInt<3>("h0"), _T_513) @[Lookup.scala 33:37] + node _T_515 = mux(_T_31, UInt<3>("h0"), _T_514) @[Lookup.scala 33:37] + node _T_516 = mux(_T_29, UInt<3>("h4"), _T_515) @[Lookup.scala 33:37] + node _T_517 = mux(_T_27, UInt<3>("h5"), _T_516) @[Lookup.scala 33:37] + node _T_518 = mux(_T_25, UInt<3>("h1"), _T_517) @[Lookup.scala 33:37] + node _T_519 = mux(_T_23, UInt<3>("h2"), _T_518) @[Lookup.scala 33:37] + node _T_520 = mux(_T_21, UInt<3>("h3"), _T_519) @[Lookup.scala 33:37] + node _T_521 = mux(_T_19, UInt<3>("h0"), _T_520) @[Lookup.scala 33:37] + node _T_522 = mux(_T_17, UInt<3>("h0"), _T_521) @[Lookup.scala 33:37] + node _T_523 = mux(_T_15, UInt<3>("h0"), _T_522) @[Lookup.scala 33:37] + node _T_524 = mux(_T_13, UInt<3>("h0"), _T_523) @[Lookup.scala 33:37] + node _T_525 = mux(_T_11, UInt<3>("h0"), _T_524) @[Lookup.scala 33:37] + node _T_526 = mux(_T_9, UInt<3>("h0"), _T_525) @[Lookup.scala 33:37] + node _T_527 = mux(_T_7, UInt<3>("h0"), _T_526) @[Lookup.scala 33:37] + node _T_528 = mux(_T_5, UInt<3>("h0"), _T_527) @[Lookup.scala 33:37] + node _T_529 = mux(_T_3, UInt<3>("h0"), _T_528) @[Lookup.scala 33:37] + node ctrlSignals_8 = mux(_T_1, UInt<3>("h0"), _T_529) @[Lookup.scala 33:37] + node _T_530 = mux(_T_97, UInt<2>("h0"), UInt<2>("h0")) @[Lookup.scala 33:37] + node _T_531 = mux(_T_95, UInt<2>("h3"), _T_530) @[Lookup.scala 33:37] + node _T_532 = mux(_T_93, UInt<2>("h3"), _T_531) @[Lookup.scala 33:37] + node _T_533 = mux(_T_91, UInt<2>("h3"), _T_532) @[Lookup.scala 33:37] + node _T_534 = mux(_T_89, UInt<2>("h3"), _T_533) @[Lookup.scala 33:37] + node _T_535 = mux(_T_87, UInt<2>("h3"), _T_534) @[Lookup.scala 33:37] + node _T_536 = mux(_T_85, UInt<2>("h3"), _T_535) @[Lookup.scala 33:37] + node _T_537 = mux(_T_83, UInt<2>("h3"), _T_536) @[Lookup.scala 33:37] + node _T_538 = mux(_T_81, UInt<2>("h3"), _T_537) @[Lookup.scala 33:37] + node _T_539 = mux(_T_79, UInt<2>("h3"), _T_538) @[Lookup.scala 33:37] + node _T_540 = mux(_T_77, UInt<2>("h0"), _T_539) @[Lookup.scala 33:37] + node _T_541 = mux(_T_75, UInt<2>("h0"), _T_540) @[Lookup.scala 33:37] + node _T_542 = mux(_T_73, UInt<2>("h0"), _T_541) @[Lookup.scala 33:37] + node _T_543 = mux(_T_71, UInt<2>("h0"), _T_542) @[Lookup.scala 33:37] + node _T_544 = mux(_T_69, UInt<2>("h0"), _T_543) @[Lookup.scala 33:37] + node _T_545 = mux(_T_67, UInt<2>("h0"), _T_544) @[Lookup.scala 33:37] + node _T_546 = mux(_T_65, UInt<2>("h0"), _T_545) @[Lookup.scala 33:37] + node _T_547 = mux(_T_63, UInt<2>("h0"), _T_546) @[Lookup.scala 33:37] + node _T_548 = mux(_T_61, UInt<2>("h0"), _T_547) @[Lookup.scala 33:37] + node _T_549 = mux(_T_59, UInt<2>("h0"), _T_548) @[Lookup.scala 33:37] + node _T_550 = mux(_T_57, UInt<2>("h0"), _T_549) @[Lookup.scala 33:37] + node _T_551 = mux(_T_55, UInt<2>("h0"), _T_550) @[Lookup.scala 33:37] + node _T_552 = mux(_T_53, UInt<2>("h0"), _T_551) @[Lookup.scala 33:37] + node _T_553 = mux(_T_51, UInt<2>("h0"), _T_552) @[Lookup.scala 33:37] + node _T_554 = mux(_T_49, UInt<2>("h0"), _T_553) @[Lookup.scala 33:37] + node _T_555 = mux(_T_47, UInt<2>("h0"), _T_554) @[Lookup.scala 33:37] + node _T_556 = mux(_T_45, UInt<2>("h0"), _T_555) @[Lookup.scala 33:37] + node _T_557 = mux(_T_43, UInt<2>("h0"), _T_556) @[Lookup.scala 33:37] + node _T_558 = mux(_T_41, UInt<2>("h0"), _T_557) @[Lookup.scala 33:37] + node _T_559 = mux(_T_39, UInt<2>("h0"), _T_558) @[Lookup.scala 33:37] + node _T_560 = mux(_T_37, UInt<2>("h0"), _T_559) @[Lookup.scala 33:37] + node _T_561 = mux(_T_35, UInt<2>("h0"), _T_560) @[Lookup.scala 33:37] + node _T_562 = mux(_T_33, UInt<2>("h0"), _T_561) @[Lookup.scala 33:37] + node _T_563 = mux(_T_31, UInt<2>("h0"), _T_562) @[Lookup.scala 33:37] + node _T_564 = mux(_T_29, UInt<2>("h1"), _T_563) @[Lookup.scala 33:37] + node _T_565 = mux(_T_27, UInt<2>("h1"), _T_564) @[Lookup.scala 33:37] + node _T_566 = mux(_T_25, UInt<2>("h1"), _T_565) @[Lookup.scala 33:37] + node _T_567 = mux(_T_23, UInt<2>("h1"), _T_566) @[Lookup.scala 33:37] + node _T_568 = mux(_T_21, UInt<2>("h1"), _T_567) @[Lookup.scala 33:37] + node _T_569 = mux(_T_19, UInt<2>("h0"), _T_568) @[Lookup.scala 33:37] + node _T_570 = mux(_T_17, UInt<2>("h0"), _T_569) @[Lookup.scala 33:37] + node _T_571 = mux(_T_15, UInt<2>("h0"), _T_570) @[Lookup.scala 33:37] + node _T_572 = mux(_T_13, UInt<2>("h0"), _T_571) @[Lookup.scala 33:37] + node _T_573 = mux(_T_11, UInt<2>("h0"), _T_572) @[Lookup.scala 33:37] + node _T_574 = mux(_T_9, UInt<2>("h0"), _T_573) @[Lookup.scala 33:37] + node _T_575 = mux(_T_7, UInt<2>("h2"), _T_574) @[Lookup.scala 33:37] + node _T_576 = mux(_T_5, UInt<2>("h2"), _T_575) @[Lookup.scala 33:37] + node _T_577 = mux(_T_3, UInt<2>("h0"), _T_576) @[Lookup.scala 33:37] + node ctrlSignals_9 = mux(_T_1, UInt<2>("h0"), _T_577) @[Lookup.scala 33:37] + node _T_578 = mux(_T_97, UInt<1>("h0"), UInt<1>("h0")) @[Lookup.scala 33:37] + node _T_579 = mux(_T_95, UInt<1>("h0"), _T_578) @[Lookup.scala 33:37] + node _T_580 = mux(_T_93, UInt<1>("h0"), _T_579) @[Lookup.scala 33:37] + node _T_581 = mux(_T_91, UInt<1>("h0"), _T_580) @[Lookup.scala 33:37] + node _T_582 = mux(_T_89, UInt<1>("h1"), _T_581) @[Lookup.scala 33:37] + node _T_583 = mux(_T_87, UInt<1>("h1"), _T_582) @[Lookup.scala 33:37] + node _T_584 = mux(_T_85, UInt<1>("h1"), _T_583) @[Lookup.scala 33:37] + node _T_585 = mux(_T_83, UInt<1>("h1"), _T_584) @[Lookup.scala 33:37] + node _T_586 = mux(_T_81, UInt<1>("h1"), _T_585) @[Lookup.scala 33:37] + node _T_587 = mux(_T_79, UInt<1>("h1"), _T_586) @[Lookup.scala 33:37] + node _T_588 = mux(_T_77, UInt<1>("h0"), _T_587) @[Lookup.scala 33:37] + node _T_589 = mux(_T_75, UInt<1>("h0"), _T_588) @[Lookup.scala 33:37] + node _T_590 = mux(_T_73, UInt<1>("h1"), _T_589) @[Lookup.scala 33:37] + node _T_591 = mux(_T_71, UInt<1>("h1"), _T_590) @[Lookup.scala 33:37] + node _T_592 = mux(_T_69, UInt<1>("h1"), _T_591) @[Lookup.scala 33:37] + node _T_593 = mux(_T_67, UInt<1>("h1"), _T_592) @[Lookup.scala 33:37] + node _T_594 = mux(_T_65, UInt<1>("h1"), _T_593) @[Lookup.scala 33:37] + node _T_595 = mux(_T_63, UInt<1>("h1"), _T_594) @[Lookup.scala 33:37] + node _T_596 = mux(_T_61, UInt<1>("h1"), _T_595) @[Lookup.scala 33:37] + node _T_597 = mux(_T_59, UInt<1>("h1"), _T_596) @[Lookup.scala 33:37] + node _T_598 = mux(_T_57, UInt<1>("h1"), _T_597) @[Lookup.scala 33:37] + node _T_599 = mux(_T_55, UInt<1>("h1"), _T_598) @[Lookup.scala 33:37] + node _T_600 = mux(_T_53, UInt<1>("h1"), _T_599) @[Lookup.scala 33:37] + node _T_601 = mux(_T_51, UInt<1>("h1"), _T_600) @[Lookup.scala 33:37] + node _T_602 = mux(_T_49, UInt<1>("h1"), _T_601) @[Lookup.scala 33:37] + node _T_603 = mux(_T_47, UInt<1>("h1"), _T_602) @[Lookup.scala 33:37] + node _T_604 = mux(_T_45, UInt<1>("h1"), _T_603) @[Lookup.scala 33:37] + node _T_605 = mux(_T_43, UInt<1>("h1"), _T_604) @[Lookup.scala 33:37] + node _T_606 = mux(_T_41, UInt<1>("h1"), _T_605) @[Lookup.scala 33:37] + node _T_607 = mux(_T_39, UInt<1>("h1"), _T_606) @[Lookup.scala 33:37] + node _T_608 = mux(_T_37, UInt<1>("h1"), _T_607) @[Lookup.scala 33:37] + node _T_609 = mux(_T_35, UInt<1>("h0"), _T_608) @[Lookup.scala 33:37] + node _T_610 = mux(_T_33, UInt<1>("h0"), _T_609) @[Lookup.scala 33:37] + node _T_611 = mux(_T_31, UInt<1>("h0"), _T_610) @[Lookup.scala 33:37] + node _T_612 = mux(_T_29, UInt<1>("h1"), _T_611) @[Lookup.scala 33:37] + node _T_613 = mux(_T_27, UInt<1>("h1"), _T_612) @[Lookup.scala 33:37] + node _T_614 = mux(_T_25, UInt<1>("h1"), _T_613) @[Lookup.scala 33:37] + node _T_615 = mux(_T_23, UInt<1>("h1"), _T_614) @[Lookup.scala 33:37] + node _T_616 = mux(_T_21, UInt<1>("h1"), _T_615) @[Lookup.scala 33:37] + node _T_617 = mux(_T_19, UInt<1>("h0"), _T_616) @[Lookup.scala 33:37] + node _T_618 = mux(_T_17, UInt<1>("h0"), _T_617) @[Lookup.scala 33:37] + node _T_619 = mux(_T_15, UInt<1>("h0"), _T_618) @[Lookup.scala 33:37] + node _T_620 = mux(_T_13, UInt<1>("h0"), _T_619) @[Lookup.scala 33:37] + node _T_621 = mux(_T_11, UInt<1>("h0"), _T_620) @[Lookup.scala 33:37] + node _T_622 = mux(_T_9, UInt<1>("h0"), _T_621) @[Lookup.scala 33:37] + node _T_623 = mux(_T_7, UInt<1>("h1"), _T_622) @[Lookup.scala 33:37] + node _T_624 = mux(_T_5, UInt<1>("h1"), _T_623) @[Lookup.scala 33:37] + node _T_625 = mux(_T_3, UInt<1>("h1"), _T_624) @[Lookup.scala 33:37] + node ctrlSignals_10 = mux(_T_1, UInt<1>("h1"), _T_625) @[Lookup.scala 33:37] + node _T_626 = mux(_T_97, UInt<3>("h0"), UInt<3>("h0")) @[Lookup.scala 33:37] + node _T_627 = mux(_T_95, UInt<3>("h4"), _T_626) @[Lookup.scala 33:37] + node _T_628 = mux(_T_93, UInt<3>("h4"), _T_627) @[Lookup.scala 33:37] + node _T_629 = mux(_T_91, UInt<3>("h4"), _T_628) @[Lookup.scala 33:37] + node _T_630 = mux(_T_89, UInt<3>("h3"), _T_629) @[Lookup.scala 33:37] + node _T_631 = mux(_T_87, UInt<3>("h2"), _T_630) @[Lookup.scala 33:37] + node _T_632 = mux(_T_85, UInt<3>("h1"), _T_631) @[Lookup.scala 33:37] + node _T_633 = mux(_T_83, UInt<3>("h3"), _T_632) @[Lookup.scala 33:37] + node _T_634 = mux(_T_81, UInt<3>("h2"), _T_633) @[Lookup.scala 33:37] + node _T_635 = mux(_T_79, UInt<3>("h1"), _T_634) @[Lookup.scala 33:37] + node _T_636 = mux(_T_77, UInt<3>("h0"), _T_635) @[Lookup.scala 33:37] + node _T_637 = mux(_T_75, UInt<3>("h0"), _T_636) @[Lookup.scala 33:37] + node _T_638 = mux(_T_73, UInt<3>("h0"), _T_637) @[Lookup.scala 33:37] + node _T_639 = mux(_T_71, UInt<3>("h0"), _T_638) @[Lookup.scala 33:37] + node _T_640 = mux(_T_69, UInt<3>("h0"), _T_639) @[Lookup.scala 33:37] + node _T_641 = mux(_T_67, UInt<3>("h0"), _T_640) @[Lookup.scala 33:37] + node _T_642 = mux(_T_65, UInt<3>("h0"), _T_641) @[Lookup.scala 33:37] + node _T_643 = mux(_T_63, UInt<3>("h0"), _T_642) @[Lookup.scala 33:37] + node _T_644 = mux(_T_61, UInt<3>("h0"), _T_643) @[Lookup.scala 33:37] + node _T_645 = mux(_T_59, UInt<3>("h0"), _T_644) @[Lookup.scala 33:37] + node _T_646 = mux(_T_57, UInt<3>("h0"), _T_645) @[Lookup.scala 33:37] + node _T_647 = mux(_T_55, UInt<3>("h0"), _T_646) @[Lookup.scala 33:37] + node _T_648 = mux(_T_53, UInt<3>("h0"), _T_647) @[Lookup.scala 33:37] + node _T_649 = mux(_T_51, UInt<3>("h0"), _T_648) @[Lookup.scala 33:37] + node _T_650 = mux(_T_49, UInt<3>("h0"), _T_649) @[Lookup.scala 33:37] + node _T_651 = mux(_T_47, UInt<3>("h0"), _T_650) @[Lookup.scala 33:37] + node _T_652 = mux(_T_45, UInt<3>("h0"), _T_651) @[Lookup.scala 33:37] + node _T_653 = mux(_T_43, UInt<3>("h0"), _T_652) @[Lookup.scala 33:37] + node _T_654 = mux(_T_41, UInt<3>("h0"), _T_653) @[Lookup.scala 33:37] + node _T_655 = mux(_T_39, UInt<3>("h0"), _T_654) @[Lookup.scala 33:37] + node _T_656 = mux(_T_37, UInt<3>("h0"), _T_655) @[Lookup.scala 33:37] + node _T_657 = mux(_T_35, UInt<3>("h0"), _T_656) @[Lookup.scala 33:37] + node _T_658 = mux(_T_33, UInt<3>("h0"), _T_657) @[Lookup.scala 33:37] + node _T_659 = mux(_T_31, UInt<3>("h0"), _T_658) @[Lookup.scala 33:37] + node _T_660 = mux(_T_29, UInt<3>("h0"), _T_659) @[Lookup.scala 33:37] + node _T_661 = mux(_T_27, UInt<3>("h0"), _T_660) @[Lookup.scala 33:37] + node _T_662 = mux(_T_25, UInt<3>("h0"), _T_661) @[Lookup.scala 33:37] + node _T_663 = mux(_T_23, UInt<3>("h0"), _T_662) @[Lookup.scala 33:37] + node _T_664 = mux(_T_21, UInt<3>("h0"), _T_663) @[Lookup.scala 33:37] + node _T_665 = mux(_T_19, UInt<3>("h0"), _T_664) @[Lookup.scala 33:37] + node _T_666 = mux(_T_17, UInt<3>("h0"), _T_665) @[Lookup.scala 33:37] + node _T_667 = mux(_T_15, UInt<3>("h0"), _T_666) @[Lookup.scala 33:37] + node _T_668 = mux(_T_13, UInt<3>("h0"), _T_667) @[Lookup.scala 33:37] + node _T_669 = mux(_T_11, UInt<3>("h0"), _T_668) @[Lookup.scala 33:37] + node _T_670 = mux(_T_9, UInt<3>("h0"), _T_669) @[Lookup.scala 33:37] + node _T_671 = mux(_T_7, UInt<3>("h0"), _T_670) @[Lookup.scala 33:37] + node _T_672 = mux(_T_5, UInt<3>("h0"), _T_671) @[Lookup.scala 33:37] + node _T_673 = mux(_T_3, UInt<3>("h0"), _T_672) @[Lookup.scala 33:37] + node ctrlSignals_11 = mux(_T_1, UInt<3>("h0"), _T_673) @[Lookup.scala 33:37] + node _T_674 = mux(_T_97, UInt<1>("h0"), UInt<1>("h1")) @[Lookup.scala 33:37] + node _T_675 = mux(_T_95, UInt<1>("h0"), _T_674) @[Lookup.scala 33:37] + node _T_676 = mux(_T_93, UInt<1>("h0"), _T_675) @[Lookup.scala 33:37] + node _T_677 = mux(_T_91, UInt<1>("h0"), _T_676) @[Lookup.scala 33:37] + node _T_678 = mux(_T_89, UInt<1>("h0"), _T_677) @[Lookup.scala 33:37] + node _T_679 = mux(_T_87, UInt<1>("h0"), _T_678) @[Lookup.scala 33:37] + node _T_680 = mux(_T_85, UInt<1>("h0"), _T_679) @[Lookup.scala 33:37] + node _T_681 = mux(_T_83, UInt<1>("h0"), _T_680) @[Lookup.scala 33:37] + node _T_682 = mux(_T_81, UInt<1>("h0"), _T_681) @[Lookup.scala 33:37] + node _T_683 = mux(_T_79, UInt<1>("h0"), _T_682) @[Lookup.scala 33:37] + node _T_684 = mux(_T_77, UInt<1>("h0"), _T_683) @[Lookup.scala 33:37] + node _T_685 = mux(_T_75, UInt<1>("h0"), _T_684) @[Lookup.scala 33:37] + node _T_686 = mux(_T_73, UInt<1>("h0"), _T_685) @[Lookup.scala 33:37] + node _T_687 = mux(_T_71, UInt<1>("h0"), _T_686) @[Lookup.scala 33:37] + node _T_688 = mux(_T_69, UInt<1>("h0"), _T_687) @[Lookup.scala 33:37] + node _T_689 = mux(_T_67, UInt<1>("h0"), _T_688) @[Lookup.scala 33:37] + node _T_690 = mux(_T_65, UInt<1>("h0"), _T_689) @[Lookup.scala 33:37] + node _T_691 = mux(_T_63, UInt<1>("h0"), _T_690) @[Lookup.scala 33:37] + node _T_692 = mux(_T_61, UInt<1>("h0"), _T_691) @[Lookup.scala 33:37] + node _T_693 = mux(_T_59, UInt<1>("h0"), _T_692) @[Lookup.scala 33:37] + node _T_694 = mux(_T_57, UInt<1>("h0"), _T_693) @[Lookup.scala 33:37] + node _T_695 = mux(_T_55, UInt<1>("h0"), _T_694) @[Lookup.scala 33:37] + node _T_696 = mux(_T_53, UInt<1>("h0"), _T_695) @[Lookup.scala 33:37] + node _T_697 = mux(_T_51, UInt<1>("h0"), _T_696) @[Lookup.scala 33:37] + node _T_698 = mux(_T_49, UInt<1>("h0"), _T_697) @[Lookup.scala 33:37] + node _T_699 = mux(_T_47, UInt<1>("h0"), _T_698) @[Lookup.scala 33:37] + node _T_700 = mux(_T_45, UInt<1>("h0"), _T_699) @[Lookup.scala 33:37] + node _T_701 = mux(_T_43, UInt<1>("h0"), _T_700) @[Lookup.scala 33:37] + node _T_702 = mux(_T_41, UInt<1>("h0"), _T_701) @[Lookup.scala 33:37] + node _T_703 = mux(_T_39, UInt<1>("h0"), _T_702) @[Lookup.scala 33:37] + node _T_704 = mux(_T_37, UInt<1>("h0"), _T_703) @[Lookup.scala 33:37] + node _T_705 = mux(_T_35, UInt<1>("h0"), _T_704) @[Lookup.scala 33:37] + node _T_706 = mux(_T_33, UInt<1>("h0"), _T_705) @[Lookup.scala 33:37] + node _T_707 = mux(_T_31, UInt<1>("h0"), _T_706) @[Lookup.scala 33:37] + node _T_708 = mux(_T_29, UInt<1>("h0"), _T_707) @[Lookup.scala 33:37] + node _T_709 = mux(_T_27, UInt<1>("h0"), _T_708) @[Lookup.scala 33:37] + node _T_710 = mux(_T_25, UInt<1>("h0"), _T_709) @[Lookup.scala 33:37] + node _T_711 = mux(_T_23, UInt<1>("h0"), _T_710) @[Lookup.scala 33:37] + node _T_712 = mux(_T_21, UInt<1>("h0"), _T_711) @[Lookup.scala 33:37] + node _T_713 = mux(_T_19, UInt<1>("h0"), _T_712) @[Lookup.scala 33:37] + node _T_714 = mux(_T_17, UInt<1>("h0"), _T_713) @[Lookup.scala 33:37] + node _T_715 = mux(_T_15, UInt<1>("h0"), _T_714) @[Lookup.scala 33:37] + node _T_716 = mux(_T_13, UInt<1>("h0"), _T_715) @[Lookup.scala 33:37] + node _T_717 = mux(_T_11, UInt<1>("h0"), _T_716) @[Lookup.scala 33:37] + node _T_718 = mux(_T_9, UInt<1>("h0"), _T_717) @[Lookup.scala 33:37] + node _T_719 = mux(_T_7, UInt<1>("h0"), _T_718) @[Lookup.scala 33:37] + node _T_720 = mux(_T_5, UInt<1>("h0"), _T_719) @[Lookup.scala 33:37] + node _T_721 = mux(_T_3, UInt<1>("h0"), _T_720) @[Lookup.scala 33:37] + node ctrlSignals_12 = mux(_T_1, UInt<1>("h0"), _T_721) @[Lookup.scala 33:37] + io.pc_sel <= ctrlSignals_0 @[Control.scala 149:16] + node _T_722 = bits(ctrlSignals_6, 0, 0) @[Control.scala 150:34] + io.inst_kill <= _T_722 @[Control.scala 150:16] + io.A_sel <= ctrlSignals_1 @[Control.scala 153:14] + io.B_sel <= ctrlSignals_2 @[Control.scala 154:14] + io.imm_sel <= ctrlSignals_3 @[Control.scala 155:14] + io.alu_op <= ctrlSignals_4 @[Control.scala 156:14] + io.br_type <= ctrlSignals_5 @[Control.scala 157:14] + io.st_type <= ctrlSignals_7 @[Control.scala 158:14] + io.ld_type <= ctrlSignals_8 @[Control.scala 161:14] + io.wb_sel <= ctrlSignals_9 @[Control.scala 162:14] + node _T_723 = bits(ctrlSignals_10, 0, 0) @[Control.scala 163:33] + io.wb_en <= _T_723 @[Control.scala 163:14] + io.csr_cmd <= ctrlSignals_11 @[Control.scala 164:14] + io.illegal <= ctrlSignals_12 @[Control.scala 165:14] + + module Core : + input clock : Clock + input reset : Reset + output io : { host : { flip fromhost : { valid : UInt<1>, bits : UInt<32>}, tohost : UInt<32>}, flip icache : { flip abort : UInt<1>, flip req : { valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, mask : UInt<4>}}, resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip dcache : { flip abort : UInt<1>, flip req : { valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, mask : UInt<4>}}, resp : { valid : UInt<1>, bits : { data : UInt<32>}}}} + + inst dpath of Datapath @[Core.scala 35:21] + dpath.clock <= clock + dpath.reset <= reset + inst ctrl of Control @[Core.scala 36:21] + ctrl.clock <= clock + ctrl.reset <= reset + io.host.tohost <= dpath.io.host.tohost @[Core.scala 38:11] + dpath.io.host.fromhost.bits <= io.host.fromhost.bits @[Core.scala 38:11] + dpath.io.host.fromhost.valid <= io.host.fromhost.valid @[Core.scala 38:11] + dpath.io.icache.resp.bits.data <= io.icache.resp.bits.data @[Core.scala 39:19] + dpath.io.icache.resp.valid <= io.icache.resp.valid @[Core.scala 39:19] + io.icache.req.bits.mask <= dpath.io.icache.req.bits.mask @[Core.scala 39:19] + io.icache.req.bits.data <= dpath.io.icache.req.bits.data @[Core.scala 39:19] + io.icache.req.bits.addr <= dpath.io.icache.req.bits.addr @[Core.scala 39:19] + io.icache.req.valid <= dpath.io.icache.req.valid @[Core.scala 39:19] + io.icache.abort <= dpath.io.icache.abort @[Core.scala 39:19] + dpath.io.dcache.resp.bits.data <= io.dcache.resp.bits.data @[Core.scala 40:19] + dpath.io.dcache.resp.valid <= io.dcache.resp.valid @[Core.scala 40:19] + io.dcache.req.bits.mask <= dpath.io.dcache.req.bits.mask @[Core.scala 40:19] + io.dcache.req.bits.data <= dpath.io.dcache.req.bits.data @[Core.scala 40:19] + io.dcache.req.bits.addr <= dpath.io.dcache.req.bits.addr @[Core.scala 40:19] + io.dcache.req.valid <= dpath.io.dcache.req.valid @[Core.scala 40:19] + io.dcache.abort <= dpath.io.dcache.abort @[Core.scala 40:19] + dpath.io.ctrl.illegal <= ctrl.io.illegal @[Core.scala 41:17] + dpath.io.ctrl.csr_cmd <= ctrl.io.csr_cmd @[Core.scala 41:17] + dpath.io.ctrl.wb_en <= ctrl.io.wb_en @[Core.scala 41:17] + dpath.io.ctrl.wb_sel <= ctrl.io.wb_sel @[Core.scala 41:17] + dpath.io.ctrl.ld_type <= ctrl.io.ld_type @[Core.scala 41:17] + dpath.io.ctrl.st_type <= ctrl.io.st_type @[Core.scala 41:17] + dpath.io.ctrl.br_type <= ctrl.io.br_type @[Core.scala 41:17] + dpath.io.ctrl.alu_op <= ctrl.io.alu_op @[Core.scala 41:17] + dpath.io.ctrl.imm_sel <= ctrl.io.imm_sel @[Core.scala 41:17] + dpath.io.ctrl.B_sel <= ctrl.io.B_sel @[Core.scala 41:17] + dpath.io.ctrl.A_sel <= ctrl.io.A_sel @[Core.scala 41:17] + dpath.io.ctrl.inst_kill <= ctrl.io.inst_kill @[Core.scala 41:17] + dpath.io.ctrl.pc_sel <= ctrl.io.pc_sel @[Core.scala 41:17] + ctrl.io.inst <= dpath.io.ctrl.inst @[Core.scala 41:17] + + module Cache : + input clock : Clock + input reset : Reset + output io : { cpu : { flip abort : UInt<1>, flip req : { valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, mask : UInt<4>}}, resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, nasti : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} + + reg state : UInt<3>, clock with : + reset => (reset, UInt<3>("h0")) @[Cache.scala 58:22] + reg v : UInt<256>, clock with : + reset => (reset, UInt<256>("h0")) @[Cache.scala 60:25] + reg d : UInt<256>, clock with : + reset => (reset, UInt<256>("h0")) @[Cache.scala 61:25] + smem metaMem : { tag : UInt<20>} [256] @[Cache.scala 62:29] + smem dataMem_0 : UInt<8>[4] [256] @[Cache.scala 63:46] + smem dataMem_1 : UInt<8>[4] [256] @[Cache.scala 63:46] + smem dataMem_2 : UInt<8>[4] [256] @[Cache.scala 63:46] + smem dataMem_3 : UInt<8>[4] [256] @[Cache.scala 63:46] + reg addr_reg : UInt<32>, clock with : + reset => (UInt<1>("h0"), addr_reg) @[Cache.scala 65:21] + reg cpu_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), cpu_data) @[Cache.scala 66:21] + reg cpu_mask : UInt<4>, clock with : + reset => (UInt<1>("h0"), cpu_mask) @[Cache.scala 67:21] + node _T = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 40:37] + reg read_count : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Counter.scala 29:33] + wire read_wrap_out : UInt<1> + read_wrap_out <= UInt<1>("h0") + when _T : @[Counter.scala 67:17] + node _T_1 = eq(read_count, UInt<1>("h1")) @[Counter.scala 38:24] + node _T_2 = add(read_count, UInt<1>("h1")) @[Counter.scala 39:22] + node _T_3 = tail(_T_2, 1) @[Counter.scala 39:22] + read_count <= _T_3 @[Counter.scala 39:13] + read_wrap_out <= _T_1 @[Counter.scala 67:24] + node _T_4 = and(io.nasti.w.ready, io.nasti.w.valid) @[Decoupled.scala 40:37] + reg write_count : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Counter.scala 29:33] + wire write_wrap_out : UInt<1> + write_wrap_out <= UInt<1>("h0") + when _T_4 : @[Counter.scala 67:17] + node _T_5 = eq(write_count, UInt<1>("h1")) @[Counter.scala 38:24] + node _T_6 = add(write_count, UInt<1>("h1")) @[Counter.scala 39:22] + node _T_7 = tail(_T_6, 1) @[Counter.scala 39:22] + write_count <= _T_7 @[Counter.scala 39:13] + write_wrap_out <= _T_5 @[Counter.scala 67:24] + node is_idle = eq(state, UInt<3>("h0")) @[Cache.scala 74:25] + node is_read = eq(state, UInt<3>("h1")) @[Cache.scala 75:25] + node is_write = eq(state, UInt<3>("h2")) @[Cache.scala 76:25] + node _T_8 = eq(state, UInt<3>("h6")) @[Cache.scala 77:25] + node is_alloc = and(_T_8, read_wrap_out) @[Cache.scala 77:38] + reg is_alloc_reg : UInt<1>, clock with : + reset => (UInt<1>("h0"), is_alloc_reg) @[Cache.scala 78:29] + is_alloc_reg <= is_alloc @[Cache.scala 78:29] + wire hit : UInt<1> @[Cache.scala 80:17] + node _T_9 = or(hit, is_alloc_reg) @[Cache.scala 81:30] + node _T_10 = and(is_write, _T_9) @[Cache.scala 81:22] + node _T_11 = eq(io.cpu.abort, UInt<1>("h0")) @[Cache.scala 81:50] + node _T_12 = and(_T_10, _T_11) @[Cache.scala 81:47] + node wen = or(_T_12, is_alloc) @[Cache.scala 81:64] + node _T_13 = eq(wen, UInt<1>("h0")) @[Cache.scala 82:13] + node _T_14 = or(is_idle, is_read) @[Cache.scala 82:30] + node _T_15 = and(_T_13, _T_14) @[Cache.scala 82:18] + node ren = and(_T_15, io.cpu.req.valid) @[Cache.scala 82:42] + reg ren_reg : UInt<1>, clock with : + reset => (UInt<1>("h0"), ren_reg) @[Cache.scala 83:24] + ren_reg <= ren @[Cache.scala 83:24] + node idx = bits(io.cpu.req.bits.addr, 11, 4) @[Cache.scala 86:22] + node tag_reg = bits(addr_reg, 31, 12) @[Cache.scala 87:26] + node idx_reg = bits(addr_reg, 11, 4) @[Cache.scala 88:26] + node off_reg = bits(addr_reg, 3, 2) @[Cache.scala 89:26] + wire _T_16 : UInt @[Cache.scala 91:27] + _T_16 is invalid @[Cache.scala 91:27] + when ren : @[Cache.scala 91:27] + _T_16 <= idx @[Cache.scala 91:27] + node _T_17 = or(_T_16, UInt<8>("h0")) @[Cache.scala 91:27] + node _T_18 = bits(_T_17, 7, 0) @[Cache.scala 91:27] + read mport rmeta = metaMem[_T_18], clock @[Cache.scala 91:27] + wire _T_19 : UInt @[Cache.scala 92:39] + _T_19 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_19 <= idx @[Cache.scala 92:39] + node _T_20 = or(_T_19, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_21 = bits(_T_20, 7, 0) @[Cache.scala 92:39] + read mport _T_22 = dataMem_0[_T_21], clock @[Cache.scala 92:39] + node _T_23 = cat(_T_22[1], _T_22[0]) @[Cache.scala 92:50] + node _T_24 = cat(_T_22[3], _T_22[2]) @[Cache.scala 92:50] + node _T_25 = cat(_T_24, _T_23) @[Cache.scala 92:50] + wire _T_26 : UInt @[Cache.scala 92:39] + _T_26 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_26 <= idx @[Cache.scala 92:39] + node _T_27 = or(_T_26, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_28 = bits(_T_27, 7, 0) @[Cache.scala 92:39] + read mport _T_29 = dataMem_1[_T_28], clock @[Cache.scala 92:39] + node _T_30 = cat(_T_29[1], _T_29[0]) @[Cache.scala 92:50] + node _T_31 = cat(_T_29[3], _T_29[2]) @[Cache.scala 92:50] + node _T_32 = cat(_T_31, _T_30) @[Cache.scala 92:50] + wire _T_33 : UInt @[Cache.scala 92:39] + _T_33 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_33 <= idx @[Cache.scala 92:39] + node _T_34 = or(_T_33, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_35 = bits(_T_34, 7, 0) @[Cache.scala 92:39] + read mport _T_36 = dataMem_2[_T_35], clock @[Cache.scala 92:39] + node _T_37 = cat(_T_36[1], _T_36[0]) @[Cache.scala 92:50] + node _T_38 = cat(_T_36[3], _T_36[2]) @[Cache.scala 92:50] + node _T_39 = cat(_T_38, _T_37) @[Cache.scala 92:50] + wire _T_40 : UInt @[Cache.scala 92:39] + _T_40 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_40 <= idx @[Cache.scala 92:39] + node _T_41 = or(_T_40, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_42 = bits(_T_41, 7, 0) @[Cache.scala 92:39] + read mport _T_43 = dataMem_3[_T_42], clock @[Cache.scala 92:39] + node _T_44 = cat(_T_43[1], _T_43[0]) @[Cache.scala 92:50] + node _T_45 = cat(_T_43[3], _T_43[2]) @[Cache.scala 92:50] + node _T_46 = cat(_T_45, _T_44) @[Cache.scala 92:50] + node _T_47 = cat(_T_32, _T_25) @[Cat.scala 30:58] + node _T_48 = cat(_T_46, _T_39) @[Cat.scala 30:58] + node rdata = cat(_T_48, _T_47) @[Cat.scala 30:58] + reg rdata_buf : UInt<128>, clock with : + reset => (UInt<1>("h0"), rdata_buf) @[Reg.scala 15:16] + when ren_reg : @[Reg.scala 16:19] + rdata_buf <= rdata @[Reg.scala 16:23] + reg refill_buf : UInt<64>[2], clock with : + reset => (UInt<1>("h0"), refill_buf) @[Cache.scala 94:23] + node _T_49 = cat(refill_buf[1], refill_buf[0]) @[Cache.scala 95:43] + node _T_50 = mux(ren_reg, rdata, rdata_buf) @[Cache.scala 95:54] + node read = mux(is_alloc_reg, _T_49, _T_50) @[Cache.scala 95:17] + node _T_51 = dshr(v, idx_reg) @[Cache.scala 97:11] + node _T_52 = bits(_T_51, 0, 0) @[Cache.scala 97:11] + node _T_53 = eq(rmeta.tag, tag_reg) @[Cache.scala 97:34] + node _T_54 = and(_T_52, _T_53) @[Cache.scala 97:21] + hit <= _T_54 @[Cache.scala 97:7] + node _T_55 = bits(read, 31, 0) @[Cache.scala 100:62] + node _T_56 = bits(read, 63, 32) @[Cache.scala 100:62] + node _T_57 = bits(read, 95, 64) @[Cache.scala 100:62] + node _T_58 = bits(read, 127, 96) @[Cache.scala 100:62] + wire _T_59 : UInt<32>[4] @[Cache.scala 100:52] + _T_59[0] <= _T_55 @[Cache.scala 100:52] + _T_59[1] <= _T_56 @[Cache.scala 100:52] + _T_59[2] <= _T_57 @[Cache.scala 100:52] + _T_59[3] <= _T_58 @[Cache.scala 100:52] + io.cpu.resp.bits.data <= _T_59[off_reg] @[Cache.scala 100:25] + node _T_60 = and(is_read, hit) @[Cache.scala 101:47] + node _T_61 = or(is_idle, _T_60) @[Cache.scala 101:36] + node _T_62 = orr(cpu_mask) @[Cache.scala 101:83] + node _T_63 = eq(_T_62, UInt<1>("h0")) @[Cache.scala 101:73] + node _T_64 = and(is_alloc_reg, _T_63) @[Cache.scala 101:70] + node _T_65 = or(_T_61, _T_64) @[Cache.scala 101:54] + io.cpu.resp.valid <= _T_65 @[Cache.scala 101:25] + when io.cpu.resp.valid : @[Cache.scala 103:27] + addr_reg <= io.cpu.req.bits.addr @[Cache.scala 104:15] + cpu_data <= io.cpu.req.bits.data @[Cache.scala 105:15] + cpu_mask <= io.cpu.req.bits.mask @[Cache.scala 106:15] + wire wmeta : { tag : UInt<20>} @[Cache.scala 109:19] + wmeta.tag <= tag_reg @[Cache.scala 110:13] + node _T_66 = eq(is_alloc, UInt<1>("h0")) @[Cache.scala 112:19] + node _T_67 = cat(off_reg, UInt<2>("h0")) @[Cat.scala 30:58] + node _T_68 = dshl(cpu_mask, _T_67) @[Cache.scala 112:40] + node _T_69 = cvt(_T_68) @[Cache.scala 112:80] + node wmask = mux(_T_66, _T_69, asSInt(UInt<1>("h1"))) @[Cache.scala 112:18] + node _T_70 = eq(is_alloc, UInt<1>("h0")) @[Cache.scala 113:19] + node _T_71 = cat(cpu_data, cpu_data) @[Cat.scala 30:58] + node _T_72 = cat(_T_71, _T_71) @[Cat.scala 30:58] + node _T_73 = cat(io.nasti.r.bits.data, refill_buf[0]) @[Cat.scala 30:58] + node wdata = mux(_T_70, _T_72, _T_73) @[Cache.scala 113:18] + when wen : @[Cache.scala 116:13] + node _T_74 = dshl(UInt<1>("h1"), idx_reg) @[Cache.scala 117:18] + node _T_75 = or(v, _T_74) @[Cache.scala 117:18] + node _T_76 = not(v) @[Cache.scala 117:18] + node _T_77 = or(_T_76, _T_74) @[Cache.scala 117:18] + node _T_78 = not(_T_77) @[Cache.scala 117:18] + node _T_79 = mux(UInt<1>("h1"), _T_75, _T_78) @[Cache.scala 117:18] + v <= _T_79 @[Cache.scala 117:7] + node _T_80 = eq(is_alloc, UInt<1>("h0")) @[Cache.scala 118:28] + node _T_81 = dshl(UInt<1>("h1"), idx_reg) @[Cache.scala 118:18] + node _T_82 = or(d, _T_81) @[Cache.scala 118:18] + node _T_83 = not(d) @[Cache.scala 118:18] + node _T_84 = or(_T_83, _T_81) @[Cache.scala 118:18] + node _T_85 = not(_T_84) @[Cache.scala 118:18] + node _T_86 = mux(_T_80, _T_82, _T_85) @[Cache.scala 118:18] + d <= _T_86 @[Cache.scala 118:7] + when is_alloc : @[Cache.scala 119:20] + write mport _T_87 = metaMem[idx_reg], clock + _T_87.tag <= wmeta.tag + node _T_88 = bits(wdata, 7, 0) @[Cache.scala 123:53] + node _T_89 = bits(wdata, 15, 8) @[Cache.scala 123:53] + node _T_90 = bits(wdata, 23, 16) @[Cache.scala 123:53] + node _T_91 = bits(wdata, 31, 24) @[Cache.scala 123:53] + wire _T_92 : UInt<8>[4] @[Cache.scala 123:42] + _T_92[0] <= _T_88 @[Cache.scala 123:42] + _T_92[1] <= _T_89 @[Cache.scala 123:42] + _T_92[2] <= _T_90 @[Cache.scala 123:42] + _T_92[3] <= _T_91 @[Cache.scala 123:42] + node _T_93 = bits(wmask, 3, 0) @[Cache.scala 124:37] + node _T_94 = bits(_T_93, 0, 0) @[Cache.scala 124:71] + node _T_95 = bits(_T_93, 1, 1) @[Cache.scala 124:71] + node _T_96 = bits(_T_93, 2, 2) @[Cache.scala 124:71] + node _T_97 = bits(_T_93, 3, 3) @[Cache.scala 124:71] + write mport _T_98 = dataMem_0[idx_reg], clock + when _T_94 : + _T_98[0] <= _T_92[0] + when _T_95 : + _T_98[1] <= _T_92[1] + when _T_96 : + _T_98[2] <= _T_92[2] + when _T_97 : + _T_98[3] <= _T_92[3] + node _T_99 = bits(wdata, 39, 32) @[Cache.scala 123:53] + node _T_100 = bits(wdata, 47, 40) @[Cache.scala 123:53] + node _T_101 = bits(wdata, 55, 48) @[Cache.scala 123:53] + node _T_102 = bits(wdata, 63, 56) @[Cache.scala 123:53] + wire _T_103 : UInt<8>[4] @[Cache.scala 123:42] + _T_103[0] <= _T_99 @[Cache.scala 123:42] + _T_103[1] <= _T_100 @[Cache.scala 123:42] + _T_103[2] <= _T_101 @[Cache.scala 123:42] + _T_103[3] <= _T_102 @[Cache.scala 123:42] + node _T_104 = bits(wmask, 7, 4) @[Cache.scala 124:37] + node _T_105 = bits(_T_104, 0, 0) @[Cache.scala 124:71] + node _T_106 = bits(_T_104, 1, 1) @[Cache.scala 124:71] + node _T_107 = bits(_T_104, 2, 2) @[Cache.scala 124:71] + node _T_108 = bits(_T_104, 3, 3) @[Cache.scala 124:71] + write mport _T_109 = dataMem_1[idx_reg], clock + when _T_105 : + _T_109[0] <= _T_103[0] + when _T_106 : + _T_109[1] <= _T_103[1] + when _T_107 : + _T_109[2] <= _T_103[2] + when _T_108 : + _T_109[3] <= _T_103[3] + node _T_110 = bits(wdata, 71, 64) @[Cache.scala 123:53] + node _T_111 = bits(wdata, 79, 72) @[Cache.scala 123:53] + node _T_112 = bits(wdata, 87, 80) @[Cache.scala 123:53] + node _T_113 = bits(wdata, 95, 88) @[Cache.scala 123:53] + wire _T_114 : UInt<8>[4] @[Cache.scala 123:42] + _T_114[0] <= _T_110 @[Cache.scala 123:42] + _T_114[1] <= _T_111 @[Cache.scala 123:42] + _T_114[2] <= _T_112 @[Cache.scala 123:42] + _T_114[3] <= _T_113 @[Cache.scala 123:42] + node _T_115 = bits(wmask, 11, 8) @[Cache.scala 124:37] + node _T_116 = bits(_T_115, 0, 0) @[Cache.scala 124:71] + node _T_117 = bits(_T_115, 1, 1) @[Cache.scala 124:71] + node _T_118 = bits(_T_115, 2, 2) @[Cache.scala 124:71] + node _T_119 = bits(_T_115, 3, 3) @[Cache.scala 124:71] + write mport _T_120 = dataMem_2[idx_reg], clock + when _T_116 : + _T_120[0] <= _T_114[0] + when _T_117 : + _T_120[1] <= _T_114[1] + when _T_118 : + _T_120[2] <= _T_114[2] + when _T_119 : + _T_120[3] <= _T_114[3] + node _T_121 = bits(wdata, 103, 96) @[Cache.scala 123:53] + node _T_122 = bits(wdata, 111, 104) @[Cache.scala 123:53] + node _T_123 = bits(wdata, 119, 112) @[Cache.scala 123:53] + node _T_124 = bits(wdata, 127, 120) @[Cache.scala 123:53] + wire _T_125 : UInt<8>[4] @[Cache.scala 123:42] + _T_125[0] <= _T_121 @[Cache.scala 123:42] + _T_125[1] <= _T_122 @[Cache.scala 123:42] + _T_125[2] <= _T_123 @[Cache.scala 123:42] + _T_125[3] <= _T_124 @[Cache.scala 123:42] + node _T_126 = bits(wmask, 15, 12) @[Cache.scala 124:37] + node _T_127 = bits(_T_126, 0, 0) @[Cache.scala 124:71] + node _T_128 = bits(_T_126, 1, 1) @[Cache.scala 124:71] + node _T_129 = bits(_T_126, 2, 2) @[Cache.scala 124:71] + node _T_130 = bits(_T_126, 3, 3) @[Cache.scala 124:71] + write mport _T_131 = dataMem_3[idx_reg], clock + when _T_127 : + _T_131[0] <= _T_125[0] + when _T_128 : + _T_131[1] <= _T_125[1] + when _T_129 : + _T_131[2] <= _T_125[2] + when _T_130 : + _T_131[3] <= _T_125[3] + node _T_132 = cat(tag_reg, idx_reg) @[Cat.scala 30:58] + node _T_133 = dshl(_T_132, UInt<3>("h4")) @[Cache.scala 130:33] + wire _T_134 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} @[nasti.scala 178:18] + _T_134 is invalid @[nasti.scala 178:18] + _T_134.id <= UInt<1>("h0") @[nasti.scala 179:11] + _T_134.addr <= _T_133 @[nasti.scala 180:13] + _T_134.len <= UInt<1>("h1") @[nasti.scala 181:12] + _T_134.size <= UInt<2>("h3") @[nasti.scala 182:13] + _T_134.burst <= UInt<1>("h1") @[nasti.scala 183:14] + _T_134.lock <= UInt<1>("h0") @[nasti.scala 184:13] + _T_134.cache <= UInt<1>("h0") @[nasti.scala 185:14] + node _T_135 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_136 = cat(_T_135, UInt<1>("h0")) @[Cat.scala 30:58] + _T_134.prot <= _T_136 @[nasti.scala 186:13] + _T_134.qos <= UInt<1>("h0") @[nasti.scala 187:12] + _T_134.region <= UInt<1>("h0") @[nasti.scala 188:15] + _T_134.user <= UInt<1>("h0") @[nasti.scala 189:13] + io.nasti.ar.bits.user <= _T_134.user @[Cache.scala 129:20] + io.nasti.ar.bits.id <= _T_134.id @[Cache.scala 129:20] + io.nasti.ar.bits.region <= _T_134.region @[Cache.scala 129:20] + io.nasti.ar.bits.qos <= _T_134.qos @[Cache.scala 129:20] + io.nasti.ar.bits.prot <= _T_134.prot @[Cache.scala 129:20] + io.nasti.ar.bits.cache <= _T_134.cache @[Cache.scala 129:20] + io.nasti.ar.bits.lock <= _T_134.lock @[Cache.scala 129:20] + io.nasti.ar.bits.burst <= _T_134.burst @[Cache.scala 129:20] + io.nasti.ar.bits.size <= _T_134.size @[Cache.scala 129:20] + io.nasti.ar.bits.len <= _T_134.len @[Cache.scala 129:20] + io.nasti.ar.bits.addr <= _T_134.addr @[Cache.scala 129:20] + io.nasti.ar.valid <= UInt<1>("h0") @[Cache.scala 131:21] + node _T_137 = eq(state, UInt<3>("h6")) @[Cache.scala 133:29] + io.nasti.r.ready <= _T_137 @[Cache.scala 133:20] + node _T_138 = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 40:37] + when _T_138 : @[Cache.scala 134:27] + refill_buf[read_count] <= io.nasti.r.bits.data @[Cache.scala 134:52] + node _T_139 = cat(rmeta.tag, idx_reg) @[Cat.scala 30:58] + node _T_140 = dshl(_T_139, UInt<3>("h4")) @[Cache.scala 138:35] + wire _T_141 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} @[nasti.scala 158:18] + _T_141 is invalid @[nasti.scala 158:18] + _T_141.id <= UInt<1>("h0") @[nasti.scala 159:11] + _T_141.addr <= _T_140 @[nasti.scala 160:13] + _T_141.len <= UInt<1>("h1") @[nasti.scala 161:12] + _T_141.size <= UInt<2>("h3") @[nasti.scala 162:13] + _T_141.burst <= UInt<1>("h1") @[nasti.scala 163:14] + _T_141.lock <= UInt<1>("h0") @[nasti.scala 164:13] + _T_141.cache <= UInt<1>("h0") @[nasti.scala 165:14] + node _T_142 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_143 = cat(_T_142, UInt<1>("h0")) @[Cat.scala 30:58] + _T_141.prot <= _T_143 @[nasti.scala 166:13] + _T_141.qos <= UInt<1>("h0") @[nasti.scala 167:12] + _T_141.region <= UInt<1>("h0") @[nasti.scala 168:15] + _T_141.user <= UInt<1>("h0") @[nasti.scala 169:13] + io.nasti.aw.bits.user <= _T_141.user @[Cache.scala 137:20] + io.nasti.aw.bits.id <= _T_141.id @[Cache.scala 137:20] + io.nasti.aw.bits.region <= _T_141.region @[Cache.scala 137:20] + io.nasti.aw.bits.qos <= _T_141.qos @[Cache.scala 137:20] + io.nasti.aw.bits.prot <= _T_141.prot @[Cache.scala 137:20] + io.nasti.aw.bits.cache <= _T_141.cache @[Cache.scala 137:20] + io.nasti.aw.bits.lock <= _T_141.lock @[Cache.scala 137:20] + io.nasti.aw.bits.burst <= _T_141.burst @[Cache.scala 137:20] + io.nasti.aw.bits.size <= _T_141.size @[Cache.scala 137:20] + io.nasti.aw.bits.len <= _T_141.len @[Cache.scala 137:20] + io.nasti.aw.bits.addr <= _T_141.addr @[Cache.scala 137:20] + io.nasti.aw.valid <= UInt<1>("h0") @[Cache.scala 139:21] + node _T_144 = bits(read, 63, 0) @[Cache.scala 142:42] + node _T_145 = bits(read, 127, 64) @[Cache.scala 142:42] + wire _T_146 : UInt<64>[2] @[Cache.scala 142:32] + _T_146[0] <= _T_144 @[Cache.scala 142:32] + _T_146[1] <= _T_145 @[Cache.scala 142:32] + wire _T_147 : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>} @[nasti.scala 198:17] + _T_147 is invalid @[nasti.scala 198:17] + node _T_148 = mux(UInt<1>("h1"), UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12] + _T_147.strb <= _T_148 @[nasti.scala 199:12] + _T_147.data <= _T_146[write_count] @[nasti.scala 200:12] + _T_147.last <= write_wrap_out @[nasti.scala 201:12] + _T_147.id <= UInt<1>("h0") @[nasti.scala 202:12] + _T_147.user <= UInt<1>("h0") @[nasti.scala 203:12] + io.nasti.w.bits.user <= _T_147.user @[Cache.scala 141:19] + io.nasti.w.bits.strb <= _T_147.strb @[Cache.scala 141:19] + io.nasti.w.bits.id <= _T_147.id @[Cache.scala 141:19] + io.nasti.w.bits.last <= _T_147.last @[Cache.scala 141:19] + io.nasti.w.bits.data <= _T_147.data @[Cache.scala 141:19] + io.nasti.w.valid <= UInt<1>("h0") @[Cache.scala 144:20] + io.nasti.b.ready <= UInt<1>("h0") @[Cache.scala 146:20] + node _T_149 = dshr(v, idx_reg) @[Cache.scala 149:19] + node _T_150 = bits(_T_149, 0, 0) @[Cache.scala 149:19] + node _T_151 = dshr(d, idx_reg) @[Cache.scala 149:33] + node _T_152 = bits(_T_151, 0, 0) @[Cache.scala 149:33] + node is_dirty = and(_T_150, _T_152) @[Cache.scala 149:29] + node _T_153 = eq(UInt<3>("h0"), state) @[Conditional.scala 37:30] + when _T_153 : @[Conditional.scala 40:58] + when io.cpu.req.valid : @[Cache.scala 152:30] + node _T_154 = orr(io.cpu.req.bits.mask) @[Cache.scala 153:43] + node _T_155 = mux(_T_154, UInt<3>("h2"), UInt<3>("h1")) @[Cache.scala 153:21] + state <= _T_155 @[Cache.scala 153:15] + else : + node _T_156 = eq(UInt<3>("h1"), state) @[Conditional.scala 37:30] + when _T_156 : @[Conditional.scala 39:67] + when hit : @[Cache.scala 157:17] + when io.cpu.req.valid : @[Cache.scala 158:32] + node _T_157 = orr(io.cpu.req.bits.mask) @[Cache.scala 159:45] + node _T_158 = mux(_T_157, UInt<3>("h2"), UInt<3>("h1")) @[Cache.scala 159:23] + state <= _T_158 @[Cache.scala 159:17] + else : + state <= UInt<3>("h0") @[Cache.scala 161:17] + else : + io.nasti.aw.valid <= is_dirty @[Cache.scala 164:27] + node _T_159 = eq(is_dirty, UInt<1>("h0")) @[Cache.scala 165:30] + io.nasti.ar.valid <= _T_159 @[Cache.scala 165:27] + node _T_160 = and(io.nasti.aw.ready, io.nasti.aw.valid) @[Decoupled.scala 40:37] + when _T_160 : @[Cache.scala 166:34] + state <= UInt<3>("h3") @[Cache.scala 167:17] + else : + node _T_161 = and(io.nasti.ar.ready, io.nasti.ar.valid) @[Decoupled.scala 40:37] + when _T_161 : @[Cache.scala 168:40] + state <= UInt<3>("h6") @[Cache.scala 169:17] + else : + node _T_162 = eq(UInt<3>("h2"), state) @[Conditional.scala 37:30] + when _T_162 : @[Conditional.scala 39:67] + node _T_163 = or(hit, is_alloc_reg) @[Cache.scala 174:16] + node _T_164 = or(_T_163, io.cpu.abort) @[Cache.scala 174:32] + when _T_164 : @[Cache.scala 174:49] + state <= UInt<3>("h0") @[Cache.scala 175:15] + else : + io.nasti.aw.valid <= is_dirty @[Cache.scala 177:27] + node _T_165 = eq(is_dirty, UInt<1>("h0")) @[Cache.scala 178:30] + io.nasti.ar.valid <= _T_165 @[Cache.scala 178:27] + node _T_166 = and(io.nasti.aw.ready, io.nasti.aw.valid) @[Decoupled.scala 40:37] + when _T_166 : @[Cache.scala 179:34] + state <= UInt<3>("h3") @[Cache.scala 180:17] + else : + node _T_167 = and(io.nasti.ar.ready, io.nasti.ar.valid) @[Decoupled.scala 40:37] + when _T_167 : @[Cache.scala 181:40] + state <= UInt<3>("h6") @[Cache.scala 182:17] + else : + node _T_168 = eq(UInt<3>("h3"), state) @[Conditional.scala 37:30] + when _T_168 : @[Conditional.scala 39:67] + io.nasti.w.valid <= UInt<1>("h1") @[Cache.scala 187:24] + when write_wrap_out : @[Cache.scala 188:28] + state <= UInt<3>("h4") @[Cache.scala 189:15] + else : + node _T_169 = eq(UInt<3>("h4"), state) @[Conditional.scala 37:30] + when _T_169 : @[Conditional.scala 39:67] + io.nasti.b.ready <= UInt<1>("h1") @[Cache.scala 193:24] + node _T_170 = and(io.nasti.b.ready, io.nasti.b.valid) @[Decoupled.scala 40:37] + when _T_170 : @[Cache.scala 194:31] + state <= UInt<3>("h5") @[Cache.scala 195:15] + else : + node _T_171 = eq(UInt<3>("h5"), state) @[Conditional.scala 37:30] + when _T_171 : @[Conditional.scala 39:67] + io.nasti.ar.valid <= UInt<1>("h1") @[Cache.scala 199:25] + node _T_172 = and(io.nasti.ar.ready, io.nasti.ar.valid) @[Decoupled.scala 40:37] + when _T_172 : @[Cache.scala 200:32] + state <= UInt<3>("h6") @[Cache.scala 201:15] + else : + node _T_173 = eq(UInt<3>("h6"), state) @[Conditional.scala 37:30] + when _T_173 : @[Conditional.scala 39:67] + when read_wrap_out : @[Cache.scala 205:27] + node _T_174 = orr(cpu_mask) @[Cache.scala 206:31] + node _T_175 = mux(_T_174, UInt<3>("h2"), UInt<3>("h0")) @[Cache.scala 206:21] + state <= _T_175 @[Cache.scala 206:15] + + module Cache_1 : + input clock : Clock + input reset : Reset + output io : { cpu : { flip abort : UInt<1>, flip req : { valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, mask : UInt<4>}}, resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, nasti : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} + + reg state : UInt<3>, clock with : + reset => (reset, UInt<3>("h0")) @[Cache.scala 58:22] + reg v : UInt<256>, clock with : + reset => (reset, UInt<256>("h0")) @[Cache.scala 60:25] + reg d : UInt<256>, clock with : + reset => (reset, UInt<256>("h0")) @[Cache.scala 61:25] + smem metaMem : { tag : UInt<20>} [256] @[Cache.scala 62:29] + smem dataMem_0 : UInt<8>[4] [256] @[Cache.scala 63:46] + smem dataMem_1 : UInt<8>[4] [256] @[Cache.scala 63:46] + smem dataMem_2 : UInt<8>[4] [256] @[Cache.scala 63:46] + smem dataMem_3 : UInt<8>[4] [256] @[Cache.scala 63:46] + reg addr_reg : UInt<32>, clock with : + reset => (UInt<1>("h0"), addr_reg) @[Cache.scala 65:21] + reg cpu_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), cpu_data) @[Cache.scala 66:21] + reg cpu_mask : UInt<4>, clock with : + reset => (UInt<1>("h0"), cpu_mask) @[Cache.scala 67:21] + node _T = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 40:37] + reg read_count : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Counter.scala 29:33] + wire read_wrap_out : UInt<1> + read_wrap_out <= UInt<1>("h0") + when _T : @[Counter.scala 67:17] + node _T_1 = eq(read_count, UInt<1>("h1")) @[Counter.scala 38:24] + node _T_2 = add(read_count, UInt<1>("h1")) @[Counter.scala 39:22] + node _T_3 = tail(_T_2, 1) @[Counter.scala 39:22] + read_count <= _T_3 @[Counter.scala 39:13] + read_wrap_out <= _T_1 @[Counter.scala 67:24] + node _T_4 = and(io.nasti.w.ready, io.nasti.w.valid) @[Decoupled.scala 40:37] + reg write_count : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Counter.scala 29:33] + wire write_wrap_out : UInt<1> + write_wrap_out <= UInt<1>("h0") + when _T_4 : @[Counter.scala 67:17] + node _T_5 = eq(write_count, UInt<1>("h1")) @[Counter.scala 38:24] + node _T_6 = add(write_count, UInt<1>("h1")) @[Counter.scala 39:22] + node _T_7 = tail(_T_6, 1) @[Counter.scala 39:22] + write_count <= _T_7 @[Counter.scala 39:13] + write_wrap_out <= _T_5 @[Counter.scala 67:24] + node is_idle = eq(state, UInt<3>("h0")) @[Cache.scala 74:25] + node is_read = eq(state, UInt<3>("h1")) @[Cache.scala 75:25] + node is_write = eq(state, UInt<3>("h2")) @[Cache.scala 76:25] + node _T_8 = eq(state, UInt<3>("h6")) @[Cache.scala 77:25] + node is_alloc = and(_T_8, read_wrap_out) @[Cache.scala 77:38] + reg is_alloc_reg : UInt<1>, clock with : + reset => (UInt<1>("h0"), is_alloc_reg) @[Cache.scala 78:29] + is_alloc_reg <= is_alloc @[Cache.scala 78:29] + wire hit : UInt<1> @[Cache.scala 80:17] + node _T_9 = or(hit, is_alloc_reg) @[Cache.scala 81:30] + node _T_10 = and(is_write, _T_9) @[Cache.scala 81:22] + node _T_11 = eq(io.cpu.abort, UInt<1>("h0")) @[Cache.scala 81:50] + node _T_12 = and(_T_10, _T_11) @[Cache.scala 81:47] + node wen = or(_T_12, is_alloc) @[Cache.scala 81:64] + node _T_13 = eq(wen, UInt<1>("h0")) @[Cache.scala 82:13] + node _T_14 = or(is_idle, is_read) @[Cache.scala 82:30] + node _T_15 = and(_T_13, _T_14) @[Cache.scala 82:18] + node ren = and(_T_15, io.cpu.req.valid) @[Cache.scala 82:42] + reg ren_reg : UInt<1>, clock with : + reset => (UInt<1>("h0"), ren_reg) @[Cache.scala 83:24] + ren_reg <= ren @[Cache.scala 83:24] + node idx = bits(io.cpu.req.bits.addr, 11, 4) @[Cache.scala 86:22] + node tag_reg = bits(addr_reg, 31, 12) @[Cache.scala 87:26] + node idx_reg = bits(addr_reg, 11, 4) @[Cache.scala 88:26] + node off_reg = bits(addr_reg, 3, 2) @[Cache.scala 89:26] + wire _T_16 : UInt @[Cache.scala 91:27] + _T_16 is invalid @[Cache.scala 91:27] + when ren : @[Cache.scala 91:27] + _T_16 <= idx @[Cache.scala 91:27] + node _T_17 = or(_T_16, UInt<8>("h0")) @[Cache.scala 91:27] + node _T_18 = bits(_T_17, 7, 0) @[Cache.scala 91:27] + read mport rmeta = metaMem[_T_18], clock @[Cache.scala 91:27] + wire _T_19 : UInt @[Cache.scala 92:39] + _T_19 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_19 <= idx @[Cache.scala 92:39] + node _T_20 = or(_T_19, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_21 = bits(_T_20, 7, 0) @[Cache.scala 92:39] + read mport _T_22 = dataMem_0[_T_21], clock @[Cache.scala 92:39] + node _T_23 = cat(_T_22[1], _T_22[0]) @[Cache.scala 92:50] + node _T_24 = cat(_T_22[3], _T_22[2]) @[Cache.scala 92:50] + node _T_25 = cat(_T_24, _T_23) @[Cache.scala 92:50] + wire _T_26 : UInt @[Cache.scala 92:39] + _T_26 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_26 <= idx @[Cache.scala 92:39] + node _T_27 = or(_T_26, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_28 = bits(_T_27, 7, 0) @[Cache.scala 92:39] + read mport _T_29 = dataMem_1[_T_28], clock @[Cache.scala 92:39] + node _T_30 = cat(_T_29[1], _T_29[0]) @[Cache.scala 92:50] + node _T_31 = cat(_T_29[3], _T_29[2]) @[Cache.scala 92:50] + node _T_32 = cat(_T_31, _T_30) @[Cache.scala 92:50] + wire _T_33 : UInt @[Cache.scala 92:39] + _T_33 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_33 <= idx @[Cache.scala 92:39] + node _T_34 = or(_T_33, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_35 = bits(_T_34, 7, 0) @[Cache.scala 92:39] + read mport _T_36 = dataMem_2[_T_35], clock @[Cache.scala 92:39] + node _T_37 = cat(_T_36[1], _T_36[0]) @[Cache.scala 92:50] + node _T_38 = cat(_T_36[3], _T_36[2]) @[Cache.scala 92:50] + node _T_39 = cat(_T_38, _T_37) @[Cache.scala 92:50] + wire _T_40 : UInt @[Cache.scala 92:39] + _T_40 is invalid @[Cache.scala 92:39] + when ren : @[Cache.scala 92:39] + _T_40 <= idx @[Cache.scala 92:39] + node _T_41 = or(_T_40, UInt<8>("h0")) @[Cache.scala 92:39] + node _T_42 = bits(_T_41, 7, 0) @[Cache.scala 92:39] + read mport _T_43 = dataMem_3[_T_42], clock @[Cache.scala 92:39] + node _T_44 = cat(_T_43[1], _T_43[0]) @[Cache.scala 92:50] + node _T_45 = cat(_T_43[3], _T_43[2]) @[Cache.scala 92:50] + node _T_46 = cat(_T_45, _T_44) @[Cache.scala 92:50] + node _T_47 = cat(_T_32, _T_25) @[Cat.scala 30:58] + node _T_48 = cat(_T_46, _T_39) @[Cat.scala 30:58] + node rdata = cat(_T_48, _T_47) @[Cat.scala 30:58] + reg rdata_buf : UInt<128>, clock with : + reset => (UInt<1>("h0"), rdata_buf) @[Reg.scala 15:16] + when ren_reg : @[Reg.scala 16:19] + rdata_buf <= rdata @[Reg.scala 16:23] + reg refill_buf : UInt<64>[2], clock with : + reset => (UInt<1>("h0"), refill_buf) @[Cache.scala 94:23] + node _T_49 = cat(refill_buf[1], refill_buf[0]) @[Cache.scala 95:43] + node _T_50 = mux(ren_reg, rdata, rdata_buf) @[Cache.scala 95:54] + node read = mux(is_alloc_reg, _T_49, _T_50) @[Cache.scala 95:17] + node _T_51 = dshr(v, idx_reg) @[Cache.scala 97:11] + node _T_52 = bits(_T_51, 0, 0) @[Cache.scala 97:11] + node _T_53 = eq(rmeta.tag, tag_reg) @[Cache.scala 97:34] + node _T_54 = and(_T_52, _T_53) @[Cache.scala 97:21] + hit <= _T_54 @[Cache.scala 97:7] + node _T_55 = bits(read, 31, 0) @[Cache.scala 100:62] + node _T_56 = bits(read, 63, 32) @[Cache.scala 100:62] + node _T_57 = bits(read, 95, 64) @[Cache.scala 100:62] + node _T_58 = bits(read, 127, 96) @[Cache.scala 100:62] + wire _T_59 : UInt<32>[4] @[Cache.scala 100:52] + _T_59[0] <= _T_55 @[Cache.scala 100:52] + _T_59[1] <= _T_56 @[Cache.scala 100:52] + _T_59[2] <= _T_57 @[Cache.scala 100:52] + _T_59[3] <= _T_58 @[Cache.scala 100:52] + io.cpu.resp.bits.data <= _T_59[off_reg] @[Cache.scala 100:25] + node _T_60 = and(is_read, hit) @[Cache.scala 101:47] + node _T_61 = or(is_idle, _T_60) @[Cache.scala 101:36] + node _T_62 = orr(cpu_mask) @[Cache.scala 101:83] + node _T_63 = eq(_T_62, UInt<1>("h0")) @[Cache.scala 101:73] + node _T_64 = and(is_alloc_reg, _T_63) @[Cache.scala 101:70] + node _T_65 = or(_T_61, _T_64) @[Cache.scala 101:54] + io.cpu.resp.valid <= _T_65 @[Cache.scala 101:25] + when io.cpu.resp.valid : @[Cache.scala 103:27] + addr_reg <= io.cpu.req.bits.addr @[Cache.scala 104:15] + cpu_data <= io.cpu.req.bits.data @[Cache.scala 105:15] + cpu_mask <= io.cpu.req.bits.mask @[Cache.scala 106:15] + wire wmeta : { tag : UInt<20>} @[Cache.scala 109:19] + wmeta.tag <= tag_reg @[Cache.scala 110:13] + node _T_66 = eq(is_alloc, UInt<1>("h0")) @[Cache.scala 112:19] + node _T_67 = cat(off_reg, UInt<2>("h0")) @[Cat.scala 30:58] + node _T_68 = dshl(cpu_mask, _T_67) @[Cache.scala 112:40] + node _T_69 = cvt(_T_68) @[Cache.scala 112:80] + node wmask = mux(_T_66, _T_69, asSInt(UInt<1>("h1"))) @[Cache.scala 112:18] + node _T_70 = eq(is_alloc, UInt<1>("h0")) @[Cache.scala 113:19] + node _T_71 = cat(cpu_data, cpu_data) @[Cat.scala 30:58] + node _T_72 = cat(_T_71, _T_71) @[Cat.scala 30:58] + node _T_73 = cat(io.nasti.r.bits.data, refill_buf[0]) @[Cat.scala 30:58] + node wdata = mux(_T_70, _T_72, _T_73) @[Cache.scala 113:18] + when wen : @[Cache.scala 116:13] + node _T_74 = dshl(UInt<1>("h1"), idx_reg) @[Cache.scala 117:18] + node _T_75 = or(v, _T_74) @[Cache.scala 117:18] + node _T_76 = not(v) @[Cache.scala 117:18] + node _T_77 = or(_T_76, _T_74) @[Cache.scala 117:18] + node _T_78 = not(_T_77) @[Cache.scala 117:18] + node _T_79 = mux(UInt<1>("h1"), _T_75, _T_78) @[Cache.scala 117:18] + v <= _T_79 @[Cache.scala 117:7] + node _T_80 = eq(is_alloc, UInt<1>("h0")) @[Cache.scala 118:28] + node _T_81 = dshl(UInt<1>("h1"), idx_reg) @[Cache.scala 118:18] + node _T_82 = or(d, _T_81) @[Cache.scala 118:18] + node _T_83 = not(d) @[Cache.scala 118:18] + node _T_84 = or(_T_83, _T_81) @[Cache.scala 118:18] + node _T_85 = not(_T_84) @[Cache.scala 118:18] + node _T_86 = mux(_T_80, _T_82, _T_85) @[Cache.scala 118:18] + d <= _T_86 @[Cache.scala 118:7] + when is_alloc : @[Cache.scala 119:20] + write mport _T_87 = metaMem[idx_reg], clock + _T_87.tag <= wmeta.tag + node _T_88 = bits(wdata, 7, 0) @[Cache.scala 123:53] + node _T_89 = bits(wdata, 15, 8) @[Cache.scala 123:53] + node _T_90 = bits(wdata, 23, 16) @[Cache.scala 123:53] + node _T_91 = bits(wdata, 31, 24) @[Cache.scala 123:53] + wire _T_92 : UInt<8>[4] @[Cache.scala 123:42] + _T_92[0] <= _T_88 @[Cache.scala 123:42] + _T_92[1] <= _T_89 @[Cache.scala 123:42] + _T_92[2] <= _T_90 @[Cache.scala 123:42] + _T_92[3] <= _T_91 @[Cache.scala 123:42] + node _T_93 = bits(wmask, 3, 0) @[Cache.scala 124:37] + node _T_94 = bits(_T_93, 0, 0) @[Cache.scala 124:71] + node _T_95 = bits(_T_93, 1, 1) @[Cache.scala 124:71] + node _T_96 = bits(_T_93, 2, 2) @[Cache.scala 124:71] + node _T_97 = bits(_T_93, 3, 3) @[Cache.scala 124:71] + write mport _T_98 = dataMem_0[idx_reg], clock + when _T_94 : + _T_98[0] <= _T_92[0] + when _T_95 : + _T_98[1] <= _T_92[1] + when _T_96 : + _T_98[2] <= _T_92[2] + when _T_97 : + _T_98[3] <= _T_92[3] + node _T_99 = bits(wdata, 39, 32) @[Cache.scala 123:53] + node _T_100 = bits(wdata, 47, 40) @[Cache.scala 123:53] + node _T_101 = bits(wdata, 55, 48) @[Cache.scala 123:53] + node _T_102 = bits(wdata, 63, 56) @[Cache.scala 123:53] + wire _T_103 : UInt<8>[4] @[Cache.scala 123:42] + _T_103[0] <= _T_99 @[Cache.scala 123:42] + _T_103[1] <= _T_100 @[Cache.scala 123:42] + _T_103[2] <= _T_101 @[Cache.scala 123:42] + _T_103[3] <= _T_102 @[Cache.scala 123:42] + node _T_104 = bits(wmask, 7, 4) @[Cache.scala 124:37] + node _T_105 = bits(_T_104, 0, 0) @[Cache.scala 124:71] + node _T_106 = bits(_T_104, 1, 1) @[Cache.scala 124:71] + node _T_107 = bits(_T_104, 2, 2) @[Cache.scala 124:71] + node _T_108 = bits(_T_104, 3, 3) @[Cache.scala 124:71] + write mport _T_109 = dataMem_1[idx_reg], clock + when _T_105 : + _T_109[0] <= _T_103[0] + when _T_106 : + _T_109[1] <= _T_103[1] + when _T_107 : + _T_109[2] <= _T_103[2] + when _T_108 : + _T_109[3] <= _T_103[3] + node _T_110 = bits(wdata, 71, 64) @[Cache.scala 123:53] + node _T_111 = bits(wdata, 79, 72) @[Cache.scala 123:53] + node _T_112 = bits(wdata, 87, 80) @[Cache.scala 123:53] + node _T_113 = bits(wdata, 95, 88) @[Cache.scala 123:53] + wire _T_114 : UInt<8>[4] @[Cache.scala 123:42] + _T_114[0] <= _T_110 @[Cache.scala 123:42] + _T_114[1] <= _T_111 @[Cache.scala 123:42] + _T_114[2] <= _T_112 @[Cache.scala 123:42] + _T_114[3] <= _T_113 @[Cache.scala 123:42] + node _T_115 = bits(wmask, 11, 8) @[Cache.scala 124:37] + node _T_116 = bits(_T_115, 0, 0) @[Cache.scala 124:71] + node _T_117 = bits(_T_115, 1, 1) @[Cache.scala 124:71] + node _T_118 = bits(_T_115, 2, 2) @[Cache.scala 124:71] + node _T_119 = bits(_T_115, 3, 3) @[Cache.scala 124:71] + write mport _T_120 = dataMem_2[idx_reg], clock + when _T_116 : + _T_120[0] <= _T_114[0] + when _T_117 : + _T_120[1] <= _T_114[1] + when _T_118 : + _T_120[2] <= _T_114[2] + when _T_119 : + _T_120[3] <= _T_114[3] + node _T_121 = bits(wdata, 103, 96) @[Cache.scala 123:53] + node _T_122 = bits(wdata, 111, 104) @[Cache.scala 123:53] + node _T_123 = bits(wdata, 119, 112) @[Cache.scala 123:53] + node _T_124 = bits(wdata, 127, 120) @[Cache.scala 123:53] + wire _T_125 : UInt<8>[4] @[Cache.scala 123:42] + _T_125[0] <= _T_121 @[Cache.scala 123:42] + _T_125[1] <= _T_122 @[Cache.scala 123:42] + _T_125[2] <= _T_123 @[Cache.scala 123:42] + _T_125[3] <= _T_124 @[Cache.scala 123:42] + node _T_126 = bits(wmask, 15, 12) @[Cache.scala 124:37] + node _T_127 = bits(_T_126, 0, 0) @[Cache.scala 124:71] + node _T_128 = bits(_T_126, 1, 1) @[Cache.scala 124:71] + node _T_129 = bits(_T_126, 2, 2) @[Cache.scala 124:71] + node _T_130 = bits(_T_126, 3, 3) @[Cache.scala 124:71] + write mport _T_131 = dataMem_3[idx_reg], clock + when _T_127 : + _T_131[0] <= _T_125[0] + when _T_128 : + _T_131[1] <= _T_125[1] + when _T_129 : + _T_131[2] <= _T_125[2] + when _T_130 : + _T_131[3] <= _T_125[3] + node _T_132 = cat(tag_reg, idx_reg) @[Cat.scala 30:58] + node _T_133 = dshl(_T_132, UInt<3>("h4")) @[Cache.scala 130:33] + wire _T_134 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} @[nasti.scala 178:18] + _T_134 is invalid @[nasti.scala 178:18] + _T_134.id <= UInt<1>("h0") @[nasti.scala 179:11] + _T_134.addr <= _T_133 @[nasti.scala 180:13] + _T_134.len <= UInt<1>("h1") @[nasti.scala 181:12] + _T_134.size <= UInt<2>("h3") @[nasti.scala 182:13] + _T_134.burst <= UInt<1>("h1") @[nasti.scala 183:14] + _T_134.lock <= UInt<1>("h0") @[nasti.scala 184:13] + _T_134.cache <= UInt<1>("h0") @[nasti.scala 185:14] + node _T_135 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_136 = cat(_T_135, UInt<1>("h0")) @[Cat.scala 30:58] + _T_134.prot <= _T_136 @[nasti.scala 186:13] + _T_134.qos <= UInt<1>("h0") @[nasti.scala 187:12] + _T_134.region <= UInt<1>("h0") @[nasti.scala 188:15] + _T_134.user <= UInt<1>("h0") @[nasti.scala 189:13] + io.nasti.ar.bits.user <= _T_134.user @[Cache.scala 129:20] + io.nasti.ar.bits.id <= _T_134.id @[Cache.scala 129:20] + io.nasti.ar.bits.region <= _T_134.region @[Cache.scala 129:20] + io.nasti.ar.bits.qos <= _T_134.qos @[Cache.scala 129:20] + io.nasti.ar.bits.prot <= _T_134.prot @[Cache.scala 129:20] + io.nasti.ar.bits.cache <= _T_134.cache @[Cache.scala 129:20] + io.nasti.ar.bits.lock <= _T_134.lock @[Cache.scala 129:20] + io.nasti.ar.bits.burst <= _T_134.burst @[Cache.scala 129:20] + io.nasti.ar.bits.size <= _T_134.size @[Cache.scala 129:20] + io.nasti.ar.bits.len <= _T_134.len @[Cache.scala 129:20] + io.nasti.ar.bits.addr <= _T_134.addr @[Cache.scala 129:20] + io.nasti.ar.valid <= UInt<1>("h0") @[Cache.scala 131:21] + node _T_137 = eq(state, UInt<3>("h6")) @[Cache.scala 133:29] + io.nasti.r.ready <= _T_137 @[Cache.scala 133:20] + node _T_138 = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 40:37] + when _T_138 : @[Cache.scala 134:27] + refill_buf[read_count] <= io.nasti.r.bits.data @[Cache.scala 134:52] + node _T_139 = cat(rmeta.tag, idx_reg) @[Cat.scala 30:58] + node _T_140 = dshl(_T_139, UInt<3>("h4")) @[Cache.scala 138:35] + wire _T_141 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} @[nasti.scala 158:18] + _T_141 is invalid @[nasti.scala 158:18] + _T_141.id <= UInt<1>("h0") @[nasti.scala 159:11] + _T_141.addr <= _T_140 @[nasti.scala 160:13] + _T_141.len <= UInt<1>("h1") @[nasti.scala 161:12] + _T_141.size <= UInt<2>("h3") @[nasti.scala 162:13] + _T_141.burst <= UInt<1>("h1") @[nasti.scala 163:14] + _T_141.lock <= UInt<1>("h0") @[nasti.scala 164:13] + _T_141.cache <= UInt<1>("h0") @[nasti.scala 165:14] + node _T_142 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_143 = cat(_T_142, UInt<1>("h0")) @[Cat.scala 30:58] + _T_141.prot <= _T_143 @[nasti.scala 166:13] + _T_141.qos <= UInt<1>("h0") @[nasti.scala 167:12] + _T_141.region <= UInt<1>("h0") @[nasti.scala 168:15] + _T_141.user <= UInt<1>("h0") @[nasti.scala 169:13] + io.nasti.aw.bits.user <= _T_141.user @[Cache.scala 137:20] + io.nasti.aw.bits.id <= _T_141.id @[Cache.scala 137:20] + io.nasti.aw.bits.region <= _T_141.region @[Cache.scala 137:20] + io.nasti.aw.bits.qos <= _T_141.qos @[Cache.scala 137:20] + io.nasti.aw.bits.prot <= _T_141.prot @[Cache.scala 137:20] + io.nasti.aw.bits.cache <= _T_141.cache @[Cache.scala 137:20] + io.nasti.aw.bits.lock <= _T_141.lock @[Cache.scala 137:20] + io.nasti.aw.bits.burst <= _T_141.burst @[Cache.scala 137:20] + io.nasti.aw.bits.size <= _T_141.size @[Cache.scala 137:20] + io.nasti.aw.bits.len <= _T_141.len @[Cache.scala 137:20] + io.nasti.aw.bits.addr <= _T_141.addr @[Cache.scala 137:20] + io.nasti.aw.valid <= UInt<1>("h0") @[Cache.scala 139:21] + node _T_144 = bits(read, 63, 0) @[Cache.scala 142:42] + node _T_145 = bits(read, 127, 64) @[Cache.scala 142:42] + wire _T_146 : UInt<64>[2] @[Cache.scala 142:32] + _T_146[0] <= _T_144 @[Cache.scala 142:32] + _T_146[1] <= _T_145 @[Cache.scala 142:32] + wire _T_147 : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>} @[nasti.scala 198:17] + _T_147 is invalid @[nasti.scala 198:17] + node _T_148 = mux(UInt<1>("h1"), UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12] + _T_147.strb <= _T_148 @[nasti.scala 199:12] + _T_147.data <= _T_146[write_count] @[nasti.scala 200:12] + _T_147.last <= write_wrap_out @[nasti.scala 201:12] + _T_147.id <= UInt<1>("h0") @[nasti.scala 202:12] + _T_147.user <= UInt<1>("h0") @[nasti.scala 203:12] + io.nasti.w.bits.user <= _T_147.user @[Cache.scala 141:19] + io.nasti.w.bits.strb <= _T_147.strb @[Cache.scala 141:19] + io.nasti.w.bits.id <= _T_147.id @[Cache.scala 141:19] + io.nasti.w.bits.last <= _T_147.last @[Cache.scala 141:19] + io.nasti.w.bits.data <= _T_147.data @[Cache.scala 141:19] + io.nasti.w.valid <= UInt<1>("h0") @[Cache.scala 144:20] + io.nasti.b.ready <= UInt<1>("h0") @[Cache.scala 146:20] + node _T_149 = dshr(v, idx_reg) @[Cache.scala 149:19] + node _T_150 = bits(_T_149, 0, 0) @[Cache.scala 149:19] + node _T_151 = dshr(d, idx_reg) @[Cache.scala 149:33] + node _T_152 = bits(_T_151, 0, 0) @[Cache.scala 149:33] + node is_dirty = and(_T_150, _T_152) @[Cache.scala 149:29] + node _T_153 = eq(UInt<3>("h0"), state) @[Conditional.scala 37:30] + when _T_153 : @[Conditional.scala 40:58] + when io.cpu.req.valid : @[Cache.scala 152:30] + node _T_154 = orr(io.cpu.req.bits.mask) @[Cache.scala 153:43] + node _T_155 = mux(_T_154, UInt<3>("h2"), UInt<3>("h1")) @[Cache.scala 153:21] + state <= _T_155 @[Cache.scala 153:15] + else : + node _T_156 = eq(UInt<3>("h1"), state) @[Conditional.scala 37:30] + when _T_156 : @[Conditional.scala 39:67] + when hit : @[Cache.scala 157:17] + when io.cpu.req.valid : @[Cache.scala 158:32] + node _T_157 = orr(io.cpu.req.bits.mask) @[Cache.scala 159:45] + node _T_158 = mux(_T_157, UInt<3>("h2"), UInt<3>("h1")) @[Cache.scala 159:23] + state <= _T_158 @[Cache.scala 159:17] + else : + state <= UInt<3>("h0") @[Cache.scala 161:17] + else : + io.nasti.aw.valid <= is_dirty @[Cache.scala 164:27] + node _T_159 = eq(is_dirty, UInt<1>("h0")) @[Cache.scala 165:30] + io.nasti.ar.valid <= _T_159 @[Cache.scala 165:27] + node _T_160 = and(io.nasti.aw.ready, io.nasti.aw.valid) @[Decoupled.scala 40:37] + when _T_160 : @[Cache.scala 166:34] + state <= UInt<3>("h3") @[Cache.scala 167:17] + else : + node _T_161 = and(io.nasti.ar.ready, io.nasti.ar.valid) @[Decoupled.scala 40:37] + when _T_161 : @[Cache.scala 168:40] + state <= UInt<3>("h6") @[Cache.scala 169:17] + else : + node _T_162 = eq(UInt<3>("h2"), state) @[Conditional.scala 37:30] + when _T_162 : @[Conditional.scala 39:67] + node _T_163 = or(hit, is_alloc_reg) @[Cache.scala 174:16] + node _T_164 = or(_T_163, io.cpu.abort) @[Cache.scala 174:32] + when _T_164 : @[Cache.scala 174:49] + state <= UInt<3>("h0") @[Cache.scala 175:15] + else : + io.nasti.aw.valid <= is_dirty @[Cache.scala 177:27] + node _T_165 = eq(is_dirty, UInt<1>("h0")) @[Cache.scala 178:30] + io.nasti.ar.valid <= _T_165 @[Cache.scala 178:27] + node _T_166 = and(io.nasti.aw.ready, io.nasti.aw.valid) @[Decoupled.scala 40:37] + when _T_166 : @[Cache.scala 179:34] + state <= UInt<3>("h3") @[Cache.scala 180:17] + else : + node _T_167 = and(io.nasti.ar.ready, io.nasti.ar.valid) @[Decoupled.scala 40:37] + when _T_167 : @[Cache.scala 181:40] + state <= UInt<3>("h6") @[Cache.scala 182:17] + else : + node _T_168 = eq(UInt<3>("h3"), state) @[Conditional.scala 37:30] + when _T_168 : @[Conditional.scala 39:67] + io.nasti.w.valid <= UInt<1>("h1") @[Cache.scala 187:24] + when write_wrap_out : @[Cache.scala 188:28] + state <= UInt<3>("h4") @[Cache.scala 189:15] + else : + node _T_169 = eq(UInt<3>("h4"), state) @[Conditional.scala 37:30] + when _T_169 : @[Conditional.scala 39:67] + io.nasti.b.ready <= UInt<1>("h1") @[Cache.scala 193:24] + node _T_170 = and(io.nasti.b.ready, io.nasti.b.valid) @[Decoupled.scala 40:37] + when _T_170 : @[Cache.scala 194:31] + state <= UInt<3>("h5") @[Cache.scala 195:15] + else : + node _T_171 = eq(UInt<3>("h5"), state) @[Conditional.scala 37:30] + when _T_171 : @[Conditional.scala 39:67] + io.nasti.ar.valid <= UInt<1>("h1") @[Cache.scala 199:25] + node _T_172 = and(io.nasti.ar.ready, io.nasti.ar.valid) @[Decoupled.scala 40:37] + when _T_172 : @[Cache.scala 200:32] + state <= UInt<3>("h6") @[Cache.scala 201:15] + else : + node _T_173 = eq(UInt<3>("h6"), state) @[Conditional.scala 37:30] + when _T_173 : @[Conditional.scala 39:67] + when read_wrap_out : @[Cache.scala 205:27] + node _T_174 = orr(cpu_mask) @[Cache.scala 206:31] + node _T_175 = mux(_T_174, UInt<3>("h2"), UInt<3>("h0")) @[Cache.scala 206:21] + state <= _T_175 @[Cache.scala 206:15] + + module MemArbiter : + input clock : Clock + input reset : Reset + output io : { flip icache : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dcache : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, nasti : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} + + reg state : UInt<3>, clock with : + reset => (reset, UInt<3>("h0")) @[Tile.scala 21:22] + io.nasti.aw.bits.user <= io.dcache.aw.bits.user @[Tile.scala 24:20] + io.nasti.aw.bits.id <= io.dcache.aw.bits.id @[Tile.scala 24:20] + io.nasti.aw.bits.region <= io.dcache.aw.bits.region @[Tile.scala 24:20] + io.nasti.aw.bits.qos <= io.dcache.aw.bits.qos @[Tile.scala 24:20] + io.nasti.aw.bits.prot <= io.dcache.aw.bits.prot @[Tile.scala 24:20] + io.nasti.aw.bits.cache <= io.dcache.aw.bits.cache @[Tile.scala 24:20] + io.nasti.aw.bits.lock <= io.dcache.aw.bits.lock @[Tile.scala 24:20] + io.nasti.aw.bits.burst <= io.dcache.aw.bits.burst @[Tile.scala 24:20] + io.nasti.aw.bits.size <= io.dcache.aw.bits.size @[Tile.scala 24:20] + io.nasti.aw.bits.len <= io.dcache.aw.bits.len @[Tile.scala 24:20] + io.nasti.aw.bits.addr <= io.dcache.aw.bits.addr @[Tile.scala 24:20] + node _T = eq(state, UInt<3>("h0")) @[Tile.scala 25:52] + node _T_1 = and(io.dcache.aw.valid, _T) @[Tile.scala 25:43] + io.nasti.aw.valid <= _T_1 @[Tile.scala 25:21] + node _T_2 = eq(state, UInt<3>("h0")) @[Tile.scala 26:52] + node _T_3 = and(io.nasti.aw.ready, _T_2) @[Tile.scala 26:43] + io.dcache.aw.ready <= _T_3 @[Tile.scala 26:22] + io.icache.aw.bits.user is invalid @[Tile.scala 27:16] + io.icache.aw.bits.id is invalid @[Tile.scala 27:16] + io.icache.aw.bits.region is invalid @[Tile.scala 27:16] + io.icache.aw.bits.qos is invalid @[Tile.scala 27:16] + io.icache.aw.bits.prot is invalid @[Tile.scala 27:16] + io.icache.aw.bits.cache is invalid @[Tile.scala 27:16] + io.icache.aw.bits.lock is invalid @[Tile.scala 27:16] + io.icache.aw.bits.burst is invalid @[Tile.scala 27:16] + io.icache.aw.bits.size is invalid @[Tile.scala 27:16] + io.icache.aw.bits.len is invalid @[Tile.scala 27:16] + io.icache.aw.bits.addr is invalid @[Tile.scala 27:16] + io.icache.aw.valid is invalid @[Tile.scala 27:16] + io.icache.aw.ready is invalid @[Tile.scala 27:16] + io.nasti.w.bits.user <= io.dcache.w.bits.user @[Tile.scala 30:20] + io.nasti.w.bits.strb <= io.dcache.w.bits.strb @[Tile.scala 30:20] + io.nasti.w.bits.id <= io.dcache.w.bits.id @[Tile.scala 30:20] + io.nasti.w.bits.last <= io.dcache.w.bits.last @[Tile.scala 30:20] + io.nasti.w.bits.data <= io.dcache.w.bits.data @[Tile.scala 30:20] + node _T_4 = eq(state, UInt<3>("h3")) @[Tile.scala 31:50] + node _T_5 = and(io.dcache.w.valid, _T_4) @[Tile.scala 31:41] + io.nasti.w.valid <= _T_5 @[Tile.scala 31:20] + node _T_6 = eq(state, UInt<3>("h3")) @[Tile.scala 32:50] + node _T_7 = and(io.nasti.w.ready, _T_6) @[Tile.scala 32:41] + io.dcache.w.ready <= _T_7 @[Tile.scala 32:21] + io.icache.w.bits.user is invalid @[Tile.scala 33:15] + io.icache.w.bits.strb is invalid @[Tile.scala 33:15] + io.icache.w.bits.id is invalid @[Tile.scala 33:15] + io.icache.w.bits.last is invalid @[Tile.scala 33:15] + io.icache.w.bits.data is invalid @[Tile.scala 33:15] + io.icache.w.valid is invalid @[Tile.scala 33:15] + io.icache.w.ready is invalid @[Tile.scala 33:15] + io.dcache.b.bits.user <= io.nasti.b.bits.user @[Tile.scala 36:20] + io.dcache.b.bits.id <= io.nasti.b.bits.id @[Tile.scala 36:20] + io.dcache.b.bits.resp <= io.nasti.b.bits.resp @[Tile.scala 36:20] + node _T_8 = eq(state, UInt<3>("h4")) @[Tile.scala 37:50] + node _T_9 = and(io.nasti.b.valid, _T_8) @[Tile.scala 37:41] + io.dcache.b.valid <= _T_9 @[Tile.scala 37:21] + node _T_10 = eq(state, UInt<3>("h4")) @[Tile.scala 38:50] + node _T_11 = and(io.dcache.b.ready, _T_10) @[Tile.scala 38:41] + io.nasti.b.ready <= _T_11 @[Tile.scala 38:20] + io.icache.b.bits.user is invalid @[Tile.scala 39:15] + io.icache.b.bits.id is invalid @[Tile.scala 39:15] + io.icache.b.bits.resp is invalid @[Tile.scala 39:15] + io.icache.b.valid is invalid @[Tile.scala 39:15] + io.icache.b.ready is invalid @[Tile.scala 39:15] + node _T_12 = mux(io.dcache.ar.valid, io.dcache.ar.bits.id, io.icache.ar.bits.id) @[Tile.scala 43:8] + node _T_13 = mux(io.dcache.ar.valid, io.dcache.ar.bits.addr, io.icache.ar.bits.addr) @[Tile.scala 44:8] + node _T_14 = mux(io.dcache.ar.valid, io.dcache.ar.bits.size, io.icache.ar.bits.size) @[Tile.scala 45:8] + node _T_15 = mux(io.dcache.ar.valid, io.dcache.ar.bits.len, io.icache.ar.bits.len) @[Tile.scala 46:8] + wire _T_16 : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} @[nasti.scala 178:18] + _T_16 is invalid @[nasti.scala 178:18] + _T_16.id <= _T_12 @[nasti.scala 179:11] + _T_16.addr <= _T_13 @[nasti.scala 180:13] + _T_16.len <= _T_15 @[nasti.scala 181:12] + _T_16.size <= _T_14 @[nasti.scala 182:13] + _T_16.burst <= UInt<1>("h1") @[nasti.scala 183:14] + _T_16.lock <= UInt<1>("h0") @[nasti.scala 184:13] + _T_16.cache <= UInt<1>("h0") @[nasti.scala 185:14] + node _T_17 = cat(UInt<1>("h0"), UInt<1>("h0")) @[Cat.scala 30:58] + node _T_18 = cat(_T_17, UInt<1>("h0")) @[Cat.scala 30:58] + _T_16.prot <= _T_18 @[nasti.scala 186:13] + _T_16.qos <= UInt<1>("h0") @[nasti.scala 187:12] + _T_16.region <= UInt<1>("h0") @[nasti.scala 188:15] + _T_16.user <= UInt<1>("h0") @[nasti.scala 189:13] + io.nasti.ar.bits.user <= _T_16.user @[Tile.scala 42:20] + io.nasti.ar.bits.id <= _T_16.id @[Tile.scala 42:20] + io.nasti.ar.bits.region <= _T_16.region @[Tile.scala 42:20] + io.nasti.ar.bits.qos <= _T_16.qos @[Tile.scala 42:20] + io.nasti.ar.bits.prot <= _T_16.prot @[Tile.scala 42:20] + io.nasti.ar.bits.cache <= _T_16.cache @[Tile.scala 42:20] + io.nasti.ar.bits.lock <= _T_16.lock @[Tile.scala 42:20] + io.nasti.ar.bits.burst <= _T_16.burst @[Tile.scala 42:20] + io.nasti.ar.bits.size <= _T_16.size @[Tile.scala 42:20] + io.nasti.ar.bits.len <= _T_16.len @[Tile.scala 42:20] + io.nasti.ar.bits.addr <= _T_16.addr @[Tile.scala 42:20] + node _T_19 = or(io.icache.ar.valid, io.dcache.ar.valid) @[Tile.scala 47:44] + node _T_20 = eq(io.nasti.aw.valid, UInt<1>("h0")) @[Tile.scala 48:5] + node _T_21 = and(_T_19, _T_20) @[Tile.scala 47:67] + node _T_22 = eq(state, UInt<3>("h0")) @[Tile.scala 48:33] + node _T_23 = and(_T_21, _T_22) @[Tile.scala 48:24] + io.nasti.ar.valid <= _T_23 @[Tile.scala 47:21] + node _T_24 = eq(io.nasti.aw.valid, UInt<1>("h0")) @[Tile.scala 49:46] + node _T_25 = and(io.nasti.ar.ready, _T_24) @[Tile.scala 49:43] + node _T_26 = eq(state, UInt<3>("h0")) @[Tile.scala 49:74] + node _T_27 = and(_T_25, _T_26) @[Tile.scala 49:65] + io.dcache.ar.ready <= _T_27 @[Tile.scala 49:22] + node _T_28 = eq(io.dcache.ar.valid, UInt<1>("h0")) @[Tile.scala 50:47] + node _T_29 = and(io.dcache.ar.ready, _T_28) @[Tile.scala 50:44] + io.icache.ar.ready <= _T_29 @[Tile.scala 50:22] + io.icache.r.bits.user <= io.nasti.r.bits.user @[Tile.scala 53:21] + io.icache.r.bits.id <= io.nasti.r.bits.id @[Tile.scala 53:21] + io.icache.r.bits.last <= io.nasti.r.bits.last @[Tile.scala 53:21] + io.icache.r.bits.data <= io.nasti.r.bits.data @[Tile.scala 53:21] + io.icache.r.bits.resp <= io.nasti.r.bits.resp @[Tile.scala 53:21] + io.dcache.r.bits.user <= io.nasti.r.bits.user @[Tile.scala 54:21] + io.dcache.r.bits.id <= io.nasti.r.bits.id @[Tile.scala 54:21] + io.dcache.r.bits.last <= io.nasti.r.bits.last @[Tile.scala 54:21] + io.dcache.r.bits.data <= io.nasti.r.bits.data @[Tile.scala 54:21] + io.dcache.r.bits.resp <= io.nasti.r.bits.resp @[Tile.scala 54:21] + node _T_30 = eq(state, UInt<3>("h1")) @[Tile.scala 55:50] + node _T_31 = and(io.nasti.r.valid, _T_30) @[Tile.scala 55:41] + io.icache.r.valid <= _T_31 @[Tile.scala 55:21] + node _T_32 = eq(state, UInt<3>("h2")) @[Tile.scala 56:50] + node _T_33 = and(io.nasti.r.valid, _T_32) @[Tile.scala 56:41] + io.dcache.r.valid <= _T_33 @[Tile.scala 56:21] + node _T_34 = eq(state, UInt<3>("h1")) @[Tile.scala 57:50] + node _T_35 = and(io.icache.r.ready, _T_34) @[Tile.scala 57:41] + node _T_36 = eq(state, UInt<3>("h2")) @[Tile.scala 58:50] + node _T_37 = and(io.dcache.r.ready, _T_36) @[Tile.scala 58:41] + node _T_38 = or(_T_35, _T_37) @[Tile.scala 57:68] + io.nasti.r.ready <= _T_38 @[Tile.scala 57:20] + node _T_39 = eq(UInt<3>("h0"), state) @[Conditional.scala 37:30] + when _T_39 : @[Conditional.scala 40:58] + node _T_40 = and(io.dcache.aw.ready, io.dcache.aw.valid) @[Decoupled.scala 40:37] + when _T_40 : @[Tile.scala 62:33] + state <= UInt<3>("h3") @[Tile.scala 63:15] + else : + node _T_41 = and(io.dcache.ar.ready, io.dcache.ar.valid) @[Decoupled.scala 40:37] + when _T_41 : @[Tile.scala 64:39] + state <= UInt<3>("h2") @[Tile.scala 65:15] + else : + node _T_42 = and(io.icache.ar.ready, io.icache.ar.valid) @[Decoupled.scala 40:37] + when _T_42 : @[Tile.scala 66:39] + state <= UInt<3>("h1") @[Tile.scala 67:15] + else : + node _T_43 = eq(UInt<3>("h1"), state) @[Conditional.scala 37:30] + when _T_43 : @[Conditional.scala 39:67] + node _T_44 = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 40:37] + node _T_45 = and(_T_44, io.nasti.r.bits.last) @[Tile.scala 71:30] + when _T_45 : @[Tile.scala 71:55] + state <= UInt<3>("h0") @[Tile.scala 72:15] + else : + node _T_46 = eq(UInt<3>("h2"), state) @[Conditional.scala 37:30] + when _T_46 : @[Conditional.scala 39:67] + node _T_47 = and(io.nasti.r.ready, io.nasti.r.valid) @[Decoupled.scala 40:37] + node _T_48 = and(_T_47, io.nasti.r.bits.last) @[Tile.scala 76:30] + when _T_48 : @[Tile.scala 76:55] + state <= UInt<3>("h0") @[Tile.scala 77:15] + else : + node _T_49 = eq(UInt<3>("h3"), state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 39:67] + node _T_50 = and(io.dcache.w.ready, io.dcache.w.valid) @[Decoupled.scala 40:37] + node _T_51 = and(_T_50, io.dcache.w.bits.last) @[Tile.scala 81:31] + when _T_51 : @[Tile.scala 81:57] + state <= UInt<3>("h4") @[Tile.scala 82:15] + else : + node _T_52 = eq(UInt<3>("h4"), state) @[Conditional.scala 37:30] + when _T_52 : @[Conditional.scala 39:67] + node _T_53 = and(io.nasti.b.ready, io.nasti.b.valid) @[Decoupled.scala 40:37] + when _T_53 : @[Tile.scala 86:31] + state <= UInt<3>("h0") @[Tile.scala 87:15] + + module Tile : + input clock : Clock + input reset : Reset + output io : { host : { flip fromhost : { valid : UInt<1>, bits : UInt<32>}, tohost : UInt<32>}, nasti : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, last : UInt<1>, id : UInt<5>, strb : UInt<8>, user : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} + + inst core of Core @[Tile.scala 107:22] + core.clock <= clock + core.reset <= reset + inst icache of Cache @[Tile.scala 108:22] + icache.clock <= clock + icache.reset <= reset + inst dcache of Cache_1 @[Tile.scala 109:22] + dcache.clock <= clock + dcache.reset <= reset + inst arb of MemArbiter @[Tile.scala 110:22] + arb.clock <= clock + arb.reset <= reset + io.host.tohost <= core.io.host.tohost @[Tile.scala 112:11] + core.io.host.fromhost.bits <= io.host.fromhost.bits @[Tile.scala 112:11] + core.io.host.fromhost.valid <= io.host.fromhost.valid @[Tile.scala 112:11] + core.io.icache.resp.bits.data <= icache.io.cpu.resp.bits.data @[Tile.scala 113:18] + core.io.icache.resp.valid <= icache.io.cpu.resp.valid @[Tile.scala 113:18] + icache.io.cpu.req.bits.mask <= core.io.icache.req.bits.mask @[Tile.scala 113:18] + icache.io.cpu.req.bits.data <= core.io.icache.req.bits.data @[Tile.scala 113:18] + icache.io.cpu.req.bits.addr <= core.io.icache.req.bits.addr @[Tile.scala 113:18] + icache.io.cpu.req.valid <= core.io.icache.req.valid @[Tile.scala 113:18] + icache.io.cpu.abort <= core.io.icache.abort @[Tile.scala 113:18] + core.io.dcache.resp.bits.data <= dcache.io.cpu.resp.bits.data @[Tile.scala 114:18] + core.io.dcache.resp.valid <= dcache.io.cpu.resp.valid @[Tile.scala 114:18] + dcache.io.cpu.req.bits.mask <= core.io.dcache.req.bits.mask @[Tile.scala 114:18] + dcache.io.cpu.req.bits.data <= core.io.dcache.req.bits.data @[Tile.scala 114:18] + dcache.io.cpu.req.bits.addr <= core.io.dcache.req.bits.addr @[Tile.scala 114:18] + dcache.io.cpu.req.valid <= core.io.dcache.req.valid @[Tile.scala 114:18] + dcache.io.cpu.abort <= core.io.dcache.abort @[Tile.scala 114:18] + arb.io.icache <= icache.io.nasti @[Tile.scala 115:17] + arb.io.dcache <= dcache.io.nasti @[Tile.scala 116:17] + io.nasti <= arb.io.nasti @[Tile.scala 117:12] + + module Queue : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_1 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_2 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_3 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_4 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_5 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_6 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_7 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module LatencyPipe : + input clock : Clock + input reset : Reset + output io : { gen : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}}} + + io.out.bits.user is invalid @[TileTester.scala 155:6] + io.out.bits.id is invalid @[TileTester.scala 155:6] + io.out.bits.resp is invalid @[TileTester.scala 155:6] + io.out.valid is invalid @[TileTester.scala 155:6] + io.out.ready is invalid @[TileTester.scala 155:6] + io.in.bits.user is invalid @[TileTester.scala 155:6] + io.in.bits.id is invalid @[TileTester.scala 155:6] + io.in.bits.resp is invalid @[TileTester.scala 155:6] + io.in.valid is invalid @[TileTester.scala 155:6] + io.in.ready is invalid @[TileTester.scala 155:6] + io.gen.user is invalid @[TileTester.scala 155:6] + io.gen.id is invalid @[TileTester.scala 155:6] + io.gen.resp is invalid @[TileTester.scala 155:6] + inst Queue of Queue @[Decoupled.scala 296:21] + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.valid @[Decoupled.scala 297:22] + Queue.io.enq.bits.user <= io.in.bits.user @[Decoupled.scala 298:21] + Queue.io.enq.bits.id <= io.in.bits.id @[Decoupled.scala 298:21] + Queue.io.enq.bits.resp <= io.in.bits.resp @[Decoupled.scala 298:21] + io.in.ready <= Queue.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_1 of Queue_1 @[Decoupled.scala 296:21] + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= Queue.io.deq.valid @[Decoupled.scala 297:22] + Queue_1.io.enq.bits.user <= Queue.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_1.io.enq.bits.id <= Queue.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_1.io.enq.bits.resp <= Queue.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue.io.deq.ready <= Queue_1.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_2 of Queue_2 @[Decoupled.scala 296:21] + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= Queue_1.io.deq.valid @[Decoupled.scala 297:22] + Queue_2.io.enq.bits.user <= Queue_1.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_2.io.enq.bits.id <= Queue_1.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_2.io.enq.bits.resp <= Queue_1.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_1.io.deq.ready <= Queue_2.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_3 of Queue_3 @[Decoupled.scala 296:21] + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= Queue_2.io.deq.valid @[Decoupled.scala 297:22] + Queue_3.io.enq.bits.user <= Queue_2.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_3.io.enq.bits.id <= Queue_2.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_3.io.enq.bits.resp <= Queue_2.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_2.io.deq.ready <= Queue_3.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_4 of Queue_4 @[Decoupled.scala 296:21] + Queue_4.clock <= clock + Queue_4.reset <= reset + Queue_4.io.enq.valid <= Queue_3.io.deq.valid @[Decoupled.scala 297:22] + Queue_4.io.enq.bits.user <= Queue_3.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_4.io.enq.bits.id <= Queue_3.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_4.io.enq.bits.resp <= Queue_3.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_3.io.deq.ready <= Queue_4.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_5 of Queue_5 @[Decoupled.scala 296:21] + Queue_5.clock <= clock + Queue_5.reset <= reset + Queue_5.io.enq.valid <= Queue_4.io.deq.valid @[Decoupled.scala 297:22] + Queue_5.io.enq.bits.user <= Queue_4.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_5.io.enq.bits.id <= Queue_4.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_5.io.enq.bits.resp <= Queue_4.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_4.io.deq.ready <= Queue_5.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_6 of Queue_6 @[Decoupled.scala 296:21] + Queue_6.clock <= clock + Queue_6.reset <= reset + Queue_6.io.enq.valid <= Queue_5.io.deq.valid @[Decoupled.scala 297:22] + Queue_6.io.enq.bits.user <= Queue_5.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_6.io.enq.bits.id <= Queue_5.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_6.io.enq.bits.resp <= Queue_5.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_5.io.deq.ready <= Queue_6.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_7 of Queue_7 @[Decoupled.scala 296:21] + Queue_7.clock <= clock + Queue_7.reset <= reset + Queue_7.io.enq.valid <= Queue_6.io.deq.valid @[Decoupled.scala 297:22] + Queue_7.io.enq.bits.user <= Queue_6.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_7.io.enq.bits.id <= Queue_6.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_7.io.enq.bits.resp <= Queue_6.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_6.io.deq.ready <= Queue_7.io.enq.ready @[Decoupled.scala 299:17] + io.out.bits <= Queue_7.io.deq.bits @[TileTester.scala 156:10] + io.out.valid <= Queue_7.io.deq.valid @[TileTester.scala 156:10] + Queue_7.io.deq.ready <= io.out.ready @[TileTester.scala 156:10] + + module Queue_8 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_9 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_10 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_11 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_12 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_13 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_14 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module Queue_15 : + input clock : Clock + input reset : Reset + output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} + + cmem ram : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} [1] @[Decoupled.scala 218:16] + reg maybe_full : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[Decoupled.scala 221:27] + node ptr_match = eq(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 223:33] + node _T = eq(maybe_full, UInt<1>("h0")) @[Decoupled.scala 224:28] + node empty = and(ptr_match, _T) @[Decoupled.scala 224:25] + node full = and(ptr_match, maybe_full) @[Decoupled.scala 225:24] + node _T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 40:37] + wire do_enq : UInt<1> + do_enq <= _T_1 + node _T_2 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 40:37] + wire do_deq : UInt<1> + do_deq <= _T_2 + when do_enq : @[Decoupled.scala 229:17] + infer mport _T_3 = ram[UInt<1>("h0")], clock @[Decoupled.scala 230:8] + _T_3.user <= io.enq.bits.user @[Decoupled.scala 230:24] + _T_3.id <= io.enq.bits.id @[Decoupled.scala 230:24] + _T_3.last <= io.enq.bits.last @[Decoupled.scala 230:24] + _T_3.data <= io.enq.bits.data @[Decoupled.scala 230:24] + _T_3.resp <= io.enq.bits.resp @[Decoupled.scala 230:24] + when do_deq : @[Decoupled.scala 233:17] + skip + node _T_4 = neq(do_enq, do_deq) @[Decoupled.scala 236:16] + when _T_4 : @[Decoupled.scala 236:28] + maybe_full <= do_enq @[Decoupled.scala 237:16] + node _T_5 = eq(empty, UInt<1>("h0")) @[Decoupled.scala 240:19] + io.deq.valid <= _T_5 @[Decoupled.scala 240:16] + node _T_6 = eq(full, UInt<1>("h0")) @[Decoupled.scala 241:19] + io.enq.ready <= _T_6 @[Decoupled.scala 241:16] + infer mport _T_7 = ram[UInt<1>("h0")], clock @[Decoupled.scala 242:21] + io.deq.bits.user <= _T_7.user @[Decoupled.scala 242:15] + io.deq.bits.id <= _T_7.id @[Decoupled.scala 242:15] + io.deq.bits.last <= _T_7.last @[Decoupled.scala 242:15] + io.deq.bits.data <= _T_7.data @[Decoupled.scala 242:15] + io.deq.bits.resp <= _T_7.resp @[Decoupled.scala 242:15] + when io.deq.ready : @[Decoupled.scala 254:25] + io.enq.ready <= UInt<1>("h1") @[Decoupled.scala 254:40] + node _T_8 = sub(UInt<1>("h0"), UInt<1>("h0")) @[Decoupled.scala 257:32] + node ptr_diff = tail(_T_8, 1) @[Decoupled.scala 257:32] + node _T_9 = and(maybe_full, ptr_match) @[Decoupled.scala 259:32] + node _T_10 = mux(_T_9, UInt<1>("h1"), UInt<1>("h0")) @[Decoupled.scala 259:20] + node _T_11 = or(_T_10, ptr_diff) @[Decoupled.scala 259:62] + io.count <= _T_11 @[Decoupled.scala 259:14] + + module LatencyPipe_1 : + input clock : Clock + input reset : Reset + output io : { gen : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} + + io.out.bits.user is invalid @[TileTester.scala 155:6] + io.out.bits.id is invalid @[TileTester.scala 155:6] + io.out.bits.last is invalid @[TileTester.scala 155:6] + io.out.bits.data is invalid @[TileTester.scala 155:6] + io.out.bits.resp is invalid @[TileTester.scala 155:6] + io.out.valid is invalid @[TileTester.scala 155:6] + io.out.ready is invalid @[TileTester.scala 155:6] + io.in.bits.user is invalid @[TileTester.scala 155:6] + io.in.bits.id is invalid @[TileTester.scala 155:6] + io.in.bits.last is invalid @[TileTester.scala 155:6] + io.in.bits.data is invalid @[TileTester.scala 155:6] + io.in.bits.resp is invalid @[TileTester.scala 155:6] + io.in.valid is invalid @[TileTester.scala 155:6] + io.in.ready is invalid @[TileTester.scala 155:6] + io.gen.user is invalid @[TileTester.scala 155:6] + io.gen.id is invalid @[TileTester.scala 155:6] + io.gen.last is invalid @[TileTester.scala 155:6] + io.gen.data is invalid @[TileTester.scala 155:6] + io.gen.resp is invalid @[TileTester.scala 155:6] + inst Queue of Queue_8 @[Decoupled.scala 296:21] + Queue.clock <= clock + Queue.reset <= reset + Queue.io.enq.valid <= io.in.valid @[Decoupled.scala 297:22] + Queue.io.enq.bits.user <= io.in.bits.user @[Decoupled.scala 298:21] + Queue.io.enq.bits.id <= io.in.bits.id @[Decoupled.scala 298:21] + Queue.io.enq.bits.last <= io.in.bits.last @[Decoupled.scala 298:21] + Queue.io.enq.bits.data <= io.in.bits.data @[Decoupled.scala 298:21] + Queue.io.enq.bits.resp <= io.in.bits.resp @[Decoupled.scala 298:21] + io.in.ready <= Queue.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_1 of Queue_9 @[Decoupled.scala 296:21] + Queue_1.clock <= clock + Queue_1.reset <= reset + Queue_1.io.enq.valid <= Queue.io.deq.valid @[Decoupled.scala 297:22] + Queue_1.io.enq.bits.user <= Queue.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_1.io.enq.bits.id <= Queue.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_1.io.enq.bits.last <= Queue.io.deq.bits.last @[Decoupled.scala 298:21] + Queue_1.io.enq.bits.data <= Queue.io.deq.bits.data @[Decoupled.scala 298:21] + Queue_1.io.enq.bits.resp <= Queue.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue.io.deq.ready <= Queue_1.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_2 of Queue_10 @[Decoupled.scala 296:21] + Queue_2.clock <= clock + Queue_2.reset <= reset + Queue_2.io.enq.valid <= Queue_1.io.deq.valid @[Decoupled.scala 297:22] + Queue_2.io.enq.bits.user <= Queue_1.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_2.io.enq.bits.id <= Queue_1.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_2.io.enq.bits.last <= Queue_1.io.deq.bits.last @[Decoupled.scala 298:21] + Queue_2.io.enq.bits.data <= Queue_1.io.deq.bits.data @[Decoupled.scala 298:21] + Queue_2.io.enq.bits.resp <= Queue_1.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_1.io.deq.ready <= Queue_2.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_3 of Queue_11 @[Decoupled.scala 296:21] + Queue_3.clock <= clock + Queue_3.reset <= reset + Queue_3.io.enq.valid <= Queue_2.io.deq.valid @[Decoupled.scala 297:22] + Queue_3.io.enq.bits.user <= Queue_2.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_3.io.enq.bits.id <= Queue_2.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_3.io.enq.bits.last <= Queue_2.io.deq.bits.last @[Decoupled.scala 298:21] + Queue_3.io.enq.bits.data <= Queue_2.io.deq.bits.data @[Decoupled.scala 298:21] + Queue_3.io.enq.bits.resp <= Queue_2.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_2.io.deq.ready <= Queue_3.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_4 of Queue_12 @[Decoupled.scala 296:21] + Queue_4.clock <= clock + Queue_4.reset <= reset + Queue_4.io.enq.valid <= Queue_3.io.deq.valid @[Decoupled.scala 297:22] + Queue_4.io.enq.bits.user <= Queue_3.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_4.io.enq.bits.id <= Queue_3.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_4.io.enq.bits.last <= Queue_3.io.deq.bits.last @[Decoupled.scala 298:21] + Queue_4.io.enq.bits.data <= Queue_3.io.deq.bits.data @[Decoupled.scala 298:21] + Queue_4.io.enq.bits.resp <= Queue_3.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_3.io.deq.ready <= Queue_4.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_5 of Queue_13 @[Decoupled.scala 296:21] + Queue_5.clock <= clock + Queue_5.reset <= reset + Queue_5.io.enq.valid <= Queue_4.io.deq.valid @[Decoupled.scala 297:22] + Queue_5.io.enq.bits.user <= Queue_4.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_5.io.enq.bits.id <= Queue_4.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_5.io.enq.bits.last <= Queue_4.io.deq.bits.last @[Decoupled.scala 298:21] + Queue_5.io.enq.bits.data <= Queue_4.io.deq.bits.data @[Decoupled.scala 298:21] + Queue_5.io.enq.bits.resp <= Queue_4.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_4.io.deq.ready <= Queue_5.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_6 of Queue_14 @[Decoupled.scala 296:21] + Queue_6.clock <= clock + Queue_6.reset <= reset + Queue_6.io.enq.valid <= Queue_5.io.deq.valid @[Decoupled.scala 297:22] + Queue_6.io.enq.bits.user <= Queue_5.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_6.io.enq.bits.id <= Queue_5.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_6.io.enq.bits.last <= Queue_5.io.deq.bits.last @[Decoupled.scala 298:21] + Queue_6.io.enq.bits.data <= Queue_5.io.deq.bits.data @[Decoupled.scala 298:21] + Queue_6.io.enq.bits.resp <= Queue_5.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_5.io.deq.ready <= Queue_6.io.enq.ready @[Decoupled.scala 299:17] + inst Queue_7 of Queue_15 @[Decoupled.scala 296:21] + Queue_7.clock <= clock + Queue_7.reset <= reset + Queue_7.io.enq.valid <= Queue_6.io.deq.valid @[Decoupled.scala 297:22] + Queue_7.io.enq.bits.user <= Queue_6.io.deq.bits.user @[Decoupled.scala 298:21] + Queue_7.io.enq.bits.id <= Queue_6.io.deq.bits.id @[Decoupled.scala 298:21] + Queue_7.io.enq.bits.last <= Queue_6.io.deq.bits.last @[Decoupled.scala 298:21] + Queue_7.io.enq.bits.data <= Queue_6.io.deq.bits.data @[Decoupled.scala 298:21] + Queue_7.io.enq.bits.resp <= Queue_6.io.deq.bits.resp @[Decoupled.scala 298:21] + Queue_6.io.deq.ready <= Queue_7.io.enq.ready @[Decoupled.scala 299:17] + io.out.bits <= Queue_7.io.deq.bits @[TileTester.scala 156:10] + io.out.valid <= Queue_7.io.deq.valid @[TileTester.scala 156:10] + Queue_7.io.deq.ready <= io.out.ready @[TileTester.scala 156:10] + + module TileTester : + input clock : Clock + input reset : UInt<1> + output io : { } + + inst dut of Tile @[TileTester.scala 32:19] + dut.clock <= clock + dut.reset <= reset + dut.io.host.fromhost.bits <= UInt<1>("h0") @[TileTester.scala 41:29] + dut.io.host.fromhost.valid <= UInt<1>("h0") @[TileTester.scala 42:30] + node _T = cat(UInt<64>("h0"), UInt<64>("h10101464c457f")) @[Cat.scala 30:58] + node _T_1 = cat(UInt<64>("h3400000100"), UInt<64>("h100f30002")) @[Cat.scala 30:58] + node _T_2 = cat(_T_1, _T) @[Cat.scala 30:58] + node _T_3 = cat(UInt<64>("h28000200200034"), UInt<64>("hb8d4")) @[Cat.scala 30:58] + node _T_4 = cat(UInt<64>("h0"), UInt<64>("h100120015")) @[Cat.scala 30:58] + node _T_5 = cat(_T_4, _T_3) @[Cat.scala 30:58] + node _T_6 = cat(_T_5, _T_2) @[Cat.scala 30:58] + node _T_7 = cat(UInt<64>("h700006010"), UInt<64>("h5f7c00000000")) @[Cat.scala 30:58] + node _T_8 = cat(UInt<64>("h604000005f80"), UInt<64>("h700001000")) @[Cat.scala 30:58] + node _T_9 = cat(_T_8, _T_7) @[Cat.scala 30:58] + node _T_10 = cat(UInt<64>("h400000044"), UInt<64>("h6040")) @[Cat.scala 30:58] + node _T_11 = cat(UInt<64>("h0"), UInt<64>("h40")) @[Cat.scala 30:58] + node _T_12 = cat(_T_11, _T_10) @[Cat.scala 30:58] + node _T_13 = cat(_T_12, _T_9) @[Cat.scala 30:58] + node _T_14 = cat(_T_13, _T_6) @[Cat.scala 30:58] + node _T_15 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_16 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_17 = cat(_T_16, _T_15) @[Cat.scala 30:58] + node _T_18 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_19 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_20 = cat(_T_19, _T_18) @[Cat.scala 30:58] + node _T_21 = cat(_T_20, _T_17) @[Cat.scala 30:58] + node _T_22 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_23 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_24 = cat(_T_23, _T_22) @[Cat.scala 30:58] + node _T_25 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_26 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_27 = cat(_T_26, _T_25) @[Cat.scala 30:58] + node _T_28 = cat(_T_27, _T_24) @[Cat.scala 30:58] + node _T_29 = cat(_T_28, _T_21) @[Cat.scala 30:58] + node _T_30 = cat(_T_29, _T_14) @[Cat.scala 30:58] + node _T_31 = cat(UInt<64>("h1300000013"), UInt<64>("h132840006f")) @[Cat.scala 30:58] + node _T_32 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_33 = cat(_T_32, _T_31) @[Cat.scala 30:58] + node _T_34 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_35 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_36 = cat(_T_35, _T_34) @[Cat.scala 30:58] + node _T_37 = cat(_T_36, _T_33) @[Cat.scala 30:58] + node _T_38 = cat(UInt<64>("h1300000013"), UInt<64>("h130000006f")) @[Cat.scala 30:58] + node _T_39 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_40 = cat(_T_39, _T_38) @[Cat.scala 30:58] + node _T_41 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_42 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_43 = cat(_T_42, _T_41) @[Cat.scala 30:58] + node _T_44 = cat(_T_43, _T_40) @[Cat.scala 30:58] + node _T_45 = cat(_T_44, _T_37) @[Cat.scala 30:58] + node _T_46 = cat(UInt<64>("h1300000013"), UInt<64>("h130000006f")) @[Cat.scala 30:58] + node _T_47 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_48 = cat(_T_47, _T_46) @[Cat.scala 30:58] + node _T_49 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_50 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_51 = cat(_T_50, _T_49) @[Cat.scala 30:58] + node _T_52 = cat(_T_51, _T_48) @[Cat.scala 30:58] + node _T_53 = cat(UInt<64>("h1300000013"), UInt<64>("h131c40006f")) @[Cat.scala 30:58] + node _T_54 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_55 = cat(_T_54, _T_53) @[Cat.scala 30:58] + node _T_56 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_57 = cat(UInt<64>("h1300000013"), UInt<64>("h1300000013")) @[Cat.scala 30:58] + node _T_58 = cat(_T_57, _T_56) @[Cat.scala 30:58] + node _T_59 = cat(_T_58, _T_55) @[Cat.scala 30:58] + node _T_60 = cat(_T_59, _T_52) @[Cat.scala 30:58] + node _T_61 = cat(_T_60, _T_45) @[Cat.scala 30:58] + node _T_62 = cat(_T_61, _T_30) @[Cat.scala 30:58] + node _T_63 = cat(UInt<64>("h21300000193"), UInt<64>("h11300000093")) @[Cat.scala 30:58] + node _T_64 = cat(UInt<64>("h41300000393"), UInt<64>("h31300000293")) @[Cat.scala 30:58] + node _T_65 = cat(_T_64, _T_63) @[Cat.scala 30:58] + node _T_66 = cat(UInt<64>("h61300000593"), UInt<64>("h51300000493")) @[Cat.scala 30:58] + node _T_67 = cat(UInt<64>("h81300000793"), UInt<64>("h71300000693")) @[Cat.scala 30:58] + node _T_68 = cat(_T_67, _T_66) @[Cat.scala 30:58] + node _T_69 = cat(_T_68, _T_65) @[Cat.scala 30:58] + node _T_70 = cat(UInt<64>("ha1300000993"), UInt<64>("h91300000893")) @[Cat.scala 30:58] + node _T_71 = cat(UInt<64>("hc1300000b93"), UInt<64>("hb1300000a93")) @[Cat.scala 30:58] + node _T_72 = cat(_T_71, _T_70) @[Cat.scala 30:58] + node _T_73 = cat(UInt<64>("he1300000d93"), UInt<64>("hd1300000c93")) @[Cat.scala 30:58] + node _T_74 = cat(UInt<64>("h300029300000f93"), UInt<64>("hf1300000e93")) @[Cat.scala 30:58] + node _T_75 = cat(_T_74, _T_73) @[Cat.scala 30:58] + node _T_76 = cat(_T_75, _T_72) @[Cat.scala 30:58] + node _T_77 = cat(_T_76, _T_69) @[Cat.scala 30:58] + node _T_78 = cat(UInt<64>("h32b73002a073"), UInt<64>("h8002933002b073")) @[Cat.scala 30:58] + node _T_79 = cat(UInt<64>("h300022f33002a073"), UInt<64>("hc2b73002a073")) @[Cat.scala 30:58] + node _T_80 = cat(_T_79, _T_78) @[Cat.scala 30:58] + node _T_81 = cat(UInt<64>("hcc63aa2300006397"), UInt<64>("h62f3330000c337")) @[Cat.scala 30:58] + node _T_82 = cat(UInt<64>("h30107308030463"), UInt<64>("h62f33300003337")) @[Cat.scala 30:58] + node _T_83 = cat(_T_82, _T_81) @[Cat.scala 30:58] + node _T_84 = cat(_T_83, _T_80) @[Cat.scala 30:58] + node _T_85 = cat(UInt<64>("hf00001d3f0000153"), UInt<64>("hf00000d3f0000053")) @[Cat.scala 30:58] + node _T_86 = cat(UInt<64>("hf00003d3f0000353"), UInt<64>("hf00002d3f0000253")) @[Cat.scala 30:58] + node _T_87 = cat(_T_86, _T_85) @[Cat.scala 30:58] + node _T_88 = cat(UInt<64>("hf00005d3f0000553"), UInt<64>("hf00004d3f0000453")) @[Cat.scala 30:58] + node _T_89 = cat(UInt<64>("hf00007d3f0000753"), UInt<64>("hf00006d3f0000653")) @[Cat.scala 30:58] + node _T_90 = cat(_T_89, _T_88) @[Cat.scala 30:58] + node _T_91 = cat(_T_90, _T_87) @[Cat.scala 30:58] + node _T_92 = cat(_T_91, _T_84) @[Cat.scala 30:58] + node _T_93 = cat(_T_92, _T_77) @[Cat.scala 30:58] + node _T_94 = cat(UInt<64>("hf00009d3f0000953"), UInt<64>("hf00008d3f0000853")) @[Cat.scala 30:58] + node _T_95 = cat(UInt<64>("hf0000bd3f0000b53"), UInt<64>("hf0000ad3f0000a53")) @[Cat.scala 30:58] + node _T_96 = cat(_T_95, _T_94) @[Cat.scala 30:58] + node _T_97 = cat(UInt<64>("hf0000dd3f0000d53"), UInt<64>("hf0000cd3f0000c53")) @[Cat.scala 30:58] + node _T_98 = cat(UInt<64>("hf0000fd3f0000f53"), UInt<64>("hf0000ed3f0000e53")) @[Cat.scala 30:58] + node _T_99 = cat(_T_98, _T_97) @[Cat.scala 30:58] + node _T_100 = cat(_T_99, _T_96) @[Cat.scala 30:58] + node _T_101 = cat(UInt<64>("hd372021300006217"), UInt<64>("h43c1819300006197")) @[Cat.scala 30:58] + node _T_102 = cat(UInt<64>("hb5706300100593"), UInt<64>("hf1002573fc027213")) @[Cat.scala 30:58] + node _T_103 = cat(_T_102, _T_101) @[Cat.scala 30:58] + node _T_104 = cat(UInt<64>("h111111300150113"), UInt<64>("hc2023301151613")) @[Cat.scala 30:58] + node _T_105 = cat(UInt<64>("h34129073bac28293"), UInt<64>("h129700410133")) @[Cat.scala 30:58] + node _T_106 = cat(_T_105, _T_104) @[Cat.scala 30:58] + node _T_107 = cat(_T_106, _T_103) @[Cat.scala 30:58] + node _T_108 = cat(_T_107, _T_100) @[Cat.scala 30:58] + node _T_109 = cat(UInt<64>("h21242300112223"), UInt<64>("hef01011310000073")) @[Cat.scala 30:58] + node _T_110 = cat(UInt<64>("h612c2300512a23"), UInt<64>("h41282300312623")) @[Cat.scala 30:58] + node _T_111 = cat(_T_110, _T_109) @[Cat.scala 30:58] + node _T_112 = cat(UInt<64>("h2a1242302912223"), UInt<64>("h281202300712e23")) @[Cat.scala 30:58] + node _T_113 = cat(UInt<64>("h2e12c2302d12a23"), UInt<64>("h2c1282302b12623")) @[Cat.scala 30:58] + node _T_114 = cat(_T_113, _T_112) @[Cat.scala 30:58] + node _T_115 = cat(_T_114, _T_111) @[Cat.scala 30:58] + node _T_116 = cat(UInt<64>("h521242305112223"), UInt<64>("h501202302f12e23")) @[Cat.scala 30:58] + node _T_117 = cat(UInt<64>("h5612c2305512a23"), UInt<64>("h541282305312623")) @[Cat.scala 30:58] + node _T_118 = cat(_T_117, _T_116) @[Cat.scala 30:58] + node _T_119 = cat(UInt<64>("h7a1242307912223"), UInt<64>("h781202305712e23")) @[Cat.scala 30:58] + node _T_120 = cat(UInt<64>("h7e12c2307d12a23"), UInt<64>("h7c1282307b12623")) @[Cat.scala 30:58] + node _T_121 = cat(_T_120, _T_119) @[Cat.scala 30:58] + node _T_122 = cat(_T_121, _T_118) @[Cat.scala 30:58] + node _T_123 = cat(_T_122, _T_115) @[Cat.scala 30:58] + node _T_124 = cat(_T_123, _T_108) @[Cat.scala 30:58] + node _T_125 = cat(_T_124, _T_93) @[Cat.scala 30:58] + node _T_126 = cat(_T_125, _T_62) @[Cat.scala 30:58] + node _T_127 = cat(UInt<64>("h10613341025f3"), UInt<64>("h3420257307f12e23")) @[Cat.scala 30:58] + node _T_128 = cat(UInt<64>("h81210300412083"), UInt<64>("h34151073624000ef")) @[Cat.scala 30:58] + node _T_129 = cat(_T_128, _T_127) @[Cat.scala 30:58] + node _T_130 = cat(UInt<64>("h181230301412283"), UInt<64>("h101220300c12183")) @[Cat.scala 30:58] + node _T_131 = cat(UInt<64>("h281250302412483"), UInt<64>("h201240301c12383")) @[Cat.scala 30:58] + node _T_132 = cat(_T_131, _T_130) @[Cat.scala 30:58] + node _T_133 = cat(_T_132, _T_129) @[Cat.scala 30:58] + node _T_134 = cat(UInt<64>("h381270303412683"), UInt<64>("h301260302c12583")) @[Cat.scala 30:58] + node _T_135 = cat(UInt<64>("h481290304412883"), UInt<64>("h401280303c12783")) @[Cat.scala 30:58] + node _T_136 = cat(_T_135, _T_134) @[Cat.scala 30:58] + node _T_137 = cat(UInt<64>("h5812b0305412a83"), UInt<64>("h5012a0304c12983")) @[Cat.scala 30:58] + node _T_138 = cat(UInt<64>("h6812d0306412c83"), UInt<64>("h6012c0305c12b83")) @[Cat.scala 30:58] + node _T_139 = cat(_T_138, _T_137) @[Cat.scala 30:58] + node _T_140 = cat(_T_139, _T_136) @[Cat.scala 30:58] + node _T_141 = cat(_T_140, _T_133) @[Cat.scala 30:58] + node _T_142 = cat(UInt<64>("h7812f0307412e83"), UInt<64>("h7012e0306c12d83")) @[Cat.scala 30:58] + node _T_143 = cat(UInt<64>("h25181310000073"), UInt<64>("h1101011307c12f83")) @[Cat.scala 30:58] + node _T_144 = cat(_T_143, _T_142) @[Cat.scala 30:58] + node _T_145 = cat(UInt<64>("h8202301060833"), UInt<64>("h62023ffc80813")) @[Cat.scala 30:58] + node _T_146 = cat(UInt<64>("h440006f02a7c063"), UInt<64>("h46061300200793")) @[Cat.scala 30:58] + node _T_147 = cat(_T_146, _T_145) @[Cat.scala 30:58] + node _T_148 = cat(_T_147, _T_144) @[Cat.scala 30:58] + node _T_149 = cat(UInt<64>("h46061300d62023"), UInt<64>("h4e6c06302d7c863")) @[Cat.scala 30:58] + node _T_150 = cat(UInt<64>("h45a7830005a703"), UInt<64>("h2c8066300458593")) @[Cat.scala 30:58] + node _T_151 = cat(_T_150, _T_149) @[Cat.scala 30:58] + node _T_152 = cat(UInt<64>("hfcf6dee300d74e63"), UInt<64>("hfcf74ee30085a683")) @[Cat.scala 30:58] + node _T_153 = cat(UInt<64>("hfcc81ee300458593"), UInt<64>("h46061300f62023")) @[Cat.scala 30:58] + node _T_154 = cat(_T_153, _T_152) @[Cat.scala 30:58] + node _T_155 = cat(_T_154, _T_151) @[Cat.scala 30:58] + node _T_156 = cat(_T_155, _T_148) @[Cat.scala 30:58] + node _T_157 = cat(_T_156, _T_141) @[Cat.scala 30:58] + node _T_158 = cat(UInt<64>("h4022803fc5ff06f"), UInt<64>("he6202300008067")) @[Cat.scala 30:58] + node _T_159 = cat(UInt<64>("ha7802300180613"), UInt<64>("h10787b300020793")) @[Cat.scala 30:58] + node _T_160 = cat(_T_159, _T_158) @[Cat.scala 30:58] + node _T_161 = cat(UInt<64>("h400079300f50a63"), UInt<64>("ha0079304c22023")) @[Cat.scala 30:58] + node _T_162 = cat(UInt<64>("h400089300008067"), UInt<64>("h51300f60663")) @[Cat.scala 30:58] + node _T_163 = cat(_T_162, _T_161) @[Cat.scala 30:58] + node _T_164 = cat(_T_163, _T_160) @[Cat.scala 30:58] + node _T_165 = cat(UInt<64>("h402202300000073"), UInt<64>("h2059300100513")) @[Cat.scala 30:58] + node _T_166 = cat(UInt<64>("ha780230005a783"), UInt<64>("h806700000513")) @[Cat.scala 30:58] + node _T_167 = cat(_T_166, _T_165) @[Cat.scala 30:58] + node _T_168 = cat(UInt<64>("h806700f5a023"), UInt<64>("h1787930005a783")) @[Cat.scala 30:58] + node _T_169 = cat(UInt<64>("hcb0c079300002c37"), UInt<64>("h13812423eb010113")) @[Cat.scala 30:58] + node _T_170 = cat(_T_169, _T_168) @[Cat.scala 30:58] + node _T_171 = cat(_T_170, _T_167) @[Cat.scala 30:58] + node _T_172 = cat(_T_171, _T_164) @[Cat.scala 30:58] + node _T_173 = cat(UInt<64>("hfffd079300f12423"), UInt<64>("h40000d3713a12023")) @[Cat.scala 30:58] + node _T_174 = cat(UInt<64>("h13512a2313312e23"), UInt<64>("h1521202314912223")) @[Cat.scala 30:58] + node _T_175 = cat(_T_174, _T_173) @[Cat.scala 30:58] + node _T_176 = cat(UInt<64>("h1361282313412c23"), UInt<64>("h1481242314112623")) @[Cat.scala 30:58] + node _T_177 = cat(UInt<64>("h5099311b12e23"), UInt<64>("h1391222313712623")) @[Cat.scala 30:58] + node _T_178 = cat(_T_177, _T_176) @[Cat.scala 30:58] + node _T_179 = cat(_T_178, _T_175) @[Cat.scala 30:58] + node _T_180 = cat(UInt<64>("h2500a9300d12223"), UInt<64>("h6049300058913")) @[Cat.scala 30:58] + node _T_181 = cat(UInt<64>("h14849306050263"), UInt<64>("h140006f00f12623")) @[Cat.scala 30:58] + node _T_182 = cat(_T_181, _T_180) @[Cat.scala 30:58] + node _T_183 = cat(UInt<64>("hff5516e30004c503"), UInt<64>("h980e700090593")) @[Cat.scala 30:58] + node _T_184 = cat(UInt<64>("h2000793fff00413"), UInt<64>("h148a130014c503")) @[Cat.scala 30:58] + node _T_185 = cat(_T_184, _T_183) @[Cat.scala 30:58] + node _T_186 = cat(_T_185, _T_182) @[Cat.scala 30:58] + node _T_187 = cat(_T_186, _T_179) @[Cat.scala 30:58] + node _T_188 = cat(_T_187, _T_172) @[Cat.scala 30:58] + node _T_189 = cat(_T_188, _T_157) @[Cat.scala 30:58] + node _T_190 = cat(UInt<64>("h61300040b13"), UInt<64>("hf12023000a0713")) @[Cat.scala 30:58] + node _T_191 = cat(UInt<64>("h55006930ff7f793"), UInt<64>("hfdd5079300900593")) @[Cat.scala 30:58] + node _T_192 = cat(_T_191, _T_190) @[Cat.scala 30:58] + node _T_193 = cat(UInt<64>("h27979300812683"), UInt<64>("h38f6e26300170493")) @[Cat.scala 30:58] + node _T_194 = cat(UInt<64>("h14c1208300078067"), UInt<64>("h7a78300d787b3")) @[Cat.scala 30:58] + node _T_195 = cat(_T_194, _T_193) @[Cat.scala 30:58] + node _T_196 = cat(_T_195, _T_192) @[Cat.scala 30:58] + node _T_197 = cat(UInt<64>("h13c1298314012903"), UInt<64>("h1441248314812403")) @[Cat.scala 30:58] + node _T_198 = cat(UInt<64>("h12c12b8313012b03"), UInt<64>("h13412a8313812a03")) @[Cat.scala 30:58] + node _T_199 = cat(_T_198, _T_197) @[Cat.scala 30:58] + node _T_200 = cat(UInt<64>("h11c12d8312012d03"), UInt<64>("h12412c8312812c03")) @[Cat.scala 30:58] + node _T_201 = cat(UInt<64>("hb13000b5463"), UInt<64>("h806715010113")) @[Cat.scala 30:58] + node _T_202 = cat(_T_201, _T_200) @[Cat.scala 30:58] + node _T_203 = cat(_T_202, _T_199) @[Cat.scala 30:58] + node _T_204 = cat(_T_203, _T_196) @[Cat.scala 30:58] + node _T_205 = cat(UInt<64>("h800413f8dff06f"), UInt<64>("h4871300174503")) @[Cat.scala 30:58] + node _T_206 = cat(UInt<64>("h41278328c7d663"), UInt<64>("h10079300000a13")) @[Cat.scala 30:58] + node _T_207 = cat(_T_206, _T_205) @[Cat.scala 30:58] + node _T_208 = cat(UInt<64>("h47ab830007ac83"), UInt<64>("hff87f79300778793")) @[Cat.scala 30:58] + node _T_209 = cat(UInt<64>("h69300040613"), UInt<64>("he1222300878713")) @[Cat.scala 30:58] + node _T_210 = cat(_T_209, _T_208) @[Cat.scala 30:58] + node _T_211 = cat(_T_210, _T_207) @[Cat.scala 30:58] + node _T_212 = cat(UInt<64>("ha128230c0010ef"), UInt<64>("hb8593000c8513")) @[Cat.scala 30:58] + node _T_213 = cat(UInt<64>("h4061300100d13"), UInt<64>("h1410d93337a0c63")) @[Cat.scala 30:58] + node _T_214 = cat(_T_213, _T_212) @[Cat.scala 30:58] + node _T_215 = cat(UInt<64>("h409000ef000b8593"), UInt<64>("hc851300000693")) @[Cat.scala 30:58] + node _T_216 = cat(UInt<64>("h58b9300050c93"), UInt<64>("h69300040613")) @[Cat.scala 30:58] + node _T_217 = cat(_T_216, _T_215) @[Cat.scala 30:58] + node _T_218 = cat(_T_217, _T_214) @[Cat.scala 30:58] + node _T_219 = cat(_T_218, _T_211) @[Cat.scala 30:58] + node _T_220 = cat(_T_219, _T_204) @[Cat.scala 30:58] + node _T_221 = cat(UInt<64>("h4d8d93001d0c13"), UInt<64>("hada023088010ef")) @[Cat.scala 30:58] + node _T_222 = cat(UInt<64>("hfe8cfce3fc5ff06f"), UInt<64>("hc0d13017a0663")) @[Cat.scala 30:58] + node _T_223 = cat(_T_222, _T_221) @[Cat.scala 30:58] + node _T_224 = cat(UInt<64>("h12503036c5263"), UInt<64>("hd0a13fffb0413")) @[Cat.scala 30:58] + node _T_225 = cat(UInt<64>("h140793000980e7"), UInt<64>("hfff4041300090593")) @[Cat.scala 30:58] + node _T_226 = cat(_T_225, _T_224) @[Cat.scala 30:58] + node _T_227 = cat(_T_226, _T_223) @[Cat.scala 30:58] + node _T_228 = cat(UInt<64>("h2d1793eb8050e3"), UInt<64>("ha0d13fefc46e3")) @[Cat.scala 30:58] + node _T_229 = cat(UInt<64>("hc12783f007a503"), UInt<64>("hf707b311010713")) @[Cat.scala 30:58] + node _T_230 = cat(_T_229, _T_228) @[Cat.scala 30:58] + node _T_231 = cat(UInt<64>("h1010793002a1a13"), UInt<64>("hfd0a33000d0413")) @[Cat.scala 30:58] + node _T_232 = cat(UInt<64>("hfff40413000a2503"), UInt<64>("h100006f01478a33")) @[Cat.scala 30:58] + node _T_233 = cat(_T_232, _T_231) @[Cat.scala 30:58] + node _T_234 = cat(_T_233, _T_230) @[Cat.scala 30:58] + node _T_235 = cat(_T_234, _T_227) @[Cat.scala 30:58] + node _T_236 = cat(UInt<64>("hfd97f79340f007b3"), UInt<64>("ha53793ffca0a13")) @[Cat.scala 30:58] + node _T_237 = cat(UInt<64>("h980e700a78533"), UInt<64>("h9059305778793")) @[Cat.scala 30:58] + node _T_238 = cat(_T_237, _T_236) @[Cat.scala 30:58] + node _T_239 = cat(UInt<64>("h17450300412783"), UInt<64>("he45ff06ffc804ce3")) @[Cat.scala 30:58] + node _T_240 = cat(UInt<64>("hf1222300478793"), UInt<64>("h7a40300048713")) @[Cat.scala 30:58] + node _T_241 = cat(_T_240, _T_239) @[Cat.scala 30:58] + node _T_242 = cat(_T_241, _T_238) @[Cat.scala 30:58] + node _T_243 = cat(UInt<64>("he49ff06ffff00413"), UInt<64>("h40b13e40b5ae3")) @[Cat.scala 30:58] + node _T_244 = cat(UInt<64>("h4871300f12023"), UInt<64>("h17450303000793")) @[Cat.scala 30:58] + node _T_245 = cat(_T_244, _T_243) @[Cat.scala 30:58] + node _T_246 = cat(UInt<64>("hf1202300174503"), UInt<64>("h2d00793e35ff06f")) @[Cat.scala 30:58] + node _T_247 = cat(UInt<64>("hfd05041300174683"), UInt<64>("he21ff06f00048713")) @[Cat.scala 30:58] + node _T_248 = cat(_T_247, _T_246) @[Cat.scala 30:58] + node _T_249 = cat(_T_248, _T_245) @[Cat.scala 30:58] + node _T_250 = cat(_T_249, _T_242) @[Cat.scala 30:58] + node _T_251 = cat(_T_250, _T_235) @[Cat.scala 30:58] + node _T_252 = cat(_T_251, _T_220) @[Cat.scala 30:58] + node _T_253 = cat(_T_252, _T_189) @[Cat.scala 30:58] + node _T_254 = cat(_T_253, _T_126) @[Cat.scala 30:58] + node _T_255 = cat(UInt<64>("h1417931ef5ea63"), UInt<64>("hfd06879300048713")) @[Cat.scala 30:58] + node _T_256 = cat(UInt<64>("hd4043300170713"), UInt<64>("h87843300341413")) @[Cat.scala 30:58] + node _T_257 = cat(_T_256, _T_255) @[Cat.scala 30:58] + node _T_258 = cat(UInt<64>("hfef5f0e3fd068793"), UInt<64>("hfd04041300074683")) @[Cat.scala 30:58] + node _T_259 = cat(UInt<64>("h9059300412783"), UInt<64>("hf8dff06f00068513")) @[Cat.scala 30:58] + node _T_260 = cat(_T_259, _T_258) @[Cat.scala 30:58] + node _T_261 = cat(_T_260, _T_257) @[Cat.scala 30:58] + node _T_262 = cat(UInt<64>("h1912223000980e7"), UInt<64>("h478c930007a503")) @[Cat.scala 30:58] + node _T_263 = cat(UInt<64>("h478c930007ac03"), UInt<64>("h412783d99ff06f")) @[Cat.scala 30:58] + node _T_264 = cat(_T_263, _T_262) @[Cat.scala 30:58] + node _T_265 = cat(UInt<64>("h2d0071300012783"), UInt<64>("h3605c63160c0c63")) @[Cat.scala 30:58] + node _T_266 = cat(UInt<64>("h235000ef000c0513"), UInt<64>("h4059314e78c63")) @[Cat.scala 30:58] + node _T_267 = cat(_T_266, _T_265) @[Cat.scala 30:58] + node _T_268 = cat(_T_267, _T_264) @[Cat.scala 30:58] + node _T_269 = cat(_T_268, _T_261) @[Cat.scala 30:58] + node _T_270 = cat(UInt<64>("hfffb0b1300012503"), UInt<64>("h1605c6340ab0b33")) @[Cat.scala 30:58] + node _T_271 = cat(UInt<64>("hc4503fe0b18e3"), UInt<64>("h980e700090593")) @[Cat.scala 30:58] + node _T_272 = cat(_T_271, _T_270) @[Cat.scala 30:58] + node _T_273 = cat(UInt<64>("hfff4041300044663"), UInt<64>("hfff00a1304050263")) @[Cat.scala 30:58] + node _T_274 = cat(UInt<64>("h980e7001c0c13"), UInt<64>("h9059301440e63")) @[Cat.scala 30:58] + node _T_275 = cat(_T_274, _T_273) @[Cat.scala 30:58] + node _T_276 = cat(_T_275, _T_272) @[Cat.scala 30:58] + node _T_277 = cat(UInt<64>("h1605c63fe0510e3"), UInt<64>("hfffb0b13000c4503")) @[Cat.scala 30:58] + node _T_278 = cat(UInt<64>("h980e702000513"), UInt<64>("h90593fffb0b13")) @[Cat.scala 30:58] + node _T_279 = cat(_T_278, _T_277) @[Cat.scala 30:58] + node _T_280 = cat(UInt<64>("ha00413d01ff06f"), UInt<64>("h1912223fe0b18e3")) @[Cat.scala 30:58] + node _T_281 = cat(UInt<64>("ha1301000413"), UInt<64>("hda1ff06f00000a13")) @[Cat.scala 30:58] + node _T_282 = cat(_T_281, _T_280) @[Cat.scala 30:58] + node _T_283 = cat(_T_282, _T_279) @[Cat.scala 30:58] + node _T_284 = cat(_T_283, _T_276) @[Cat.scala 30:58] + node _T_285 = cat(_T_284, _T_269) @[Cat.scala 30:58] + node _T_286 = cat(UInt<64>("h980e700090593"), UInt<64>("h3000513d95ff06f")) @[Cat.scala 30:58] + node _T_287 = cat(UInt<64>("h1000413000980e7"), UInt<64>("h780051300090593")) @[Cat.scala 30:58] + node _T_288 = cat(_T_287, _T_286) @[Cat.scala 30:58] + node _T_289 = cat(UInt<64>("h7ac8300000b93"), UInt<64>("h41278300000a13")) @[Cat.scala 30:58] + node _T_290 = cat(UInt<64>("h100793d81ff06f"), UInt<64>("hf1222300478793")) @[Cat.scala 30:58] + node _T_291 = cat(_T_290, _T_289) @[Cat.scala 30:58] + node _T_292 = cat(_T_291, _T_288) @[Cat.scala 30:58] + node _T_293 = cat(UInt<64>("hff87f79300778793"), UInt<64>("h4127830ac7d263")) @[Cat.scala 30:58] + node _T_294 = cat(UInt<64>("he122230047a783"), UInt<64>("h7a80300878713")) @[Cat.scala 30:58] + node _T_295 = cat(_T_294, _T_293) @[Cat.scala 30:58] + node _T_296 = cat(UInt<64>("h905930407da63"), UInt<64>("h80c9300078b93")) @[Cat.scala 30:58] + node _T_297 = cat(UInt<64>("h100373341900833"), UInt<64>("h980e702d00513")) @[Cat.scala 30:58] + node _T_298 = cat(_T_297, _T_296) @[Cat.scala 30:58] + node _T_299 = cat(_T_298, _T_295) @[Cat.scala 30:58] + node _T_300 = cat(_T_299, _T_292) @[Cat.scala 30:58] + node _T_301 = cat(UInt<64>("ha0041340e78bb3"), UInt<64>("h80c93417007b3")) @[Cat.scala 30:58] + node _T_302 = cat(UInt<64>("h16061300174503"), UInt<64>("hd25ff06f00000a13")) @[Cat.scala 30:58] + node _T_303 = cat(_T_302, _T_301) @[Cat.scala 30:58] + node _T_304 = cat(UInt<64>("h250051300090593"), UInt<64>("hc71ff06f00048713")) @[Cat.scala 30:58] + node _T_305 = cat(UInt<64>("ha00413c31ff06f"), UInt<64>("ha0493000980e7")) @[Cat.scala 30:58] + node _T_306 = cat(_T_305, _T_304) @[Cat.scala 30:58] + node _T_307 = cat(_T_306, _T_303) @[Cat.scala 30:58] + node _T_308 = cat(UInt<64>("hf00502e3000c4503"), UInt<64>("hcf5ff06f00000a13")) @[Cat.scala 30:58] + node _T_309 = cat(UInt<64>("hf0878c13000027b7"), UInt<64>("hed5ff06ffff00a13")) @[Cat.scala 30:58] + node _T_310 = cat(_T_309, _T_308) @[Cat.scala 30:58] + node _T_311 = cat(UInt<64>("h4787930007a803"), UInt<64>("h412783e85ff06f")) @[Cat.scala 30:58] + node _T_312 = cat(UInt<64>("h68513f69ff06f"), UInt<64>("h41f8579300f12223")) @[Cat.scala 30:58] + node _T_313 = cat(_T_312, _T_311) @[Cat.scala 30:58] + node _T_314 = cat(_T_313, _T_310) @[Cat.scala 30:58] + node _T_315 = cat(_T_314, _T_307) @[Cat.scala 30:58] + node _T_316 = cat(_T_315, _T_300) @[Cat.scala 30:58] + node _T_317 = cat(_T_316, _T_285) @[Cat.scala 30:58] + node _T_318 = cat(UInt<64>("h100c13cc8cf6e3"), UInt<64>("hdbdff06f00048713")) @[Cat.scala 30:58] + node _T_319 = cat(UInt<64>("hd16c48e300000d13"), UInt<64>("ha13fffb0413")) @[Cat.scala 30:58] + node _T_320 = cat(_T_319, _T_318) @[Cat.scala 30:58] + node _T_321 = cat(UInt<64>("h7807907300156793"), UInt<64>("h151513d3dff06f")) @[Cat.scala 30:58] + node _T_322 = cat(UInt<64>("h11262300812423"), UInt<64>("hff0101130000006f")) @[Cat.scala 30:58] + node _T_323 = cat(_T_322, _T_321) @[Cat.scala 30:58] + node _T_324 = cat(_T_323, _T_320) @[Cat.scala 30:58] + node _T_325 = cat(UInt<64>("hc0025730080076f"), UInt<64>("h101041300200693")) @[Cat.scala 30:58] + node _T_326 = cat(UInt<64>("he50a6300800713"), UInt<64>("had50863f8010113")) @[Cat.scala 30:58] + node _T_327 = cat(_T_326, _T_325) @[Cat.scala 30:58] + node _T_328 = cat(UInt<64>("h6f78079073"), UInt<64>("ha7378793000017b7")) @[Cat.scala 30:58] + node _T_329 = cat(UInt<64>("h4d20069330d70063"), UInt<64>("h5d0069304462703")) @[Cat.scala 30:58] + node _T_330 = cat(_T_329, _T_328) @[Cat.scala 30:58] + node _T_331 = cat(_T_330, _T_327) @[Cat.scala 30:58] + node _T_332 = cat(_T_331, _T_324) @[Cat.scala 30:58] + node _T_333 = cat(UInt<64>("h2862303fc07f793"), UInt<64>("h3f1079308d70e63")) @[Cat.scala 30:58] + node _T_334 = cat(UInt<64>("h2c625030117a223"), UInt<64>("h41f7589300e7a023")) @[Cat.scala 30:58] + node _T_335 = cat(_T_334, _T_333) @[Cat.scala 30:58] + node _T_336 = cat(UInt<64>("h306268301f7a623"), UInt<64>("h41f35f930067a423")) @[Cat.scala 30:58] + node _T_337 = cat(UInt<64>("hd7ac2301d7aa23"), UInt<64>("h41f55e9300a7a823")) @[Cat.scala 30:58] + node _T_338 = cat(_T_337, _T_336) @[Cat.scala 30:58] + node _T_339 = cat(_T_338, _T_335) @[Cat.scala 30:58] + node _T_340 = cat(UInt<64>("h780790730330000f"), UInt<64>("h117ae2341f6d893")) @[Cat.scala 30:58] + node _T_341 = cat(UInt<64>("h7a703fe068ee3"), UInt<64>("h781716f300000713")) @[Cat.scala 30:58] + node _T_342 = cat(_T_341, _T_340) @[Cat.scala 30:58] + node _T_343 = cat(UInt<64>("hc12083ff040113"), UInt<64>("h707930047a783")) @[Cat.scala 30:58] + node _T_344 = cat(UInt<64>("h101011302f62423"), UInt<64>("h81240300458513")) @[Cat.scala 30:58] + node _T_345 = cat(_T_344, _T_343) @[Cat.scala 30:58] + node _T_346 = cat(_T_345, _T_342) @[Cat.scala 30:58] + node _T_347 = cat(_T_346, _T_339) @[Cat.scala 30:58] + node _T_348 = cat(_T_347, _T_332) @[Cat.scala 30:58] + node _T_349 = cat(UInt<64>("hf777b30005a783"), UInt<64>("h7270300008067")) @[Cat.scala 30:58] + node _T_350 = cat(UInt<64>("h2862703fd1ff06f"), UInt<64>("h793f4f718e3")) @[Cat.scala 30:58] + node _T_351 = cat(_T_350, _T_349) @[Cat.scala 30:58] + node _T_352 = cat(UInt<64>("h80418793c0002573"), UInt<64>("hc00e57300070463")) @[Cat.scala 30:58] + node _T_353 = cat(UInt<64>("h26b740d50533"), UInt<64>("h7a68300071c63")) @[Cat.scala 30:58] + node _T_354 = cat(_T_353, _T_352) @[Cat.scala 30:58] + node _T_355 = cat(_T_354, _T_351) @[Cat.scala 30:58] + node _T_356 = cat(UInt<64>("hc020257300a7a023"), UInt<64>("h4d7a423f1068693")) @[Cat.scala 30:58] + node _T_357 = cat(UInt<64>("h26b740d50533"), UInt<64>("h47a68300071c63")) @[Cat.scala 30:58] + node _T_358 = cat(_T_357, _T_356) @[Cat.scala 30:58] + node _T_359 = cat(UInt<64>("hcc00257300a7a223"), UInt<64>("h4d7a623f1868693")) @[Cat.scala 30:58] + node _T_360 = cat(UInt<64>("h26b740d50533"), UInt<64>("h87a68300071c63")) @[Cat.scala 30:58] + node _T_361 = cat(_T_360, _T_359) @[Cat.scala 30:58] + node _T_362 = cat(_T_361, _T_358) @[Cat.scala 30:58] + node _T_363 = cat(_T_362, _T_355) @[Cat.scala 30:58] + node _T_364 = cat(UInt<64>("hcc10257300a7a423"), UInt<64>("h4d7a823f2068693")) @[Cat.scala 30:58] + node _T_365 = cat(UInt<64>("h26b740d50533"), UInt<64>("hc7a68300071c63")) @[Cat.scala 30:58] + node _T_366 = cat(_T_365, _T_364) @[Cat.scala 30:58] + node _T_367 = cat(UInt<64>("hcc20257300a7a623"), UInt<64>("h4d7aa23f2868693")) @[Cat.scala 30:58] + node _T_368 = cat(UInt<64>("h26b740d50533"), UInt<64>("h107a68300071c63")) @[Cat.scala 30:58] + node _T_369 = cat(_T_368, _T_367) @[Cat.scala 30:58] + node _T_370 = cat(_T_369, _T_366) @[Cat.scala 30:58] + node _T_371 = cat(UInt<64>("hcc30257300a7a823"), UInt<64>("h4d7ac23f3068693")) @[Cat.scala 30:58] + node _T_372 = cat(UInt<64>("h26b740d50533"), UInt<64>("h147a68300071c63")) @[Cat.scala 30:58] + node _T_373 = cat(_T_372, _T_371) @[Cat.scala 30:58] + node _T_374 = cat(UInt<64>("hcc40257300a7aa23"), UInt<64>("h4d7ae23f3868693")) @[Cat.scala 30:58] + node _T_375 = cat(UInt<64>("h26b740d50533"), UInt<64>("h187a68300071c63")) @[Cat.scala 30:58] + node _T_376 = cat(_T_375, _T_374) @[Cat.scala 30:58] + node _T_377 = cat(_T_376, _T_373) @[Cat.scala 30:58] + node _T_378 = cat(_T_377, _T_370) @[Cat.scala 30:58] + node _T_379 = cat(_T_378, _T_363) @[Cat.scala 30:58] + node _T_380 = cat(_T_379, _T_348) @[Cat.scala 30:58] + node _T_381 = cat(_T_380, _T_317) @[Cat.scala 30:58] + node _T_382 = cat(UInt<64>("hcc50257300a7ac23"), UInt<64>("h6d7a023f4068693")) @[Cat.scala 30:58] + node _T_383 = cat(UInt<64>("h26b740d50533"), UInt<64>("h1c7a68300071c63")) @[Cat.scala 30:58] + node _T_384 = cat(_T_383, _T_382) @[Cat.scala 30:58] + node _T_385 = cat(UInt<64>("hcc60257300a7ae23"), UInt<64>("h6d7a223f4868693")) @[Cat.scala 30:58] + node _T_386 = cat(UInt<64>("h26b740d50533"), UInt<64>("h207a68300071c63")) @[Cat.scala 30:58] + node _T_387 = cat(_T_386, _T_385) @[Cat.scala 30:58] + node _T_388 = cat(_T_387, _T_384) @[Cat.scala 30:58] + node _T_389 = cat(UInt<64>("hcc70257302a7a023"), UInt<64>("h6d7a423f5068693")) @[Cat.scala 30:58] + node _T_390 = cat(UInt<64>("h26b740d50533"), UInt<64>("h247a68300071c63")) @[Cat.scala 30:58] + node _T_391 = cat(_T_390, _T_389) @[Cat.scala 30:58] + node _T_392 = cat(UInt<64>("hcc80257302a7a223"), UInt<64>("h6d7a623f5868693")) @[Cat.scala 30:58] + node _T_393 = cat(UInt<64>("h26b740d50533"), UInt<64>("h287a68300071c63")) @[Cat.scala 30:58] + node _T_394 = cat(_T_393, _T_392) @[Cat.scala 30:58] + node _T_395 = cat(_T_394, _T_391) @[Cat.scala 30:58] + node _T_396 = cat(_T_395, _T_388) @[Cat.scala 30:58] + node _T_397 = cat(UInt<64>("hcc90257302a7a423"), UInt<64>("h6d7a823f6068693")) @[Cat.scala 30:58] + node _T_398 = cat(UInt<64>("h26b740d50533"), UInt<64>("h2c7a68300071c63")) @[Cat.scala 30:58] + node _T_399 = cat(_T_398, _T_397) @[Cat.scala 30:58] + node _T_400 = cat(UInt<64>("hcca0257302a7a623"), UInt<64>("h6d7aa23f6868693")) @[Cat.scala 30:58] + node _T_401 = cat(UInt<64>("h26b740d50533"), UInt<64>("h307a68300071c63")) @[Cat.scala 30:58] + node _T_402 = cat(_T_401, _T_400) @[Cat.scala 30:58] + node _T_403 = cat(_T_402, _T_399) @[Cat.scala 30:58] + node _T_404 = cat(UInt<64>("hccb0257302a7a823"), UInt<64>("h6d7ac23f7068693")) @[Cat.scala 30:58] + node _T_405 = cat(UInt<64>("h26b740d50533"), UInt<64>("h347a68300071c63")) @[Cat.scala 30:58] + node _T_406 = cat(_T_405, _T_404) @[Cat.scala 30:58] + node _T_407 = cat(UInt<64>("hccc0257302a7aa23"), UInt<64>("h6d7ae23f7868693")) @[Cat.scala 30:58] + node _T_408 = cat(UInt<64>("h26b740d50533"), UInt<64>("h387a68300071c63")) @[Cat.scala 30:58] + node _T_409 = cat(_T_408, _T_407) @[Cat.scala 30:58] + node _T_410 = cat(_T_409, _T_406) @[Cat.scala 30:58] + node _T_411 = cat(_T_410, _T_403) @[Cat.scala 30:58] + node _T_412 = cat(_T_411, _T_396) @[Cat.scala 30:58] + node _T_413 = cat(UInt<64>("hccd0257302a7ac23"), UInt<64>("h8d7a023f8068693")) @[Cat.scala 30:58] + node _T_414 = cat(UInt<64>("h26b740d50533"), UInt<64>("h3c7a68300071c63")) @[Cat.scala 30:58] + node _T_415 = cat(_T_414, _T_413) @[Cat.scala 30:58] + node _T_416 = cat(UInt<64>("hcce0257302a7ae23"), UInt<64>("h8d7a223f8868693")) @[Cat.scala 30:58] + node _T_417 = cat(UInt<64>("h26b740d50533"), UInt<64>("h407a68300071c63")) @[Cat.scala 30:58] + node _T_418 = cat(_T_417, _T_416) @[Cat.scala 30:58] + node _T_419 = cat(_T_418, _T_415) @[Cat.scala 30:58] + node _T_420 = cat(UInt<64>("hccf0257304a7a023"), UInt<64>("h8d7a423f9068693")) @[Cat.scala 30:58] + node _T_421 = cat(UInt<64>("h273740e50533"), UInt<64>("h447a70302071863")) @[Cat.scala 30:58] + node _T_422 = cat(_T_421, _T_420) @[Cat.scala 30:58] + node _T_423 = cat(UInt<64>("hc00f57304a7a223"), UInt<64>("h8e7a623f9870713")) @[Cat.scala 30:58] + node _T_424 = cat(UInt<64>("hca9ff0ef02862503"), UInt<64>("hd75ff06f00000793")) @[Cat.scala 30:58] + node _T_425 = cat(_T_424, _T_423) @[Cat.scala 30:58] + node _T_426 = cat(_T_425, _T_422) @[Cat.scala 30:58] + node _T_427 = cat(_T_426, _T_419) @[Cat.scala 30:58] + node _T_428 = cat(UInt<64>("h59305d00893"), UInt<64>("hd91ff06f04a7a223")) @[Cat.scala 30:58] + node _T_429 = cat(UInt<64>("h4d2008930000006f"), UInt<64>("h7300000613")) @[Cat.scala 30:58] + node _T_430 = cat(_T_429, _T_428) @[Cat.scala 30:58] + node _T_431 = cat(UInt<64>("h806700000073"), UInt<64>("h61300000593")) @[Cat.scala 30:58] + node _T_432 = cat(UInt<64>("h5041300112623"), UInt<64>("h812423ff010113")) @[Cat.scala 30:58] + node _T_433 = cat(_T_432, _T_431) @[Cat.scala 30:58] + node _T_434 = cat(_T_433, _T_430) @[Cat.scala 30:58] + node _T_435 = cat(UInt<64>("h10051304000893"), UInt<64>("h50613460000ef")) @[Cat.scala 30:58] + node _T_436 = cat(UInt<64>("h81240300c12083"), UInt<64>("h7300040593")) @[Cat.scala 30:58] + node _T_437 = cat(_T_436, _T_435) @[Cat.scala 30:58] + node _T_438 = cat(UInt<64>("h6f00050463"), UInt<64>("h806701010113")) @[Cat.scala 30:58] + node _T_439 = cat(UInt<64>("h1b1069302112623"), UInt<64>("hfd01011300008067")) @[Cat.scala 30:58] + node _T_440 = cat(_T_439, _T_438) @[Cat.scala 30:58] + node _T_441 = cat(_T_440, _T_437) @[Cat.scala 30:58] + node _T_442 = cat(_T_441, _T_434) @[Cat.scala 30:58] + node _T_443 = cat(_T_442, _T_427) @[Cat.scala 30:58] + node _T_444 = cat(_T_443, _T_412) @[Cat.scala 30:58] + node _T_445 = cat(UInt<64>("hc8373300f57613"), UInt<64>("h90081300b10893")) @[Cat.scala 30:58] + node _T_446 = cat(UInt<64>("hc787b303078793"), UInt<64>("h277779340e00733")) @[Cat.scala 30:58] + node _T_447 = cat(_T_446, _T_445) @[Cat.scala 30:58] + node _T_448 = cat(UInt<64>("hfff6869300455513"), UInt<64>("hf6802301c59713")) @[Cat.scala 30:58] + node _T_449 = cat(UInt<64>("hc10513fd1698e3"), UInt<64>("h45d59300a76533")) @[Cat.scala 30:58] + node _T_450 = cat(_T_449, _T_448) @[Cat.scala 30:58] + node _T_451 = cat(_T_450, _T_447) @[Cat.scala 30:58] + node _T_452 = cat(UInt<64>("h400089300050613"), UInt<64>("h3dc000ef00010e23")) @[Cat.scala 30:58] + node _T_453 = cat(UInt<64>("h2c1208300000073"), UInt<64>("hc1059300100513")) @[Cat.scala 30:58] + node _T_454 = cat(_T_453, _T_452) @[Cat.scala 30:58] + node _T_455 = cat(UInt<64>("h2410313fc010113"), UInt<64>("h806703010113")) @[Cat.scala 30:58] + node _T_456 = cat(UInt<64>("h2d1262302b12223"), UInt<64>("h5061302c12423")) @[Cat.scala 30:58] + node _T_457 = cat(_T_456, _T_455) @[Cat.scala 30:58] + node _T_458 = cat(_T_457, _T_454) @[Cat.scala 30:58] + node _T_459 = cat(_T_458, _T_451) @[Cat.scala 30:58] + node _T_460 = cat(UInt<64>("h112e2300000593"), UInt<64>("h3069350c00513")) @[Cat.scala 30:58] + node _T_461 = cat(UInt<64>("h3112e2303012c23"), UInt<64>("h2f12a2302e12823")) @[Cat.scala 30:58] + node _T_462 = cat(_T_461, _T_460) @[Cat.scala 30:58] + node _T_463 = cat(UInt<64>("h51301c12083"), UInt<64>("heccff0ef00612623")) @[Cat.scala 30:58] + node _T_464 = cat(UInt<64>("h3810313fb010113"), UInt<64>("h806704010113")) @[Cat.scala 30:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 30:58] + node _T_466 = cat(_T_465, _T_462) @[Cat.scala 30:58] + node _T_467 = cat(UInt<64>("h2c12c2300050413"), UInt<64>("ha1262302812423")) @[Cat.scala 30:58] + node _T_468 = cat(UInt<64>("hc1059355800513"), UInt<64>("h5861302d12e23")) @[Cat.scala 30:58] + node _T_469 = cat(_T_468, _T_467) @[Cat.scala 30:58] + node _T_470 = cat(UInt<64>("h4e1202304f12223"), UInt<64>("h211262300030693")) @[Cat.scala 30:58] + node _T_471 = cat(UInt<64>("he74ff0ef00612e23"), UInt<64>("h511262305012423")) @[Cat.scala 30:58] + node _T_472 = cat(_T_471, _T_470) @[Cat.scala 30:58] + node _T_473 = cat(_T_472, _T_469) @[Cat.scala 30:58] + node _T_474 = cat(_T_473, _T_466) @[Cat.scala 30:58] + node _T_475 = cat(_T_474, _T_459) @[Cat.scala 30:58] + node _T_476 = cat(UInt<64>("h2c1208300c12503"), UInt<64>("h7802300c12783")) @[Cat.scala 30:58] + node _T_477 = cat(UInt<64>("h806705010113"), UInt<64>("h281240340850533")) @[Cat.scala 30:58] + node _T_478 = cat(_T_477, _T_476) @[Cat.scala 30:58] + node _T_479 = cat(UInt<64>("h2091303212023"), UInt<64>("h2912223fd010113")) @[Cat.scala 30:58] + node _T_480 = cat(UInt<64>("h58a1301412c23"), UInt<64>("h409904b300020493")) @[Cat.scala 30:58] + node _T_481 = cat(_T_480, _T_479) @[Cat.scala 30:58] + node _T_482 = cat(_T_481, _T_478) @[Cat.scala 30:58] + node _T_483 = cat(UInt<64>("h301041301312e23"), UInt<64>("h281242302112623")) @[Cat.scala 30:58] + node _T_484 = cat(UInt<64>("h5099301712623"), UInt<64>("h161282301512a23")) @[Cat.scala 30:58] + node _T_485 = cat(_T_484, _T_483) @[Cat.scala 30:58] + node _T_486 = cat(UInt<64>("h8c41859300048613"), UInt<64>("h20513d8010113")) @[Cat.scala 30:58] + node _T_487 = cat(UInt<64>("h4126063304420613"), UInt<64>("hb0000ef00020b13")) @[Cat.scala 30:58] + node _T_488 = cat(_T_487, _T_486) @[Cat.scala 30:58] + node _T_489 = cat(_T_488, _T_485) @[Cat.scala 30:58] + node _T_490 = cat(_T_489, _T_482) @[Cat.scala 30:58] + node _T_491 = cat(UInt<64>("ha05931bc000ef"), UInt<64>("h593009b0533")) @[Cat.scala 30:58] + node _T_492 = cat(UInt<64>("h59303f10a93"), UInt<64>("he55ff0ef00098513")) @[Cat.scala 30:58] + node _T_493 = cat(_T_492, _T_491) @[Cat.scala 30:58] + node _T_494 = cat(UInt<64>("h425000effc0afa93"), UInt<64>("h8041849300000513")) @[Cat.scala 30:58] + node _T_495 = cat(UInt<64>("ha8a1300090993"), UInt<64>("h50b9304848913")) @[Cat.scala 30:58] + node _T_496 = cat(_T_495, _T_494) @[Cat.scala 30:58] + node _T_497 = cat(_T_496, _T_493) @[Cat.scala 30:58] + node _T_498 = cat(UInt<64>("h49091300448493"), UInt<64>("h100006f00002b37")) @[Cat.scala 30:58] + node _T_499 = cat(UInt<64>("h92603fe0688e3"), UInt<64>("h4a68303348663")) @[Cat.scala 30:58] + node _T_500 = cat(_T_499, _T_498) @[Cat.scala 30:58] + node _T_501 = cat(UInt<64>("h448493ed1ff0ef"), UInt<64>("hfb8b0593000a0513")) @[Cat.scala 30:58] + node _T_502 = cat(UInt<64>("h34a8063fd349ee3"), UInt<64>("h49091300aa0a33")) @[Cat.scala 30:58] + node _T_503 = cat(_T_502, _T_501) @[Cat.scala 30:58] + node _T_504 = cat(_T_503, _T_500) @[Cat.scala 30:58] + node _T_505 = cat(_T_504, _T_497) @[Cat.scala 30:58] + node _T_506 = cat(_T_505, _T_490) @[Cat.scala 30:58] + node _T_507 = cat(_T_506, _T_475) @[Cat.scala 30:58] + node _T_508 = cat(_T_507, _T_444) @[Cat.scala 30:58] + node _T_509 = cat(_T_508, _T_381) @[Cat.scala 30:58] + node _T_510 = cat(UInt<64>("h400089300050613"), UInt<64>("h21c000ef000a8513")) @[Cat.scala 30:58] + node _T_511 = cat(UInt<64>("hb851300000073"), UInt<64>("ha859300100513")) @[Cat.scala 30:58] + node _T_512 = cat(_T_511, _T_510) @[Cat.scala 30:58] + node _T_513 = cat(UInt<64>("hc508b30037f793"), UInt<64>("ha5c7b3d69ff0ef")) @[Cat.scala 30:58] + node _T_514 = cat(UInt<64>("h3577930ec7fe63"), UInt<64>("h3007930e079263")) @[Cat.scala 30:58] + node _T_515 = cat(_T_514, _T_513) @[Cat.scala 30:58] + node _T_516 = cat(_T_515, _T_512) @[Cat.scala 30:58] + node _T_517 = cat(UInt<64>("h50713fe080793"), UInt<64>("hffc8f81304079a63")) @[Cat.scala 30:58] + node _T_518 = cat(UInt<64>("h307786300070793"), UInt<64>("h5869306f56663")) @[Cat.scala 30:58] + node _T_519 = cat(_T_518, _T_517) @[Cat.scala 30:58] + node _T_520 = cat(UInt<64>("hfec7ae2300468693"), UInt<64>("h4787930006a603")) @[Cat.scala 30:58] + node _T_521 = cat(UInt<64>("hffc8781301078833"), UInt<64>("hfff74793ff07e8e3")) @[Cat.scala 30:58] + node _T_522 = cat(_T_521, _T_520) @[Cat.scala 30:58] + node _T_523 = cat(_T_522, _T_519) @[Cat.scala 30:58] + node _T_524 = cat(_T_523, _T_516) @[Cat.scala 30:58] + node _T_525 = cat(UInt<64>("h9176863010585b3"), UInt<64>("h107073300480813")) @[Cat.scala 30:58] + node _T_526 = cat(UInt<64>("h1707130005c683"), UInt<64>("h5071300008067")) @[Cat.scala 30:58] + node _T_527 = cat(_T_526, _T_525) @[Cat.scala 30:58] + node _T_528 = cat(UInt<64>("hfe0796e300158593"), UInt<64>("hfed70fa300377793")) @[Cat.scala 30:58] + node _T_529 = cat(UInt<64>("h5a383f8f77ee3"), UInt<64>("hfe080793ffc8f813")) @[Cat.scala 30:58] + node _T_530 = cat(_T_529, _T_528) @[Cat.scala 30:58] + node _T_531 = cat(_T_530, _T_527) @[Cat.scala 30:58] + node _T_532 = cat(UInt<64>("h105ae8300c5af03"), UInt<64>("h85af830045a283")) @[Cat.scala 30:58] + node _T_533 = cat(UInt<64>("h245859301c5a603"), UInt<64>("h185a3030145ae03")) @[Cat.scala 30:58] + node _T_534 = cat(_T_533, _T_532) @[Cat.scala 30:58] + node _T_535 = cat(UInt<64>("hfe572023fc772e23"), UInt<64>("hffc5a68302470713")) @[Cat.scala 30:58] + node _T_536 = cat(UInt<64>("hffc72823ffd72623"), UInt<64>("hffe72423fff72223")) @[Cat.scala 30:58] + node _T_537 = cat(_T_536, _T_535) @[Cat.scala 30:58] + node _T_538 = cat(_T_537, _T_534) @[Cat.scala 30:58] + node _T_539 = cat(_T_538, _T_531) @[Cat.scala 30:58] + node _T_540 = cat(_T_539, _T_524) @[Cat.scala 30:58] + node _T_541 = cat(UInt<64>("hfaf768e3fed72e23"), UInt<64>("hfec72c23fe672a23")) @[Cat.scala 30:58] + node _T_542 = cat(UInt<64>("h5c78303157463"), UInt<64>("h50713f45ff06f")) @[Cat.scala 30:58] + node _T_543 = cat(_T_542, _T_541) @[Cat.scala 30:58] + node _T_544 = cat(UInt<64>("hff1768e3fef70fa3"), UInt<64>("h15859300170713")) @[Cat.scala 30:58] + node _T_545 = cat(UInt<64>("hf55ff06fff1562e3"), UInt<64>("h5071300008067")) @[Cat.scala 30:58] + node _T_546 = cat(_T_545, _T_544) @[Cat.scala 30:58] + node _T_547 = cat(_T_546, _T_543) @[Cat.scala 30:58] + node _T_548 = cat(UInt<64>("h2c87e6300050713"), UInt<64>("hf0081300008067")) @[Cat.scala 30:58] + node _T_549 = cat(UInt<64>("hff06769308059263"), UInt<64>("ha07906300f77793")) @[Cat.scala 30:58] + node _T_550 = cat(_T_549, _T_548) @[Cat.scala 30:58] + node _T_551 = cat(UInt<64>("hb7222300b72023"), UInt<64>("he686b300f67613")) @[Cat.scala 30:58] + node _T_552 = cat(UInt<64>("hfed766e301070713"), UInt<64>("hb7262300b72423")) @[Cat.scala 30:58] + node _T_553 = cat(_T_552, _T_551) @[Cat.scala 30:58] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 30:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 30:58] + node _T_556 = cat(UInt<64>("h26969340c806b3"), UInt<64>("h806700061463")) @[Cat.scala 30:58] + node _T_557 = cat(UInt<64>("hb7072300c68067"), UInt<64>("h5686b300000297")) @[Cat.scala 30:58] + node _T_558 = cat(_T_557, _T_556) @[Cat.scala 30:58] + node _T_559 = cat(UInt<64>("hb7052300b705a3"), UInt<64>("hb7062300b706a3")) @[Cat.scala 30:58] + node _T_560 = cat(UInt<64>("hb7032300b703a3"), UInt<64>("hb7042300b704a3")) @[Cat.scala 30:58] + node _T_561 = cat(_T_560, _T_559) @[Cat.scala 30:58] + node _T_562 = cat(_T_561, _T_558) @[Cat.scala 30:58] + node _T_563 = cat(UInt<64>("hb7012300b701a3"), UInt<64>("hb7022300b702a3")) @[Cat.scala 30:58] + node _T_564 = cat(UInt<64>("hff5f59300008067"), UInt<64>("hb7002300b700a3")) @[Cat.scala 30:58] + node _T_565 = cat(_T_564, _T_563) @[Cat.scala 30:58] + node _T_566 = cat(UInt<64>("hd5e5b301059693"), UInt<64>("hd5e5b300859693")) @[Cat.scala 30:58] + node _T_567 = cat(UInt<64>("h5686b300000297"), UInt<64>("h279693f6dff06f")) @[Cat.scala 30:58] + node _T_568 = cat(_T_567, _T_566) @[Cat.scala 30:58] + node _T_569 = cat(_T_568, _T_565) @[Cat.scala 30:58] + node _T_570 = cat(_T_569, _T_562) @[Cat.scala 30:58] + node _T_571 = cat(_T_570, _T_555) @[Cat.scala 30:58] + node _T_572 = cat(_T_571, _T_540) @[Cat.scala 30:58] + node _T_573 = cat(UInt<64>("hff07879300028093"), UInt<64>("hfa0680e700008293")) @[Cat.scala 30:58] + node _T_574 = cat(UInt<64>("hf3dff06ff6c878e3"), UInt<64>("hf6063340f70733")) @[Cat.scala 30:58] + node _T_575 = cat(_T_574, _T_573) @[Cat.scala 30:58] + node _T_576 = cat(UInt<64>("h7f7f86b704079a63"), UInt<64>("h5059300357793")) @[Cat.scala 30:58] + node _T_577 = cat(UInt<64>("hffc5278300450513"), UInt<64>("hfff00613f7f68693")) @[Cat.scala 30:58] + node _T_578 = cat(_T_577, _T_576) @[Cat.scala 30:58] + node _T_579 = cat(_T_578, _T_575) @[Cat.scala 30:58] + node _T_580 = cat(UInt<64>("hf767b300d7e7b3"), UInt<64>("hd7073300d7f733")) @[Cat.scala 30:58] + node _T_581 = cat(UInt<64>("hffd5468340b507b3"), UInt<64>("hffc54703fec784e3")) @[Cat.scala 30:58] + node _T_582 = cat(_T_581, _T_580) @[Cat.scala 30:58] + node _T_583 = cat(UInt<64>("hfff7851302068863"), UInt<64>("h2070e63ffe54603")) @[Cat.scala 30:58] + node _T_584 = cat(UInt<64>("h54783fa070ae3"), UInt<64>("h806702060c63")) @[Cat.scala 30:58] + node _T_585 = cat(_T_584, _T_583) @[Cat.scala 30:58] + node _T_586 = cat(_T_585, _T_582) @[Cat.scala 30:58] + node _T_587 = cat(_T_586, _T_579) @[Cat.scala 30:58] + node _T_588 = cat(UInt<64>("h40b50533fe0798e3"), UInt<64>("h35771300150513")) @[Cat.scala 30:58] + node _T_589 = cat(UInt<64>("h8067ffd78513"), UInt<64>("h8067fff50513")) @[Cat.scala 30:58] + node _T_590 = cat(_T_589, _T_588) @[Cat.scala 30:58] + node _T_591 = cat(UInt<64>("h8067ffe78513"), UInt<64>("h8067ffc78513")) @[Cat.scala 30:58] + node _T_592 = cat(UInt<64>("h15079302078a63"), UInt<64>("h5478302058e63")) @[Cat.scala 30:58] + node _T_593 = cat(_T_592, _T_591) @[Cat.scala 30:58] + node _T_594 = cat(_T_593, _T_590) @[Cat.scala 30:58] + node _T_595 = cat(UInt<64>("h68c63fff74683"), UInt<64>("h100006f00b505b3")) @[Cat.scala 30:58] + node _T_596 = cat(UInt<64>("h40a58533fef598e3"), UInt<64>("h17871300070793")) @[Cat.scala 30:58] + node _T_597 = cat(_T_596, _T_595) @[Cat.scala 30:58] + node _T_598 = cat(UInt<64>("h51300008067"), UInt<64>("h40a7853300008067")) @[Cat.scala 30:58] + node _T_599 = cat(UInt<64>("h50e1300060893"), UInt<64>("h6831300008067")) @[Cat.scala 30:58] + node _T_600 = cat(_T_599, _T_598) @[Cat.scala 30:58] + node _T_601 = cat(_T_600, _T_597) @[Cat.scala 30:58] + node _T_602 = cat(_T_601, _T_594) @[Cat.scala 30:58] + node _T_603 = cat(_T_602, _T_587) @[Cat.scala 30:58] + node _T_604 = cat(UInt<64>("h107b712c5fc63"), UInt<64>("hc069e6300058813")) @[Cat.scala 30:58] + node _T_605 = cat(UInt<64>("h37979300c7b7b3"), UInt<64>("hff0079322f67e63")) @[Cat.scala 30:58] + node _T_606 = cat(_T_605, _T_604) @[Cat.scala 30:58] + node _T_607 = cat(UInt<64>("he68733e0870713"), UInt<64>("hf656b300002737")) @[Cat.scala 30:58] + node _T_608 = cat(UInt<64>("h40f686b300f707b3"), UInt<64>("h200069300074703")) @[Cat.scala 30:58] + node _T_609 = cat(_T_608, _T_607) @[Cat.scala 30:58] + node _T_610 = cat(_T_609, _T_606) @[Cat.scala 30:58] + node _T_611 = cat(UInt<64>("hd618b300f557b3"), UInt<64>("hd5973300068c63")) @[Cat.scala 30:58] + node _T_612 = cat(UInt<64>("h2c855330108d613"), UInt<64>("hd51e3300e7e833")) @[Cat.scala 30:58] + node _T_613 = cat(_T_612, _T_611) @[Cat.scala 30:58] + node _T_614 = cat(UInt<64>("h2c87733010e5793"), UInt<64>("h106d69301089693")) @[Cat.scala 30:58] + node _T_615 = cat(UInt<64>("hb87c6300e7e833"), UInt<64>("h107171302a685b3")) @[Cat.scala 30:58] + node _T_616 = cat(_T_615, _T_614) @[Cat.scala 30:58] + node _T_617 = cat(_T_616, _T_613) @[Cat.scala 30:58] + node _T_618 = cat(_T_617, _T_610) @[Cat.scala 30:58] + node _T_619 = cat(UInt<64>("h3eb8686301186463"), UInt<64>("hfff5079301180833")) @[Cat.scala 30:58] + node _T_620 = cat(UInt<64>("h10e1e1302c85733"), UInt<64>("h40b8083300078513")) @[Cat.scala 30:58] + node _T_621 = cat(_T_620, _T_619) @[Cat.scala 30:58] + node _T_622 = cat(UInt<64>("h108181302e686b3"), UInt<64>("h2c87833010e5e13")) @[Cat.scala 30:58] + node _T_623 = cat(UInt<64>("hfff7079301088833"), UInt<64>("hd87c63010e6833")) @[Cat.scala 30:58] + node _T_624 = cat(_T_623, _T_622) @[Cat.scala 30:58] + node _T_625 = cat(_T_624, _T_621) @[Cat.scala 30:58] + node _T_626 = cat(UInt<64>("h105151334d87263"), UInt<64>("hffe7071335186663")) @[Cat.scala 30:58] + node _T_627 = cat(UInt<64>("h806700078513"), UInt<64>("h59300e567b3")) @[Cat.scala 30:58] + node _T_628 = cat(_T_627, _T_626) @[Cat.scala 30:58] + node _T_629 = cat(UInt<64>("h100073714f6e263"), UInt<64>("h107b712d5ee63")) @[Cat.scala 30:58] + node _T_630 = cat(UInt<64>("h87771340e00733"), UInt<64>("h17471300e6b733")) @[Cat.scala 30:58] + node _T_631 = cat(_T_630, _T_629) @[Cat.scala 30:58] + node _T_632 = cat(_T_631, _T_628) @[Cat.scala 30:58] + node _T_633 = cat(_T_632, _T_625) @[Cat.scala 30:58] + node _T_634 = cat(_T_633, _T_618) @[Cat.scala 30:58] + node _T_635 = cat(_T_634, _T_603) @[Cat.scala 30:58] + node _T_636 = cat(_T_635, _T_572) @[Cat.scala 30:58] + node _T_637 = cat(UInt<64>("he087879300e6d8b3"), UInt<64>("h27b701070713")) @[Cat.scala 30:58] + node _T_638 = cat(UInt<64>("he7873302000e13"), UInt<64>("h7c78300f887b3")) @[Cat.scala 30:58] + node _T_639 = cat(_T_638, _T_637) @[Cat.scala 30:58] + node _T_640 = cat(UInt<64>("h10079300000593"), UInt<64>("h140e126340ee0e33")) @[Cat.scala 30:58] + node _T_641 = cat(UInt<64>("he80006f0017c793"), UInt<64>("hc537b30f036a63")) @[Cat.scala 30:58] + node _T_642 = cat(_T_641, _T_640) @[Cat.scala 30:58] + node _T_643 = cat(_T_642, _T_639) @[Cat.scala 30:58] + node _T_644 = cat(UInt<64>("h107b702c8d8b3"), UInt<64>("h10089300061663")) @[Cat.scala 30:58] + node _T_645 = cat(UInt<64>("h17c79300f8b7b3"), UInt<64>("h10007b70ef8e663")) @[Cat.scala 30:58] + node _T_646 = cat(_T_645, _T_644) @[Cat.scala 30:58] + node _T_647 = cat(UInt<64>("h273701078793"), UInt<64>("h87f79340f007b3")) @[Cat.scala 30:58] + node _T_648 = cat(UInt<64>("h7430300e68733"), UInt<64>("he087071300f8d6b3")) @[Cat.scala 30:58] + node _T_649 = cat(_T_648, _T_647) @[Cat.scala 30:58] + node _T_650 = cat(_T_649, _T_646) @[Cat.scala 30:58] + node _T_651 = cat(_T_650, _T_643) @[Cat.scala 30:58] + node _T_652 = cat(UInt<64>("h1c0e9663406e8eb3"), UInt<64>("hf3033302000e93")) @[Cat.scala 30:58] + node _T_653 = cat(UInt<64>("h10656130108d693"), UInt<64>("h4115873301089613")) @[Cat.scala 30:58] + node _T_654 = cat(_T_653, _T_652) @[Cat.scala 30:58] + node _T_655 = cat(UInt<64>("h2d7773302d75533"), UInt<64>("h10e581300100593")) @[Cat.scala 30:58] + node _T_656 = cat(UInt<64>("h67fc6300e867b3"), UInt<64>("h107171302c50333")) @[Cat.scala 30:58] + node _T_657 = cat(_T_656, _T_655) @[Cat.scala 30:58] + node _T_658 = cat(_T_657, _T_654) @[Cat.scala 30:58] + node _T_659 = cat(UInt<64>("h2a67e2630117e463"), UInt<64>("hfff50713011787b3")) @[Cat.scala 30:58] + node _T_660 = cat(UInt<64>("h10e1e1302d7d733"), UInt<64>("h406787b300070513")) @[Cat.scala 30:58] + node _T_661 = cat(_T_660, _T_659) @[Cat.scala 30:58] + node _T_662 = cat(UInt<64>("h107979302c70633"), UInt<64>("h2d7f7b3010e5e13")) @[Cat.scala 30:58] + node _T_663 = cat(UInt<64>("hfff7069300f887b3"), UInt<64>("hc7fc6300fe67b3")) @[Cat.scala 30:58] + node _T_664 = cat(_T_663, _T_662) @[Cat.scala 30:58] + node _T_665 = cat(_T_664, _T_661) @[Cat.scala 30:58] + node _T_666 = cat(_T_665, _T_658) @[Cat.scala 30:58] + node _T_667 = cat(_T_666, _T_651) @[Cat.scala 30:58] + node _T_668 = cat(UInt<64>("h10515131ec7fe63"), UInt<64>("hffe707132117e263")) @[Cat.scala 30:58] + node _T_669 = cat(UInt<64>("h59300008067"), UInt<64>("h7851300e567b3")) @[Cat.scala 30:58] + node _T_670 = cat(_T_669, _T_668) @[Cat.scala 30:58] + node _T_671 = cat(UInt<64>("hff0071300008067"), UInt<64>("h7851300000793")) @[Cat.scala 30:58] + node _T_672 = cat(UInt<64>("hff00793ecdff06f"), UInt<64>("h37171300d73733")) @[Cat.scala 30:58] + node _T_673 = cat(_T_672, _T_671) @[Cat.scala 30:58] + node _T_674 = cat(_T_673, _T_670) @[Cat.scala 30:58] + node _T_675 = cat(UInt<64>("h10007b7f25ff06f"), UInt<64>("h3797930117b7b3")) @[Cat.scala 30:58] + node _T_676 = cat(UInt<64>("h87f79340f007b3"), UInt<64>("h17c79300f637b3")) @[Cat.scala 30:58] + node _T_677 = cat(_T_676, _T_675) @[Cat.scala 30:58] + node _T_678 = cat(UInt<64>("h1c696b300e657b3"), UInt<64>("hdbdff06f01078793")) @[Cat.scala 30:58] + node _T_679 = cat(UInt<64>("h3e35eb30106df13"), UInt<64>("he5d33300f6e6b3")) @[Cat.scala 30:58] + node _T_680 = cat(_T_679, _T_678) @[Cat.scala 30:58] + node _T_681 = cat(_T_680, _T_677) @[Cat.scala 30:58] + node _T_682 = cat(_T_681, _T_674) @[Cat.scala 30:58] + node _T_683 = cat(UInt<64>("h1c595b301085813"), UInt<64>("he5573301069813")) @[Cat.scala 30:58] + node _T_684 = cat(UInt<64>("h3e3733301c61633"), UInt<64>("h105d89300b765b3")) @[Cat.scala 30:58] + node _T_685 = cat(_T_684, _T_683) @[Cat.scala 30:58] + node _T_686 = cat(UInt<64>("he8fa630068e8b3"), UInt<64>("h103131303d80733")) @[Cat.scala 30:58] + node _T_687 = cat(UInt<64>("h78e9318d8fc63"), UInt<64>("hfffe879300d888b3")) @[Cat.scala 30:58] + node _T_688 = cat(_T_687, _T_686) @[Cat.scala 30:58] + node _T_689 = cat(_T_688, _T_685) @[Cat.scala 30:58] + node _T_690 = cat(UInt<64>("h105d59301059593"), UInt<64>("h3e8d33340e888b3")) @[Cat.scala 30:58] + node _T_691 = cat(UInt<64>("h115e73301089893"), UInt<64>("h268083303e8f8b3")) @[Cat.scala 30:58] + node _T_692 = cat(_T_691, _T_690) @[Cat.scala 30:58] + node _T_693 = cat(UInt<64>("h14d77a63fff30793"), UInt<64>("hd7073301077a63")) @[Cat.scala 30:58] + node _T_694 = cat(UInt<64>("h6eeeb3000107b7"), UInt<64>("h10e9e9300078313")) @[Cat.scala 30:58] + node _T_695 = cat(_T_694, _T_693) @[Cat.scala 30:58] + node _T_696 = cat(_T_695, _T_692) @[Cat.scala 30:58] + node _T_697 = cat(_T_696, _T_689) @[Cat.scala 30:58] + node _T_698 = cat(_T_697, _T_682) @[Cat.scala 30:58] + node _T_699 = cat(_T_698, _T_667) @[Cat.scala 30:58] + node _T_700 = cat(UInt<64>("hd676b3010ed893"), UInt<64>("hdef5b3fff78693")) @[Cat.scala 30:58] + node _T_701 = cat(UInt<64>("h2d886b341070733"), UInt<64>("h2d5833301065613")) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_700) @[Cat.scala 30:58] + node _T_703 = cat(UInt<64>("hb805b300d585b3"), UInt<64>("h2c585b301035813")) @[Cat.scala 30:58] + node _T_704 = cat(UInt<64>("h105d89300f80833"), UInt<64>("hd5f46302c88833")) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_703) @[Cat.scala 30:58] + node _T_706 = cat(_T_705, _T_702) @[Cat.scala 30:58] + node _T_707 = cat(UInt<64>("he87930d070663"), UInt<64>("hf07686301088833")) @[Cat.scala 30:58] + node _T_708 = cat(UInt<64>("h65d63301d898b3"), UInt<64>("hed1ff06f00000593")) @[Cat.scala 30:58] + node _T_709 = cat(_T_708, _T_707) @[Cat.scala 30:58] + node _T_710 = cat(UInt<64>("h1d5973301089f13"), UInt<64>("h2f658330108d793")) @[Cat.scala 30:58] + node _T_711 = cat(UInt<64>("h103569300e36333"), UInt<64>("h655333010f5f13")) @[Cat.scala 30:58] + node _T_712 = cat(_T_711, _T_710) @[Cat.scala 30:58] + node _T_713 = cat(_T_712, _T_709) @[Cat.scala 30:58] + node _T_714 = cat(_T_713, _T_706) @[Cat.scala 30:58] + node _T_715 = cat(UInt<64>("h1061613030f0733"), UInt<64>("h2f6763301d51e33")) @[Cat.scala 30:58] + node _T_716 = cat(UInt<64>("hfff80613011686b3"), UInt<64>("he6fe6300c6e6b3")) @[Cat.scala 30:58] + node _T_717 = cat(_T_716, _T_715) @[Cat.scala 30:58] + node _T_718 = cat(UInt<64>("h11686b3ffe80813"), UInt<64>("hce6f2630d16e463")) @[Cat.scala 30:58] + node _T_719 = cat(UInt<64>("h103531301031313"), UInt<64>("h2f6d5b340e686b3")) @[Cat.scala 30:58] + node _T_720 = cat(_T_719, _T_718) @[Cat.scala 30:58] + node _T_721 = cat(_T_720, _T_717) @[Cat.scala 30:58] + node _T_722 = cat(UInt<64>("hd3673301069693"), UInt<64>("h2bf063302f6f6b3")) @[Cat.scala 30:58] + node _T_723 = cat(UInt<64>("h9176263fff58693"), UInt<64>("h117073300c77e63")) @[Cat.scala 30:58] + node _T_724 = cat(_T_723, _T_722) @[Cat.scala 30:58] + node _T_725 = cat(UInt<64>("h108181301170733"), UInt<64>("hffe5859308c77063")) @[Cat.scala 30:58] + node _T_726 = cat(UInt<64>("h78693000f0613"), UInt<64>("hb865b340c70733")) @[Cat.scala 30:58] + node _T_727 = cat(_T_726, _T_725) @[Cat.scala 30:58] + node _T_728 = cat(_T_727, _T_724) @[Cat.scala 30:58] + node _T_729 = cat(_T_728, _T_721) @[Cat.scala 30:58] + node _T_730 = cat(_T_729, _T_714) @[Cat.scala 30:58] + node _T_731 = cat(UInt<64>("h78713e05ff06f"), UInt<64>("h68713da5ff06f")) @[Cat.scala 30:58] + node _T_732 = cat(UInt<64>("hd5f5b3fff68693"), UInt<64>("h106b7cbdff06f")) @[Cat.scala 30:58] + node _T_733 = cat(_T_732, _T_731) @[Cat.scala 30:58] + node _T_734 = cat(UInt<64>("hd586b301c51733"), UInt<64>("hd376b301059593")) @[Cat.scala 30:58] + node _T_735 = cat(UInt<64>("hde9ff06f00000593"), UInt<64>("hfffe8793f0d77ee3")) @[Cat.scala 30:58] + node _T_736 = cat(_T_735, _T_734) @[Cat.scala 30:58] + node _T_737 = cat(_T_736, _T_733) @[Cat.scala 30:58] + node _T_738 = cat(UInt<64>("hea9ff06f00d70733"), UInt<64>("hffe30313eb0778e3")) @[Cat.scala 30:58] + node _T_739 = cat(UInt<64>("he65ff06f00d888b3"), UInt<64>("hffee8e93e6e8f6e3")) @[Cat.scala 30:58] + node _T_740 = cat(_T_739, _T_738) @[Cat.scala 30:58] + node _T_741 = cat(UInt<64>("hf45ff06f00060813"), UInt<64>("hf89ff06f00068593")) @[Cat.scala 30:58] + node _T_742 = cat(UInt<64>("hffe50513d5dff06f"), UInt<64>("h11787b3ffe50513")) @[Cat.scala 30:58] + node _T_743 = cat(_T_742, _T_741) @[Cat.scala 30:58] + node _T_744 = cat(_T_743, _T_740) @[Cat.scala 30:58] + node _T_745 = cat(_T_744, _T_737) @[Cat.scala 30:58] + node _T_746 = cat(UInt<64>("h6871300060813"), UInt<64>("hc11ff06f01180833")) @[Cat.scala 30:58] + node _T_747 = cat(UInt<64>("h14c5f2630c069c63"), UInt<64>("h58e1300050893")) @[Cat.scala 30:58] + node _T_748 = cat(_T_747, _T_746) @[Cat.scala 30:58] + node _T_749 = cat(UInt<64>("hf637b3010007b7"), UInt<64>("h20f66863000107b7")) @[Cat.scala 30:58] + node _T_750 = cat(UInt<64>("h10787930087f793"), UInt<64>("h40f007b30017c793")) @[Cat.scala 30:58] + node _T_751 = cat(_T_750, _T_749) @[Cat.scala 30:58] + node _T_752 = cat(_T_751, _T_748) @[Cat.scala 30:58] + node _T_753 = cat(UInt<64>("he68733e0870713"), UInt<64>("hf656b300002737")) @[Cat.scala 30:58] + node _T_754 = cat(UInt<64>("h40f3033300f687b3"), UInt<64>("h200031300074683")) @[Cat.scala 30:58] + node _T_755 = cat(_T_754, _T_753) @[Cat.scala 30:58] + node _T_756 = cat(UInt<64>("h66183300f557b3"), UInt<64>("h6595b300030c63")) @[Cat.scala 30:58] + node _T_757 = cat(UInt<64>("h3de55b301085e93"), UInt<64>("h6518b300b7ee33")) @[Cat.scala 30:58] + node _T_758 = cat(_T_757, _T_756) @[Cat.scala 30:58] + node _T_759 = cat(_T_758, _T_755) @[Cat.scala 30:58] + node _T_760 = cat(_T_759, _T_752) @[Cat.scala 30:58] + node _T_761 = cat(_T_760, _T_745) @[Cat.scala 30:58] + node _T_762 = cat(_T_761, _T_730) @[Cat.scala 30:58] + node _T_763 = cat(_T_762, _T_699) @[Cat.scala 30:58] + node _T_764 = cat(_T_763, _T_636) @[Cat.scala 30:58] + node _T_765 = cat(UInt<64>("h3de76b30108d713"), UInt<64>("h106561301081613")) @[Cat.scala 30:58] + node _T_766 = cat(UInt<64>("hb7786300d76733"), UInt<64>("h106969302b605b3")) @[Cat.scala 30:58] + node _T_767 = cat(_T_766, _T_765) @[Cat.scala 30:58] + node _T_768 = cat(UInt<64>("h40b7073338b76863"), UInt<64>("h107646301070733")) @[Cat.scala 30:58] + node _T_769 = cat(UInt<64>("h3d777330108d893"), UInt<64>("h108989303d757b3")) @[Cat.scala 30:58] + node _T_770 = cat(_T_769, _T_768) @[Cat.scala 30:58] + node _T_771 = cat(_T_770, _T_767) @[Cat.scala 30:58] + node _T_772 = cat(UInt<64>("ha7fa6300e8e7b3"), UInt<64>("h107171302f60533")) @[Cat.scala 30:58] + node _T_773 = cat(UInt<64>("h10787b300a7f463"), UInt<64>("h107e663010787b3")) @[Cat.scala 30:58] + node _T_774 = cat(_T_773, _T_772) @[Cat.scala 30:58] + node _T_775 = cat(UInt<64>("h806700000593"), UInt<64>("h67d53340a787b3")) @[Cat.scala 30:58] + node _T_776 = cat(UInt<64>("h10007b710f6ee63"), UInt<64>("h107b7fed5eee3")) @[Cat.scala 30:58] + node _T_777 = cat(_T_776, _T_775) @[Cat.scala 30:58] + node _T_778 = cat(_T_777, _T_774) @[Cat.scala 30:58] + node _T_779 = cat(_T_778, _T_771) @[Cat.scala 30:58] + node _T_780 = cat(UInt<64>("h87f79340f007b3"), UInt<64>("h17c79300f6b7b3")) @[Cat.scala 30:58] + node _T_781 = cat(UInt<64>("he083031300f6deb3"), UInt<64>("h233701078793")) @[Cat.scala 30:58] + node _T_782 = cat(_T_781, _T_780) @[Cat.scala 30:58] + node _T_783 = cat(UInt<64>("hff0f3302000e93"), UInt<64>("h34f03006e8333")) @[Cat.scala 30:58] + node _T_784 = cat(UInt<64>("h5079301c76663"), UInt<64>("h100e986341ee8eb3")) @[Cat.scala 30:58] + node _T_785 = cat(_T_784, _T_783) @[Cat.scala 30:58] + node _T_786 = cat(_T_785, _T_782) @[Cat.scala 30:58] + node _T_787 = cat(UInt<64>("hf5353340d585b3"), UInt<64>("h40c507b30108ea63")) @[Cat.scala 30:58] + node _T_788 = cat(UInt<64>("h8067000e0593"), UInt<64>("h7851340a58e33")) @[Cat.scala 30:58] + node _T_789 = cat(_T_788, _T_787) @[Cat.scala 30:58] + node _T_790 = cat(UInt<64>("h107b702c85833"), UInt<64>("h10081300061663")) @[Cat.scala 30:58] + node _T_791 = cat(UInt<64>("h17c79300f837b3"), UInt<64>("h10007b70af86a63")) @[Cat.scala 30:58] + node _T_792 = cat(_T_791, _T_790) @[Cat.scala 30:58] + node _T_793 = cat(_T_792, _T_789) @[Cat.scala 30:58] + node _T_794 = cat(_T_793, _T_786) @[Cat.scala 30:58] + node _T_795 = cat(_T_794, _T_779) @[Cat.scala 30:58] + node _T_796 = cat(UInt<64>("h273701078793"), UInt<64>("h87f79340f007b3")) @[Cat.scala 30:58] + node _T_797 = cat(UInt<64>("h7470300e68733"), UInt<64>("he087071300f856b3")) @[Cat.scala 30:58] + node _T_798 = cat(_T_797, _T_796) @[Cat.scala 30:58] + node _T_799 = cat(UInt<64>("h1c03106340f30333"), UInt<64>("hf707b302000313")) @[Cat.scala 30:58] + node _T_800 = cat(UInt<64>("h105551301085693"), UInt<64>("h410585b301081513")) @[Cat.scala 30:58] + node _T_801 = cat(_T_800, _T_799) @[Cat.scala 30:58] + node _T_802 = cat(_T_801, _T_798) @[Cat.scala 30:58] + node _T_803 = cat(UInt<64>("h2a6063302d5f5b3"), UInt<64>("h2d5d6330108d713")) @[Cat.scala 30:58] + node _T_804 = cat(UInt<64>("h107073300c77a63"), UInt<64>("hb7673301059593")) @[Cat.scala 30:58] + node _T_805 = cat(_T_804, _T_803) @[Cat.scala 30:58] + node _T_806 = cat(UInt<64>("h40c7073301070733"), UInt<64>("hc7746301076663")) @[Cat.scala 30:58] + node _T_807 = cat(UInt<64>("h2d777330107d793"), UInt<64>("h108979302d75633")) @[Cat.scala 30:58] + node _T_808 = cat(_T_807, _T_806) @[Cat.scala 30:58] + node _T_809 = cat(_T_808, _T_805) @[Cat.scala 30:58] + node _T_810 = cat(_T_809, _T_802) @[Cat.scala 30:58] + node _T_811 = cat(UInt<64>("heca7fae300e7e7b3"), UInt<64>("h107171302a60533")) @[Cat.scala 30:58] + node _T_812 = cat(UInt<64>("h37979300d7b7b3"), UInt<64>("hff00793ec1ff06f")) @[Cat.scala 30:58] + node _T_813 = cat(_T_812, _T_811) @[Cat.scala 30:58] + node _T_814 = cat(UInt<64>("h3797930107b7b3"), UInt<64>("hff00793ef5ff06f")) @[Cat.scala 30:58] + node _T_815 = cat(UInt<64>("h37979300c7b7b3"), UInt<64>("hff00793f5dff06f")) @[Cat.scala 30:58] + node _T_816 = cat(_T_815, _T_814) @[Cat.scala 30:58] + node _T_817 = cat(_T_816, _T_813) @[Cat.scala 30:58] + node _T_818 = cat(UInt<64>("he6e6b301d696b3"), UInt<64>("h1e65733e01ff06f")) @[Cat.scala 30:58] + node _T_819 = cat(UInt<64>("h106971303f35e33"), UInt<64>("h106df9301e5d333")) @[Cat.scala 30:58] + node _T_820 = cat(_T_819, _T_818) @[Cat.scala 30:58] + node _T_821 = cat(UInt<64>("h1e555b301d59833"), UInt<64>("h1d617b301075713")) @[Cat.scala 30:58] + node _T_822 = cat(UInt<64>("h3f3733301d51533"), UInt<64>("h10858930105e833")) @[Cat.scala 30:58] + node _T_823 = cat(_T_822, _T_821) @[Cat.scala 30:58] + node _T_824 = cat(_T_823, _T_820) @[Cat.scala 30:58] + node _T_825 = cat(_T_824, _T_817) @[Cat.scala 30:58] + node _T_826 = cat(_T_825, _T_810) @[Cat.scala 30:58] + node _T_827 = cat(_T_826, _T_795) @[Cat.scala 30:58] + node _T_828 = cat(UInt<64>("hc8fa630068e8b3"), UInt<64>("h103131303c70633")) @[Cat.scala 30:58] + node _T_829 = cat(UInt<64>("h58e1318d8f863"), UInt<64>("hfffe059300d888b3")) @[Cat.scala 30:58] + node _T_830 = cat(_T_829, _T_828) @[Cat.scala 30:58] + node _T_831 = cat(UInt<64>("h108581301081813"), UInt<64>("h3f8d33340c888b3")) @[Cat.scala 30:58] + node _T_832 = cat(UInt<64>("h118683301089893"), UInt<64>("h267073303f8f8b3")) @[Cat.scala 30:58] + node _T_833 = cat(_T_832, _T_831) @[Cat.scala 30:58] + node _T_834 = cat(_T_833, _T_830) @[Cat.scala 30:58] + node _T_835 = cat(UInt<64>("h14d87663fff30613"), UInt<64>("hd8083300e87a63")) @[Cat.scala 30:58] + node _T_836 = cat(UInt<64>("h6e6333000102b7"), UInt<64>("h10e1e1300060313")) @[Cat.scala 30:58] + node _T_837 = cat(_T_836, _T_835) @[Cat.scala 30:58] + node _T_838 = cat(UInt<64>("hb7f5b301035e13"), UInt<64>("hb37633fff28593")) @[Cat.scala 30:58] + node _T_839 = cat(UInt<64>("h266063340e80733"), UInt<64>("h2b60fb30107d313")) @[Cat.scala 30:58] + node _T_840 = cat(_T_839, _T_838) @[Cat.scala 30:58] + node _T_841 = cat(_T_840, _T_837) @[Cat.scala 30:58] + node _T_842 = cat(_T_841, _T_834) @[Cat.scala 30:58] + node _T_843 = cat(UInt<64>("hc8883300b60633"), UInt<64>("h2be05b3010fd893")) @[Cat.scala 30:58] + node _T_844 = cat(UInt<64>("h1063700530333"), UInt<64>("hb87463026e0333")) @[Cat.scala 30:58] + node _T_845 = cat(_T_844, _T_843) @[Cat.scala 30:58] + node _T_846 = cat(UInt<64>("h108189300b87833"), UInt<64>("h1085613fff60593")) @[Cat.scala 30:58] + node _T_847 = cat(UInt<64>("hc67626301088833"), UInt<64>("hbff83300660333")) @[Cat.scala 30:58] + node _T_848 = cat(_T_847, _T_846) @[Cat.scala 30:58] + node _T_849 = cat(_T_848, _T_845) @[Cat.scala 30:58] + node _T_850 = cat(UInt<64>("h40f507b300080793"), UInt<64>("h4067073310670063")) @[Cat.scala 30:58] + node _T_851 = cat(UInt<64>("h1d7d7b301e71533"), UInt<64>("h40a7073300f53533")) @[Cat.scala 30:58] + node _T_852 = cat(_T_851, _T_850) @[Cat.scala 30:58] + node _T_853 = cat(UInt<64>("h68183300008067"), UInt<64>("h1d755b300f56533")) @[Cat.scala 30:58] + node _T_854 = cat(UInt<64>("h1081e1302e6d633"), UInt<64>("h108571300f5d6b3")) @[Cat.scala 30:58] + node _T_855 = cat(_T_854, _T_853) @[Cat.scala 30:58] + node _T_856 = cat(_T_855, _T_852) @[Cat.scala 30:58] + node _T_857 = cat(_T_856, _T_849) @[Cat.scala 30:58] + node _T_858 = cat(_T_857, _T_842) @[Cat.scala 30:58] + node _T_859 = cat(UInt<64>("hb7e7b300f557b3"), UInt<64>("h10e5e13006595b3")) @[Cat.scala 30:58] + node _T_860 = cat(UInt<64>("h2ce05b302e6f6b3"), UInt<64>("h6518b30107de93")) @[Cat.scala 30:58] + node _T_861 = cat(_T_860, _T_859) @[Cat.scala 30:58] + node _T_862 = cat(UInt<64>("h106063300b67a63"), UInt<64>("hdee63301069693")) @[Cat.scala 30:58] + node _T_863 = cat(UInt<64>("h40b6063301060633"), UInt<64>("hb6746301066663")) @[Cat.scala 30:58] + node _T_864 = cat(_T_863, _T_862) @[Cat.scala 30:58] + node _T_865 = cat(_T_864, _T_861) @[Cat.scala 30:58] + node _T_866 = cat(UInt<64>("h2e676330107d793"), UInt<64>("h107979302e655b3")) @[Cat.scala 30:58] + node _T_867 = cat(UInt<64>("hb6fa6300c7e6b3"), UInt<64>("h106161302be05b3")) @[Cat.scala 30:58] + node _T_868 = cat(_T_867, _T_866) @[Cat.scala 30:58] + node _T_869 = cat(UInt<64>("h10686b300b6f463"), UInt<64>("h106e663010686b3")) @[Cat.scala 30:58] + node _T_870 = cat(UInt<64>("hdc5ff06f00070693"), UInt<64>("he051340b685b3")) @[Cat.scala 30:58] + node _T_871 = cat(_T_870, _T_869) @[Cat.scala 30:58] + node _T_872 = cat(_T_871, _T_868) @[Cat.scala 30:58] + node _T_873 = cat(_T_872, _T_865) @[Cat.scala 30:58] + node _T_874 = cat(UInt<64>("h4106883300f83833"), UInt<64>("h40d306b340f807b3")) @[Cat.scala 30:58] + node _T_875 = cat(UInt<64>("hffe30313eae87ce3"), UInt<64>("hf39ff06f41070733")) @[Cat.scala 30:58] + node _T_876 = cat(_T_875, _T_874) @[Cat.scala 30:58] + node _T_877 = cat(UInt<64>("hffee0e13e6c8fae3"), UInt<64>("heb1ff06f00d80833")) @[Cat.scala 30:58] + node _T_878 = cat(UInt<64>("hc71ff06f01070733"), UInt<64>("he6dff06f00d888b3")) @[Cat.scala 30:58] + node _T_879 = cat(_T_878, _T_877) @[Cat.scala 30:58] + node _T_880 = cat(_T_879, _T_876) @[Cat.scala 30:58] + node _T_881 = cat(UInt<64>("hf01ff06f00000713"), UInt<64>("h80793fd0560e3")) @[Cat.scala 30:58] + node _T_882 = cat(UInt<64>("h27b784030313"), UInt<64>("h81010113fffff337")) @[Cat.scala 30:58] + node _T_883 = cat(_T_882, _T_881) @[Cat.scala 30:58] + node _T_884 = cat(UInt<64>("hffffe6377e912223"), UInt<64>("h7e8124237e112623")) @[Cat.scala 30:58] + node _T_885 = cat(UInt<64>("h6060613002787b3"), UInt<64>("hfa07879300610133")) @[Cat.scala 30:58] + node _T_886 = cat(_T_885, _T_884) @[Cat.scala 30:58] + node _T_887 = cat(_T_886, _T_883) @[Cat.scala 30:58] + node _T_888 = cat(_T_887, _T_880) @[Cat.scala 30:58] + node _T_889 = cat(_T_888, _T_873) @[Cat.scala 30:58] + node _T_890 = cat(_T_889, _T_858) @[Cat.scala 30:58] + node _T_891 = cat(_T_890, _T_827) @[Cat.scala 30:58] + node _T_892 = cat(UInt<64>("h7e80051303c48593"), UInt<64>("h24b700c78433")) @[Cat.scala 30:58] + node _T_893 = cat(UInt<64>("h7e80051300040613"), UInt<64>("h889fe0ef00040613")) @[Cat.scala 30:58] + node _T_894 = cat(_T_893, _T_892) @[Cat.scala 30:58] + node _T_895 = cat(UInt<64>("h40613000047b7"), UInt<64>("h879fe0ef03c48593")) @[Cat.scala 30:58] + node _T_896 = cat(UInt<64>("h626837e800893"), UInt<64>("h513fdc78793")) @[Cat.scala 30:58] + node _T_897 = cat(_T_896, _T_895) @[Cat.scala 30:58] + node _T_898 = cat(_T_897, _T_894) @[Cat.scala 30:58] + node _T_899 = cat(UInt<64>("h2e69e630047a583"), UInt<64>("h4628030007a703")) @[Cat.scala 30:58] + node _T_900 = cat(UInt<64>("h87879300b81863"), UInt<64>("h25051300860613")) @[Cat.scala 30:58] + node _T_901 = cat(_T_900, _T_899) @[Cat.scala 30:58] + node _T_902 = cat(UInt<64>("h7c03031300001337"), UInt<64>("h513fd151ee3")) @[Cat.scala 30:58] + node _T_903 = cat(UInt<64>("h7e4124837e812403"), UInt<64>("h7ec1208300610133")) @[Cat.scala 30:58] + node _T_904 = cat(_T_903, _T_902) @[Cat.scala 30:58] + node _T_905 = cat(_T_904, _T_901) @[Cat.scala 30:58] + node _T_906 = cat(_T_905, _T_898) @[Cat.scala 30:58] + node _T_907 = cat(UInt<64>("hfddff06f00150513"), UInt<64>("h80677f010113")) @[Cat.scala 30:58] + node _T_908 = cat(UInt<64>("hfa05859300100513"), UInt<64>("h4000893000025b7")) @[Cat.scala 30:58] + node _T_909 = cat(_T_908, _T_907) @[Cat.scala 30:58] + node _T_910 = cat(UInt<64>("h8067fff00513"), UInt<64>("h7301700613")) @[Cat.scala 30:58] + node _T_911 = cat(UInt<64>("h9a8000005e0"), UInt<64>("h9a800000680")) @[Cat.scala 30:58] + node _T_912 = cat(_T_911, _T_910) @[Cat.scala 30:58] + node _T_913 = cat(_T_912, _T_909) @[Cat.scala 30:58] + node _T_914 = cat(UInt<64>("h7a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_915 = cat(UInt<64>("h678000007e4"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_916 = cat(_T_915, _T_914) @[Cat.scala 30:58] + node _T_917 = cat(UInt<64>("h7f8000007f8"), UInt<64>("h7d0000009a8")) @[Cat.scala 30:58] + node _T_918 = cat(UInt<64>("h7f8000007f8"), UInt<64>("h7f8000007f8")) @[Cat.scala 30:58] + node _T_919 = cat(_T_918, _T_917) @[Cat.scala 30:58] + node _T_920 = cat(_T_919, _T_916) @[Cat.scala 30:58] + node _T_921 = cat(_T_920, _T_913) @[Cat.scala 30:58] + node _T_922 = cat(_T_921, _T_906) @[Cat.scala 30:58] + node _T_923 = cat(UInt<64>("h9a8000007f8"), UInt<64>("h7f8000007f8")) @[Cat.scala 30:58] + node _T_924 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_925 = cat(_T_924, _T_923) @[Cat.scala 30:58] + node _T_926 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_927 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_928 = cat(_T_927, _T_926) @[Cat.scala 30:58] + node _T_929 = cat(_T_928, _T_925) @[Cat.scala 30:58] + node _T_930 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_931 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_932 = cat(_T_931, _T_930) @[Cat.scala 30:58] + node _T_933 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_934 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_935 = cat(_T_934, _T_933) @[Cat.scala 30:58] + node _T_936 = cat(_T_935, _T_932) @[Cat.scala 30:58] + node _T_937 = cat(_T_936, _T_929) @[Cat.scala 30:58] + node _T_938 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_939 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_940 = cat(_T_939, _T_938) @[Cat.scala 30:58] + node _T_941 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_942 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h93c00000838")) @[Cat.scala 30:58] + node _T_943 = cat(_T_942, _T_941) @[Cat.scala 30:58] + node _T_944 = cat(_T_943, _T_940) @[Cat.scala 30:58] + node _T_945 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9a8000009a8")) @[Cat.scala 30:58] + node _T_946 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h998000009a8")) @[Cat.scala 30:58] + node _T_947 = cat(_T_946, _T_945) @[Cat.scala 30:58] + node _T_948 = cat(UInt<64>("h9a8000009a8"), UInt<64>("h9040000068c")) @[Cat.scala 30:58] + node _T_949 = cat(UInt<64>("h9a8000008ec"), UInt<64>("h9a800000854")) @[Cat.scala 30:58] + node _T_950 = cat(_T_949, _T_948) @[Cat.scala 30:58] + node _T_951 = cat(_T_950, _T_947) @[Cat.scala 30:58] + node _T_952 = cat(_T_951, _T_944) @[Cat.scala 30:58] + node _T_953 = cat(_T_952, _T_937) @[Cat.scala 30:58] + node _T_954 = cat(_T_953, _T_922) @[Cat.scala 30:58] + node _T_955 = cat(UInt<64>("h303030302020100"), UInt<64>("h8f8000009a8")) @[Cat.scala 30:58] + node _T_956 = cat(UInt<64>("h505050505050505"), UInt<64>("h404040404040404")) @[Cat.scala 30:58] + node _T_957 = cat(_T_956, _T_955) @[Cat.scala 30:58] + node _T_958 = cat(UInt<64>("h606060606060606"), UInt<64>("h505050505050505")) @[Cat.scala 30:58] + node _T_959 = cat(UInt<64>("h606060606060606"), UInt<64>("h606060606060606")) @[Cat.scala 30:58] + node _T_960 = cat(_T_959, _T_958) @[Cat.scala 30:58] + node _T_961 = cat(_T_960, _T_957) @[Cat.scala 30:58] + node _T_962 = cat(UInt<64>("h707070707070707"), UInt<64>("h606060606060606")) @[Cat.scala 30:58] + node _T_963 = cat(UInt<64>("h707070707070707"), UInt<64>("h707070707070707")) @[Cat.scala 30:58] + node _T_964 = cat(_T_963, _T_962) @[Cat.scala 30:58] + node _T_965 = cat(UInt<64>("h707070707070707"), UInt<64>("h707070707070707")) @[Cat.scala 30:58] + node _T_966 = cat(UInt<64>("h707070707070707"), UInt<64>("h707070707070707")) @[Cat.scala 30:58] + node _T_967 = cat(_T_966, _T_965) @[Cat.scala 30:58] + node _T_968 = cat(_T_967, _T_964) @[Cat.scala 30:58] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 30:58] + node _T_970 = cat(UInt<64>("h808080808080808"), UInt<64>("h707070707070707")) @[Cat.scala 30:58] + node _T_971 = cat(UInt<64>("h808080808080808"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_972 = cat(_T_971, _T_970) @[Cat.scala 30:58] + node _T_973 = cat(UInt<64>("h808080808080808"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_974 = cat(UInt<64>("h808080808080808"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_975 = cat(_T_974, _T_973) @[Cat.scala 30:58] + node _T_976 = cat(_T_975, _T_972) @[Cat.scala 30:58] + node _T_977 = cat(UInt<64>("h808080808080808"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_978 = cat(UInt<64>("h808080808080808"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_979 = cat(_T_978, _T_977) @[Cat.scala 30:58] + node _T_980 = cat(UInt<64>("h808080808080808"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_981 = cat(UInt<64>("h808080808080808"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_982 = cat(_T_981, _T_980) @[Cat.scala 30:58] + node _T_983 = cat(_T_982, _T_979) @[Cat.scala 30:58] + node _T_984 = cat(_T_983, _T_976) @[Cat.scala 30:58] + node _T_985 = cat(_T_984, _T_969) @[Cat.scala 30:58] + node _T_986 = cat(UInt<64>("h296c6c756e28"), UInt<64>("h808080808080808")) @[Cat.scala 30:58] + node _T_987 = cat(UInt<64>("h74657274736e69"), UInt<64>("h656c637963")) @[Cat.scala 30:58] + node _T_988 = cat(_T_987, _T_986) @[Cat.scala 30:58] + node _T_989 = cat(UInt<64>("h316863726175"), UInt<64>("h306863726175")) @[Cat.scala 30:58] + node _T_990 = cat(UInt<64>("h336863726175"), UInt<64>("h326863726175")) @[Cat.scala 30:58] + node _T_991 = cat(_T_990, _T_989) @[Cat.scala 30:58] + node _T_992 = cat(_T_991, _T_988) @[Cat.scala 30:58] + node _T_993 = cat(UInt<64>("h356863726175"), UInt<64>("h346863726175")) @[Cat.scala 30:58] + node _T_994 = cat(UInt<64>("h376863726175"), UInt<64>("h366863726175")) @[Cat.scala 30:58] + node _T_995 = cat(_T_994, _T_993) @[Cat.scala 30:58] + node _T_996 = cat(UInt<64>("h396863726175"), UInt<64>("h386863726175")) @[Cat.scala 30:58] + node _T_997 = cat(UInt<64>("h31316863726175"), UInt<64>("h30316863726175")) @[Cat.scala 30:58] + node _T_998 = cat(_T_997, _T_996) @[Cat.scala 30:58] + node _T_999 = cat(_T_998, _T_995) @[Cat.scala 30:58] + node _T_1000 = cat(_T_999, _T_992) @[Cat.scala 30:58] + node _T_1001 = cat(UInt<64>("h33316863726175"), UInt<64>("h32316863726175")) @[Cat.scala 30:58] + node _T_1002 = cat(UInt<64>("h35316863726175"), UInt<64>("h34316863726175")) @[Cat.scala 30:58] + node _T_1003 = cat(_T_1002, _T_1001) @[Cat.scala 30:58] + node _T_1004 = cat(UInt<64>("h29286e69616d2074"), UInt<64>("h6e656d656c706d49")) @[Cat.scala 30:58] + node _T_1005 = cat(UInt<64>("ha6425203d207325"), UInt<64>("ha216f6f66202c")) @[Cat.scala 30:58] + node _T_1006 = cat(_T_1005, _T_1004) @[Cat.scala 30:58] + node _T_1007 = cat(_T_1006, _T_1003) @[Cat.scala 30:58] + node _T_1008 = cat(UInt<64>("h527a0100000000"), UInt<64>("h1000000000")) @[Cat.scala 30:58] + node _T_1009 = cat(UInt<64>("h1800000010"), UInt<64>("h20d1b01010401")) @[Cat.scala 30:58] + node _T_1010 = cat(_T_1009, _T_1008) @[Cat.scala 30:58] + node _T_1011 = cat(UInt<64>("h1000000000"), UInt<64>("h120fffff044")) @[Cat.scala 30:58] + node _T_1012 = cat(UInt<64>("h90"), UInt<64>("hfffff22c0000002c")) @[Cat.scala 30:58] + node _T_1013 = cat(_T_1012, _T_1011) @[Cat.scala 30:58] + node _T_1014 = cat(_T_1013, _T_1010) @[Cat.scala 30:58] + node _T_1015 = cat(_T_1014, _T_1007) @[Cat.scala 30:58] + node _T_1016 = cat(_T_1015, _T_1000) @[Cat.scala 30:58] + node _T_1017 = cat(_T_1016, _T_985) @[Cat.scala 30:58] + node _T_1018 = cat(_T_1017, _T_954) @[Cat.scala 30:58] + node _T_1019 = cat(_T_1018, _T_891) @[Cat.scala 30:58] + node _T_1020 = cat(UInt<64>("h44fffff2a8"), UInt<64>("h4000000010")) @[Cat.scala 30:58] + node _T_1021 = cat(UInt<64>("hfffff2d800000054"), UInt<64>("h1000000000")) @[Cat.scala 30:58] + node _T_1022 = cat(_T_1021, _T_1020) @[Cat.scala 30:58] + node _T_1023 = cat(UInt<64>("h6800000010"), UInt<64>("h494")) @[Cat.scala 30:58] + node _T_1024 = cat(UInt<64>("h2900000000"), UInt<64>("h448fffff758")) @[Cat.scala 30:58] + node _T_1025 = cat(_T_1024, _T_1023) @[Cat.scala 30:58] + node _T_1026 = cat(_T_1025, _T_1022) @[Cat.scala 30:58] + node _T_1027 = cat(UInt<64>("h2340000014f"), UInt<64>("h341000001c6")) @[Cat.scala 30:58] + node _T_1028 = cat(UInt<64>("h2ed000003dd"), UInt<64>("hbb00000001")) @[Cat.scala 30:58] + node _T_1029 = cat(_T_1028, _T_1027) @[Cat.scala 30:58] + node _T_1030 = cat(UInt<64>("h840000023c"), UInt<64>("h15e0000016d")) @[Cat.scala 30:58] + node _T_1031 = cat(UInt<64>("h24800000099"), UInt<64>("h3b500000040")) @[Cat.scala 30:58] + node _T_1032 = cat(_T_1031, _T_1030) @[Cat.scala 30:58] + node _T_1033 = cat(_T_1032, _T_1029) @[Cat.scala 30:58] + node _T_1034 = cat(_T_1033, _T_1026) @[Cat.scala 30:58] + node _T_1035 = cat(UInt<64>("h26d0000008c"), UInt<64>("h325000000d8")) @[Cat.scala 30:58] + node _T_1036 = cat(UInt<64>("h3a30000023c"), UInt<64>("h6000000d2")) @[Cat.scala 30:58] + node _T_1037 = cat(_T_1036, _T_1035) @[Cat.scala 30:58] + node _T_1038 = cat(UInt<64>("h18800000251"), UInt<64>("h37a00000153")) @[Cat.scala 30:58] + node _T_1039 = cat(UInt<64>("h3c1000000e4"), UInt<64>("h2b600000382")) @[Cat.scala 30:58] + node _T_1040 = cat(_T_1039, _T_1038) @[Cat.scala 30:58] + node _T_1041 = cat(_T_1040, _T_1037) @[Cat.scala 30:58] + node _T_1042 = cat(UInt<64>("h7400000373"), UInt<64>("h6e0000000c")) @[Cat.scala 30:58] + node _T_1043 = cat(UInt<64>("h1aa00000286"), UInt<64>("h128000002ee")) @[Cat.scala 30:58] + node _T_1044 = cat(_T_1043, _T_1042) @[Cat.scala 30:58] + node _T_1045 = cat(UInt<64>("h293000001b4"), UInt<64>("h13a000001f4")) @[Cat.scala 30:58] + node _T_1046 = cat(UInt<64>("h13f0000032c"), UInt<64>("h306000002bd")) @[Cat.scala 30:58] + node _T_1047 = cat(_T_1046, _T_1045) @[Cat.scala 30:58] + node _T_1048 = cat(_T_1047, _T_1044) @[Cat.scala 30:58] + node _T_1049 = cat(_T_1048, _T_1041) @[Cat.scala 30:58] + node _T_1050 = cat(_T_1049, _T_1034) @[Cat.scala 30:58] + node _T_1051 = cat(UInt<64>("h36b00000096"), UInt<64>("h2a6000003d5")) @[Cat.scala 30:58] + node _T_1052 = cat(UInt<64>("h1da00000234"), UInt<64>("h178000002b8")) @[Cat.scala 30:58] + node _T_1053 = cat(_T_1052, _T_1051) @[Cat.scala 30:58] + node _T_1054 = cat(UInt<64>("h21b00000102"), UInt<64>("h3aa00000110")) @[Cat.scala 30:58] + node _T_1055 = cat(UInt<64>("hcb000001fd"), UInt<64>("h23900000287")) @[Cat.scala 30:58] + node _T_1056 = cat(_T_1055, _T_1054) @[Cat.scala 30:58] + node _T_1057 = cat(_T_1056, _T_1053) @[Cat.scala 30:58] + node _T_1058 = cat(UInt<64>("h2f7000002bf"), UInt<64>("h11800000058")) @[Cat.scala 30:58] + node _T_1059 = cat(UInt<64>("h1ff00000177"), UInt<64>("h25e0000029d")) @[Cat.scala 30:58] + node _T_1060 = cat(_T_1059, _T_1058) @[Cat.scala 30:58] + node _T_1061 = cat(UInt<64>("hc3000003a8"), UInt<64>("h29100000227")) @[Cat.scala 30:58] + node _T_1062 = cat(UInt<64>("h10b00000239"), UInt<64>("h5100000250")) @[Cat.scala 30:58] + node _T_1063 = cat(_T_1062, _T_1061) @[Cat.scala 30:58] + node _T_1064 = cat(_T_1063, _T_1060) @[Cat.scala 30:58] + node _T_1065 = cat(_T_1064, _T_1057) @[Cat.scala 30:58] + node _T_1066 = cat(UInt<64>("h15100000320"), UInt<64>("he5000003b8")) @[Cat.scala 30:58] + node _T_1067 = cat(UInt<64>("h38600000283"), UInt<64>("h3b000000248")) @[Cat.scala 30:58] + node _T_1068 = cat(_T_1067, _T_1066) @[Cat.scala 30:58] + node _T_1069 = cat(UInt<64>("h391000001e9"), UInt<64>("hf100000170")) @[Cat.scala 30:58] + node _T_1070 = cat(UInt<64>("h3a500000139"), UInt<64>("h33a00000148")) @[Cat.scala 30:58] + node _T_1071 = cat(_T_1070, _T_1069) @[Cat.scala 30:58] + node _T_1072 = cat(_T_1071, _T_1068) @[Cat.scala 30:58] + node _T_1073 = cat(UInt<64>("hc300000184"), UInt<64>("h3d900000250")) @[Cat.scala 30:58] + node _T_1074 = cat(UInt<64>("h23600000289"), UInt<64>("h3c00000021f")) @[Cat.scala 30:58] + node _T_1075 = cat(_T_1074, _T_1073) @[Cat.scala 30:58] + node _T_1076 = cat(UInt<64>("h289000003e5"), UInt<64>("h15e000003d3")) @[Cat.scala 30:58] + node _T_1077 = cat(UInt<64>("hb50000004f"), UInt<64>("h2910000032e")) @[Cat.scala 30:58] + node _T_1078 = cat(_T_1077, _T_1076) @[Cat.scala 30:58] + node _T_1079 = cat(_T_1078, _T_1075) @[Cat.scala 30:58] + node _T_1080 = cat(_T_1079, _T_1072) @[Cat.scala 30:58] + node _T_1081 = cat(_T_1080, _T_1065) @[Cat.scala 30:58] + node _T_1082 = cat(_T_1081, _T_1050) @[Cat.scala 30:58] + node _T_1083 = cat(UInt<64>("h35b000003e6"), UInt<64>("h6f000000d0")) @[Cat.scala 30:58] + node _T_1084 = cat(UInt<64>("h1200000034f"), UInt<64>("h4100000275")) @[Cat.scala 30:58] + node _T_1085 = cat(_T_1084, _T_1083) @[Cat.scala 30:58] + node _T_1086 = cat(UInt<64>("h8d000003e5"), UInt<64>("h15d000002c0")) @[Cat.scala 30:58] + node _T_1087 = cat(UInt<64>("h376000002cb"), UInt<64>("h389000000fd")) @[Cat.scala 30:58] + node _T_1088 = cat(_T_1087, _T_1086) @[Cat.scala 30:58] + node _T_1089 = cat(_T_1088, _T_1085) @[Cat.scala 30:58] + node _T_1090 = cat(UInt<64>("h2400000019f"), UInt<64>("h108000001ae")) @[Cat.scala 30:58] + node _T_1091 = cat(UInt<64>("h2f9000002bc"), UInt<64>("h3d30000021a")) @[Cat.scala 30:58] + node _T_1092 = cat(_T_1091, _T_1090) @[Cat.scala 30:58] + node _T_1093 = cat(UInt<64>("h1de000001ee"), UInt<64>("hf100000004")) @[Cat.scala 30:58] + node _T_1094 = cat(UInt<64>("h19300000360"), UInt<64>("h1f300000064")) @[Cat.scala 30:58] + node _T_1095 = cat(_T_1094, _T_1093) @[Cat.scala 30:58] + node _T_1096 = cat(_T_1095, _T_1092) @[Cat.scala 30:58] + node _T_1097 = cat(_T_1096, _T_1089) @[Cat.scala 30:58] + node _T_1098 = cat(UInt<64>("h1bc000001a0"), UInt<64>("hde000002b5")) @[Cat.scala 30:58] + node _T_1099 = cat(UInt<64>("h2a40000011d"), UInt<64>("h2d100000128")) @[Cat.scala 30:58] + node _T_1100 = cat(_T_1099, _T_1098) @[Cat.scala 30:58] + node _T_1101 = cat(UInt<64>("he00000004e"), UInt<64>("h13d0000026c")) @[Cat.scala 30:58] + node _T_1102 = cat(UInt<64>("h1200000021c"), UInt<64>("h3a90000015f")) @[Cat.scala 30:58] + node _T_1103 = cat(_T_1102, _T_1101) @[Cat.scala 30:58] + node _T_1104 = cat(_T_1103, _T_1100) @[Cat.scala 30:58] + node _T_1105 = cat(UInt<64>("h267000000a9"), UInt<64>("h7700000286")) @[Cat.scala 30:58] + node _T_1106 = cat(UInt<64>("h18500000121"), UInt<64>("h25e0000020f")) @[Cat.scala 30:58] + node _T_1107 = cat(_T_1106, _T_1105) @[Cat.scala 30:58] + node _T_1108 = cat(UInt<64>("h1c700000321"), UInt<64>("h15f0000031c")) @[Cat.scala 30:58] + node _T_1109 = cat(UInt<64>("h16f000002f6"), UInt<64>("h116000002d0")) @[Cat.scala 30:58] + node _T_1110 = cat(_T_1109, _T_1108) @[Cat.scala 30:58] + node _T_1111 = cat(_T_1110, _T_1107) @[Cat.scala 30:58] + node _T_1112 = cat(_T_1111, _T_1104) @[Cat.scala 30:58] + node _T_1113 = cat(_T_1112, _T_1097) @[Cat.scala 30:58] + node _T_1114 = cat(UInt<64>("h2480000005c"), UInt<64>("h166000002e9")) @[Cat.scala 30:58] + node _T_1115 = cat(UInt<64>("h3d90000010f"), UInt<64>("h3e000003dd")) @[Cat.scala 30:58] + node _T_1116 = cat(_T_1115, _T_1114) @[Cat.scala 30:58] + node _T_1117 = cat(UInt<64>("h15a00000314"), UInt<64>("h19300000355")) @[Cat.scala 30:58] + node _T_1118 = cat(UInt<64>("h22f000000de"), UInt<64>("h20500000213")) @[Cat.scala 30:58] + node _T_1119 = cat(_T_1118, _T_1117) @[Cat.scala 30:58] + node _T_1120 = cat(_T_1119, _T_1116) @[Cat.scala 30:58] + node _T_1121 = cat(UInt<64>("h307000000f1"), UInt<64>("h38c000001cd")) @[Cat.scala 30:58] + node _T_1122 = cat(UInt<64>("h30a0000014c"), UInt<64>("hff00000166")) @[Cat.scala 30:58] + node _T_1123 = cat(_T_1122, _T_1121) @[Cat.scala 30:58] + node _T_1124 = cat(UInt<64>("h8f000002e4"), UInt<64>("h256000002ac")) @[Cat.scala 30:58] + node _T_1125 = cat(UInt<64>("h7d00000137"), UInt<64>("h21000001be")) @[Cat.scala 30:58] + node _T_1126 = cat(_T_1125, _T_1124) @[Cat.scala 30:58] + node _T_1127 = cat(_T_1126, _T_1123) @[Cat.scala 30:58] + node _T_1128 = cat(_T_1127, _T_1120) @[Cat.scala 30:58] + node _T_1129 = cat(UInt<64>("h3a50000022d"), UInt<64>("h3ad000002e7")) @[Cat.scala 30:58] + node _T_1130 = cat(UInt<64>("h2290000022d"), UInt<64>("h31f000001df")) @[Cat.scala 30:58] + node _T_1131 = cat(_T_1130, _T_1129) @[Cat.scala 30:58] + node _T_1132 = cat(UInt<64>("h2880000031c"), UInt<64>("h1af0000039d")) @[Cat.scala 30:58] + node _T_1133 = cat(UInt<64>("h11f0000037b"), UInt<64>("h3b800000165")) @[Cat.scala 30:58] + node _T_1134 = cat(_T_1133, _T_1132) @[Cat.scala 30:58] + node _T_1135 = cat(_T_1134, _T_1131) @[Cat.scala 30:58] + node _T_1136 = cat(UInt<64>("h3100000202"), UInt<64>("h130000029a")) @[Cat.scala 30:58] + node _T_1137 = cat(UInt<64>("h5f00000366"), UInt<64>("h560000022d")) @[Cat.scala 30:58] + node _T_1138 = cat(_T_1137, _T_1136) @[Cat.scala 30:58] + node _T_1139 = cat(UInt<64>("h24b000001b8"), UInt<64>("h1b900000355")) @[Cat.scala 30:58] + node _T_1140 = cat(UInt<64>("h17e000002a6"), UInt<64>("h2660000003d")) @[Cat.scala 30:58] + node _T_1141 = cat(_T_1140, _T_1139) @[Cat.scala 30:58] + node _T_1142 = cat(_T_1141, _T_1138) @[Cat.scala 30:58] + node _T_1143 = cat(_T_1142, _T_1135) @[Cat.scala 30:58] + node _T_1144 = cat(_T_1143, _T_1128) @[Cat.scala 30:58] + node _T_1145 = cat(_T_1144, _T_1113) @[Cat.scala 30:58] + node _T_1146 = cat(_T_1145, _T_1082) @[Cat.scala 30:58] + node _T_1147 = cat(UInt<64>("h32800000009"), UInt<64>("h1180000018c")) @[Cat.scala 30:58] + node _T_1148 = cat(UInt<64>("h333000000aa"), UInt<64>("h3cb00000011")) @[Cat.scala 30:58] + node _T_1149 = cat(_T_1148, _T_1147) @[Cat.scala 30:58] + node _T_1150 = cat(UInt<64>("h1c20000017c"), UInt<64>("h15800000123")) @[Cat.scala 30:58] + node _T_1151 = cat(UInt<64>("h3c5000000b9"), UInt<64>("h20000000218")) @[Cat.scala 30:58] + node _T_1152 = cat(_T_1151, _T_1150) @[Cat.scala 30:58] + node _T_1153 = cat(_T_1152, _T_1149) @[Cat.scala 30:58] + node _T_1154 = cat(UInt<64>("h3280000021b"), UInt<64>("h15b00000395")) @[Cat.scala 30:58] + node _T_1155 = cat(UInt<64>("h21900000377"), UInt<64>("h372000003d7")) @[Cat.scala 30:58] + node _T_1156 = cat(_T_1155, _T_1154) @[Cat.scala 30:58] + node _T_1157 = cat(UInt<64>("h2bd00000264"), UInt<64>("h3b200000036")) @[Cat.scala 30:58] + node _T_1158 = cat(UInt<64>("h237000001df"), UInt<64>("h164000003b7")) @[Cat.scala 30:58] + node _T_1159 = cat(_T_1158, _T_1157) @[Cat.scala 30:58] + node _T_1160 = cat(_T_1159, _T_1156) @[Cat.scala 30:58] + node _T_1161 = cat(_T_1160, _T_1153) @[Cat.scala 30:58] + node _T_1162 = cat(UInt<64>("h1600000007"), UInt<64>("h37b00000097")) @[Cat.scala 30:58] + node _T_1163 = cat(UInt<64>("h2990000014f"), UInt<64>("h23800000281")) @[Cat.scala 30:58] + node _T_1164 = cat(_T_1163, _T_1162) @[Cat.scala 30:58] + node _T_1165 = cat(UInt<64>("h1b20000005f"), UInt<64>("h1a7000002da")) @[Cat.scala 30:58] + node _T_1166 = cat(UInt<64>("h200000118"), UInt<64>("h9e000002d8")) @[Cat.scala 30:58] + node _T_1167 = cat(_T_1166, _T_1165) @[Cat.scala 30:58] + node _T_1168 = cat(_T_1167, _T_1164) @[Cat.scala 30:58] + node _T_1169 = cat(UInt<64>("hf7000002b0"), UInt<64>("h540000018b")) @[Cat.scala 30:58] + node _T_1170 = cat(UInt<64>("h1b3000001dc"), UInt<64>("h310000038f")) @[Cat.scala 30:58] + node _T_1171 = cat(_T_1170, _T_1169) @[Cat.scala 30:58] + node _T_1172 = cat(UInt<64>("h365000002d9"), UInt<64>("h3180000032f")) @[Cat.scala 30:58] + node _T_1173 = cat(UInt<64>("h19e0000007f"), UInt<64>("h1e600000109")) @[Cat.scala 30:58] + node _T_1174 = cat(_T_1173, _T_1172) @[Cat.scala 30:58] + node _T_1175 = cat(_T_1174, _T_1171) @[Cat.scala 30:58] + node _T_1176 = cat(_T_1175, _T_1168) @[Cat.scala 30:58] + node _T_1177 = cat(_T_1176, _T_1161) @[Cat.scala 30:58] + node _T_1178 = cat(UInt<64>("h224000000d6"), UInt<64>("h171000000ec")) @[Cat.scala 30:58] + node _T_1179 = cat(UInt<64>("h37800000006"), UInt<64>("h206000000b4")) @[Cat.scala 30:58] + node _T_1180 = cat(_T_1179, _T_1178) @[Cat.scala 30:58] + node _T_1181 = cat(UInt<64>("h11c00000254"), UInt<64>("h2aa000001f7")) @[Cat.scala 30:58] + node _T_1182 = cat(UInt<64>("h1f300000283"), UInt<64>("h108000000ad")) @[Cat.scala 30:58] + node _T_1183 = cat(_T_1182, _T_1181) @[Cat.scala 30:58] + node _T_1184 = cat(_T_1183, _T_1180) @[Cat.scala 30:58] + node _T_1185 = cat(UInt<64>("h38100000257"), UInt<64>("h1220000015a")) @[Cat.scala 30:58] + node _T_1186 = cat(UInt<64>("h2db00000351"), UInt<64>("hd700000044")) @[Cat.scala 30:58] + node _T_1187 = cat(_T_1186, _T_1185) @[Cat.scala 30:58] + node _T_1188 = cat(UInt<64>("hfb0000026b"), UInt<64>("h2b000000292")) @[Cat.scala 30:58] + node _T_1189 = cat(UInt<64>("h22b00000083"), UInt<64>("h31200000079")) @[Cat.scala 30:58] + node _T_1190 = cat(_T_1189, _T_1188) @[Cat.scala 30:58] + node _T_1191 = cat(_T_1190, _T_1187) @[Cat.scala 30:58] + node _T_1192 = cat(_T_1191, _T_1184) @[Cat.scala 30:58] + node _T_1193 = cat(UInt<64>("h2100000029b"), UInt<64>("h12e0000033c")) @[Cat.scala 30:58] + node _T_1194 = cat(UInt<64>("h142000001e7"), UInt<64>("h220000001b1")) @[Cat.scala 30:58] + node _T_1195 = cat(_T_1194, _T_1193) @[Cat.scala 30:58] + node _T_1196 = cat(UInt<64>("h11f0000007d"), UInt<64>("h3b3000002f1")) @[Cat.scala 30:58] + node _T_1197 = cat(UInt<64>("h1300000000e"), UInt<64>("h33800000272")) @[Cat.scala 30:58] + node _T_1198 = cat(_T_1197, _T_1196) @[Cat.scala 30:58] + node _T_1199 = cat(_T_1198, _T_1195) @[Cat.scala 30:58] + node _T_1200 = cat(UInt<64>("h2dd00000193"), UInt<64>("h3140000000a")) @[Cat.scala 30:58] + node _T_1201 = cat(UInt<64>("h16e000002bf"), UInt<64>("h3bf0000006a")) @[Cat.scala 30:58] + node _T_1202 = cat(_T_1201, _T_1200) @[Cat.scala 30:58] + node _T_1203 = cat(UInt<64>("h126000003c4"), UInt<64>("h2d200000332")) @[Cat.scala 30:58] + node _T_1204 = cat(UInt<64>("h28d0000036a"), UInt<64>("h3cf00000196")) @[Cat.scala 30:58] + node _T_1205 = cat(_T_1204, _T_1203) @[Cat.scala 30:58] + node _T_1206 = cat(_T_1205, _T_1202) @[Cat.scala 30:58] + node _T_1207 = cat(_T_1206, _T_1199) @[Cat.scala 30:58] + node _T_1208 = cat(_T_1207, _T_1192) @[Cat.scala 30:58] + node _T_1209 = cat(_T_1208, _T_1177) @[Cat.scala 30:58] + node _T_1210 = cat(UInt<64>("h5b00000056"), UInt<64>("h2ec00000358")) @[Cat.scala 30:58] + node _T_1211 = cat(UInt<64>("h6900000294"), UInt<64>("h17a0000003c")) @[Cat.scala 30:58] + node _T_1212 = cat(_T_1211, _T_1210) @[Cat.scala 30:58] + node _T_1213 = cat(UInt<64>("h17d00000099"), UInt<64>("h660000029b")) @[Cat.scala 30:58] + node _T_1214 = cat(UInt<64>("h33900000062"), UInt<64>("h28b00000079")) @[Cat.scala 30:58] + node _T_1215 = cat(_T_1214, _T_1213) @[Cat.scala 30:58] + node _T_1216 = cat(_T_1215, _T_1212) @[Cat.scala 30:58] + node _T_1217 = cat(UInt<64>("h164000000ec"), UInt<64>("h3480000019c")) @[Cat.scala 30:58] + node _T_1218 = cat(UInt<64>("h36000001a7"), UInt<64>("h940000000c")) @[Cat.scala 30:58] + node _T_1219 = cat(_T_1218, _T_1217) @[Cat.scala 30:58] + node _T_1220 = cat(UInt<64>("h3bb000000d8"), UInt<64>("h8c000003c5")) @[Cat.scala 30:58] + node _T_1221 = cat(UInt<64>("h21500000169"), UInt<64>("h1570000026d")) @[Cat.scala 30:58] + node _T_1222 = cat(_T_1221, _T_1220) @[Cat.scala 30:58] + node _T_1223 = cat(_T_1222, _T_1219) @[Cat.scala 30:58] + node _T_1224 = cat(_T_1223, _T_1216) @[Cat.scala 30:58] + node _T_1225 = cat(UInt<64>("h209000002cb"), UInt<64>("h2f500000399")) @[Cat.scala 30:58] + node _T_1226 = cat(UInt<64>("h2500000012b"), UInt<64>("h34500000287")) @[Cat.scala 30:58] + node _T_1227 = cat(_T_1226, _T_1225) @[Cat.scala 30:58] + node _T_1228 = cat(UInt<64>("had000002aa"), UInt<64>("hd00000376")) @[Cat.scala 30:58] + node _T_1229 = cat(UInt<64>("h79000001ed"), UInt<64>("h3f00000024")) @[Cat.scala 30:58] + node _T_1230 = cat(_T_1229, _T_1228) @[Cat.scala 30:58] + node _T_1231 = cat(_T_1230, _T_1227) @[Cat.scala 30:58] + node _T_1232 = cat(UInt<64>("h2f600000219"), UInt<64>("h8500000227")) @[Cat.scala 30:58] + node _T_1233 = cat(UInt<64>("h3b700000283"), UInt<64>("h174000003c9")) @[Cat.scala 30:58] + node _T_1234 = cat(_T_1233, _T_1232) @[Cat.scala 30:58] + node _T_1235 = cat(UInt<64>("h810000019f"), UInt<64>("h27000001b2")) @[Cat.scala 30:58] + node _T_1236 = cat(UInt<64>("h34f000001b6"), UInt<64>("h6e0000012f")) @[Cat.scala 30:58] + node _T_1237 = cat(_T_1236, _T_1235) @[Cat.scala 30:58] + node _T_1238 = cat(_T_1237, _T_1234) @[Cat.scala 30:58] + node _T_1239 = cat(_T_1238, _T_1231) @[Cat.scala 30:58] + node _T_1240 = cat(_T_1239, _T_1224) @[Cat.scala 30:58] + node _T_1241 = cat(UInt<64>("hff000000cb"), UInt<64>("h1b50000035c")) @[Cat.scala 30:58] + node _T_1242 = cat(UInt<64>("h199000003dc"), UInt<64>("h10d000001de")) @[Cat.scala 30:58] + node _T_1243 = cat(_T_1242, _T_1241) @[Cat.scala 30:58] + node _T_1244 = cat(UInt<64>("h18f000002cf"), UInt<64>("h274000002a3")) @[Cat.scala 30:58] + node _T_1245 = cat(UInt<64>("h2f100000152"), UInt<64>("h225000003de")) @[Cat.scala 30:58] + node _T_1246 = cat(_T_1245, _T_1244) @[Cat.scala 30:58] + node _T_1247 = cat(_T_1246, _T_1243) @[Cat.scala 30:58] + node _T_1248 = cat(UInt<64>("hab00000279"), UInt<64>("h234000001c2")) @[Cat.scala 30:58] + node _T_1249 = cat(UInt<64>("h2d700000286"), UInt<64>("h130000009b")) @[Cat.scala 30:58] + node _T_1250 = cat(_T_1249, _T_1248) @[Cat.scala 30:58] + node _T_1251 = cat(UInt<64>("h309000001ab"), UInt<64>("h1f5000001c4")) @[Cat.scala 30:58] + node _T_1252 = cat(UInt<64>("h2f1000003dc"), UInt<64>("h2b000001fd")) @[Cat.scala 30:58] + node _T_1253 = cat(_T_1252, _T_1251) @[Cat.scala 30:58] + node _T_1254 = cat(_T_1253, _T_1250) @[Cat.scala 30:58] + node _T_1255 = cat(_T_1254, _T_1247) @[Cat.scala 30:58] + node _T_1256 = cat(UInt<64>("hca0000000c"), UInt<64>("h51000001aa")) @[Cat.scala 30:58] + node _T_1257 = cat(UInt<64>("h990000008e"), UInt<64>("h355000001e3")) @[Cat.scala 30:58] + node _T_1258 = cat(_T_1257, _T_1256) @[Cat.scala 30:58] + node _T_1259 = cat(UInt<64>("h16500000186"), UInt<64>("h2f800000153")) @[Cat.scala 30:58] + node _T_1260 = cat(UInt<64>("h39a000000ab"), UInt<64>("h3af00000032")) @[Cat.scala 30:58] + node _T_1261 = cat(_T_1260, _T_1259) @[Cat.scala 30:58] + node _T_1262 = cat(_T_1261, _T_1258) @[Cat.scala 30:58] + node _T_1263 = cat(UInt<64>("h1f000000069"), UInt<64>("h14800000259")) @[Cat.scala 30:58] + node _T_1264 = cat(UInt<64>("h20400000079"), UInt<64>("h1ba000003c8")) @[Cat.scala 30:58] + node _T_1265 = cat(_T_1264, _T_1263) @[Cat.scala 30:58] + node _T_1266 = cat(UInt<64>("h11400000051"), UInt<64>("h2810000036f")) @[Cat.scala 30:58] + node _T_1267 = cat(UInt<64>("h7100000258"), UInt<64>("h31200000366")) @[Cat.scala 30:58] + node _T_1268 = cat(_T_1267, _T_1266) @[Cat.scala 30:58] + node _T_1269 = cat(_T_1268, _T_1265) @[Cat.scala 30:58] + node _T_1270 = cat(_T_1269, _T_1262) @[Cat.scala 30:58] + node _T_1271 = cat(_T_1270, _T_1255) @[Cat.scala 30:58] + node _T_1272 = cat(_T_1271, _T_1240) @[Cat.scala 30:58] + node _T_1273 = cat(_T_1272, _T_1209) @[Cat.scala 30:58] + node _T_1274 = cat(_T_1273, _T_1146) @[Cat.scala 30:58] + node _T_1275 = cat(UInt<64>("h38b00000367"), UInt<64>("h34a0000025b")) @[Cat.scala 30:58] + node _T_1276 = cat(UInt<64>("hed00000262"), UInt<64>("h11300000377")) @[Cat.scala 30:58] + node _T_1277 = cat(_T_1276, _T_1275) @[Cat.scala 30:58] + node _T_1278 = cat(UInt<64>("h310000000ea"), UInt<64>("h2000000194")) @[Cat.scala 30:58] + node _T_1279 = cat(UInt<64>("h1650000020e"), UInt<64>("h235000002e9")) @[Cat.scala 30:58] + node _T_1280 = cat(_T_1279, _T_1278) @[Cat.scala 30:58] + node _T_1281 = cat(_T_1280, _T_1277) @[Cat.scala 30:58] + node _T_1282 = cat(UInt<64>("h333000001b9"), UInt<64>("h32300000113")) @[Cat.scala 30:58] + node _T_1283 = cat(UInt<64>("h118000002f0"), UInt<64>("h2ef000000e2")) @[Cat.scala 30:58] + node _T_1284 = cat(_T_1283, _T_1282) @[Cat.scala 30:58] + node _T_1285 = cat(UInt<64>("h1ca000002d6"), UInt<64>("h55000003af")) @[Cat.scala 30:58] + node _T_1286 = cat(UInt<64>("h2c6000000c9"), UInt<64>("h1c6000002c5")) @[Cat.scala 30:58] + node _T_1287 = cat(_T_1286, _T_1285) @[Cat.scala 30:58] + node _T_1288 = cat(_T_1287, _T_1284) @[Cat.scala 30:58] + node _T_1289 = cat(_T_1288, _T_1281) @[Cat.scala 30:58] + node _T_1290 = cat(UInt<64>("h29000002f6"), UInt<64>("h1cb00000036")) @[Cat.scala 30:58] + node _T_1291 = cat(UInt<64>("h1790000018d"), UInt<64>("hfd00000035")) @[Cat.scala 30:58] + node _T_1292 = cat(_T_1291, _T_1290) @[Cat.scala 30:58] + node _T_1293 = cat(UInt<64>("h2bc0000008d"), UInt<64>("h1fc00000029")) @[Cat.scala 30:58] + node _T_1294 = cat(UInt<64>("h1e0000002eb"), UInt<64>("h35c000001a0")) @[Cat.scala 30:58] + node _T_1295 = cat(_T_1294, _T_1293) @[Cat.scala 30:58] + node _T_1296 = cat(_T_1295, _T_1292) @[Cat.scala 30:58] + node _T_1297 = cat(UInt<64>("h1f3000001de"), UInt<64>("h2e5000000db")) @[Cat.scala 30:58] + node _T_1298 = cat(UInt<64>("h31000000b4"), UInt<64>("h2c500000302")) @[Cat.scala 30:58] + node _T_1299 = cat(_T_1298, _T_1297) @[Cat.scala 30:58] + node _T_1300 = cat(UInt<64>("h369000002b3"), UInt<64>("h173000001e2")) @[Cat.scala 30:58] + node _T_1301 = cat(UInt<64>("h3e0000000ad"), UInt<64>("h3b1000002d5")) @[Cat.scala 30:58] + node _T_1302 = cat(_T_1301, _T_1300) @[Cat.scala 30:58] + node _T_1303 = cat(_T_1302, _T_1299) @[Cat.scala 30:58] + node _T_1304 = cat(_T_1303, _T_1296) @[Cat.scala 30:58] + node _T_1305 = cat(_T_1304, _T_1289) @[Cat.scala 30:58] + node _T_1306 = cat(UInt<64>("h2d100000392"), UInt<64>("h20e000000ba")) @[Cat.scala 30:58] + node _T_1307 = cat(UInt<64>("he8000003c3"), UInt<64>("h1b300000001")) @[Cat.scala 30:58] + node _T_1308 = cat(_T_1307, _T_1306) @[Cat.scala 30:58] + node _T_1309 = cat(UInt<64>("h2b9000001d0"), UInt<64>("h1f1000000f7")) @[Cat.scala 30:58] + node _T_1310 = cat(UInt<64>("h15c00000209"), UInt<64>("h1e0000016a")) @[Cat.scala 30:58] + node _T_1311 = cat(_T_1310, _T_1309) @[Cat.scala 30:58] + node _T_1312 = cat(_T_1311, _T_1308) @[Cat.scala 30:58] + node _T_1313 = cat(UInt<64>("h15e00000078"), UInt<64>("hfa000000e9")) @[Cat.scala 30:58] + node _T_1314 = cat(UInt<64>("h23d0000030b"), UInt<64>("hfa00000028")) @[Cat.scala 30:58] + node _T_1315 = cat(_T_1314, _T_1313) @[Cat.scala 30:58] + node _T_1316 = cat(UInt<64>("h2ed000000a1"), UInt<64>("h310000000c3")) @[Cat.scala 30:58] + node _T_1317 = cat(UInt<64>("h337000001b7"), UInt<64>("h1f6000002e7")) @[Cat.scala 30:58] + node _T_1318 = cat(_T_1317, _T_1316) @[Cat.scala 30:58] + node _T_1319 = cat(_T_1318, _T_1315) @[Cat.scala 30:58] + node _T_1320 = cat(_T_1319, _T_1312) @[Cat.scala 30:58] + node _T_1321 = cat(UInt<64>("haa00000193"), UInt<64>("h33a00000163")) @[Cat.scala 30:58] + node _T_1322 = cat(UInt<64>("h2a200000279"), UInt<64>("ha00000008d")) @[Cat.scala 30:58] + node _T_1323 = cat(_T_1322, _T_1321) @[Cat.scala 30:58] + node _T_1324 = cat(UInt<64>("hca0000030e"), UInt<64>("h2000000121")) @[Cat.scala 30:58] + node _T_1325 = cat(UInt<64>("h3550000027c"), UInt<64>("h8f00000140")) @[Cat.scala 30:58] + node _T_1326 = cat(_T_1325, _T_1324) @[Cat.scala 30:58] + node _T_1327 = cat(_T_1326, _T_1323) @[Cat.scala 30:58] + node _T_1328 = cat(UInt<64>("h18a00000354"), UInt<64>("h5a00000076")) @[Cat.scala 30:58] + node _T_1329 = cat(UInt<64>("h35700000330"), UInt<64>("h6b00000046")) @[Cat.scala 30:58] + node _T_1330 = cat(_T_1329, _T_1328) @[Cat.scala 30:58] + node _T_1331 = cat(UInt<64>("h9d000003ba"), UInt<64>("h6a00000184")) @[Cat.scala 30:58] + node _T_1332 = cat(UInt<64>("h2fd00000010"), UInt<64>("h600000024")) @[Cat.scala 30:58] + node _T_1333 = cat(_T_1332, _T_1331) @[Cat.scala 30:58] + node _T_1334 = cat(_T_1333, _T_1330) @[Cat.scala 30:58] + node _T_1335 = cat(_T_1334, _T_1327) @[Cat.scala 30:58] + node _T_1336 = cat(_T_1335, _T_1320) @[Cat.scala 30:58] + node _T_1337 = cat(_T_1336, _T_1305) @[Cat.scala 30:58] + node _T_1338 = cat(UInt<64>("hc2000002b7"), UInt<64>("hcc000002ba")) @[Cat.scala 30:58] + node _T_1339 = cat(UInt<64>("hda00000256"), UInt<64>("h23e000002a5")) @[Cat.scala 30:58] + node _T_1340 = cat(_T_1339, _T_1338) @[Cat.scala 30:58] + node _T_1341 = cat(UInt<64>("hb100000338"), UInt<64>("h20e00000373")) @[Cat.scala 30:58] + node _T_1342 = cat(UInt<64>("h2ba000001ce"), UInt<64>("hef000002ea")) @[Cat.scala 30:58] + node _T_1343 = cat(_T_1342, _T_1341) @[Cat.scala 30:58] + node _T_1344 = cat(_T_1343, _T_1340) @[Cat.scala 30:58] + node _T_1345 = cat(UInt<64>("h2c200000216"), UInt<64>("h2f5000001ff")) @[Cat.scala 30:58] + node _T_1346 = cat(UInt<64>("h54000001ac"), UInt<64>("h31000001b8")) @[Cat.scala 30:58] + node _T_1347 = cat(_T_1346, _T_1345) @[Cat.scala 30:58] + node _T_1348 = cat(UInt<64>("h37d000002d6"), UInt<64>("h31f000002dc")) @[Cat.scala 30:58] + node _T_1349 = cat(UInt<64>("h17500000223"), UInt<64>("h200000002be")) @[Cat.scala 30:58] + node _T_1350 = cat(_T_1349, _T_1348) @[Cat.scala 30:58] + node _T_1351 = cat(_T_1350, _T_1347) @[Cat.scala 30:58] + node _T_1352 = cat(_T_1351, _T_1344) @[Cat.scala 30:58] + node _T_1353 = cat(UInt<64>("he0000031e"), UInt<64>("h1ec00000056")) @[Cat.scala 30:58] + node _T_1354 = cat(UInt<64>("h5300000015"), UInt<64>("h26d000000d7")) @[Cat.scala 30:58] + node _T_1355 = cat(_T_1354, _T_1353) @[Cat.scala 30:58] + node _T_1356 = cat(UInt<64>("h31a0000003b"), UInt<64>("h670000028b")) @[Cat.scala 30:58] + node _T_1357 = cat(UInt<64>("h28300000291"), UInt<64>("h399000001ad")) @[Cat.scala 30:58] + node _T_1358 = cat(_T_1357, _T_1356) @[Cat.scala 30:58] + node _T_1359 = cat(_T_1358, _T_1355) @[Cat.scala 30:58] + node _T_1360 = cat(UInt<64>("h342000003cd"), UInt<64>("h37000000060")) @[Cat.scala 30:58] + node _T_1361 = cat(UInt<64>("h1ce000003c6"), UInt<64>("hef00000293")) @[Cat.scala 30:58] + node _T_1362 = cat(_T_1361, _T_1360) @[Cat.scala 30:58] + node _T_1363 = cat(UInt<64>("h2310000003e"), UInt<64>("h720000020c")) @[Cat.scala 30:58] + node _T_1364 = cat(UInt<64>("ha0000012f"), UInt<64>("h21100000271")) @[Cat.scala 30:58] + node _T_1365 = cat(_T_1364, _T_1363) @[Cat.scala 30:58] + node _T_1366 = cat(_T_1365, _T_1362) @[Cat.scala 30:58] + node _T_1367 = cat(_T_1366, _T_1359) @[Cat.scala 30:58] + node _T_1368 = cat(_T_1367, _T_1352) @[Cat.scala 30:58] + node _T_1369 = cat(UInt<64>("h38800000199"), UInt<64>("h3e5000002ca")) @[Cat.scala 30:58] + node _T_1370 = cat(UInt<64>("h197000002d8"), UInt<64>("h18300000037")) @[Cat.scala 30:58] + node _T_1371 = cat(_T_1370, _T_1369) @[Cat.scala 30:58] + node _T_1372 = cat(UInt<64>("h22f000001b4"), UInt<64>("h6900000131")) @[Cat.scala 30:58] + node _T_1373 = cat(UInt<64>("h20000000250"), UInt<64>("h3a800000385")) @[Cat.scala 30:58] + node _T_1374 = cat(_T_1373, _T_1372) @[Cat.scala 30:58] + node _T_1375 = cat(_T_1374, _T_1371) @[Cat.scala 30:58] + node _T_1376 = cat(UInt<64>("h12e0000031c"), UInt<64>("h199000002b3")) @[Cat.scala 30:58] + node _T_1377 = cat(UInt<64>("h1ab000000b1"), UInt<64>("hca000001f1")) @[Cat.scala 30:58] + node _T_1378 = cat(_T_1377, _T_1376) @[Cat.scala 30:58] + node _T_1379 = cat(UInt<64>("h167000003e3"), UInt<64>("h265000003ac")) @[Cat.scala 30:58] + node _T_1380 = cat(UInt<64>("h2ac0000009e"), UInt<64>("h209000001e0")) @[Cat.scala 30:58] + node _T_1381 = cat(_T_1380, _T_1379) @[Cat.scala 30:58] + node _T_1382 = cat(_T_1381, _T_1378) @[Cat.scala 30:58] + node _T_1383 = cat(_T_1382, _T_1375) @[Cat.scala 30:58] + node _T_1384 = cat(UInt<64>("hb900000263"), UInt<64>("h1600000336")) @[Cat.scala 30:58] + node _T_1385 = cat(UInt<64>("h6b0000000e"), UInt<64>("h138000002a8")) @[Cat.scala 30:58] + node _T_1386 = cat(_T_1385, _T_1384) @[Cat.scala 30:58] + node _T_1387 = cat(UInt<64>("h1830000031d"), UInt<64>("h1120000006f")) @[Cat.scala 30:58] + node _T_1388 = cat(UInt<64>("h1e600000000"), UInt<64>("hf2000000b9")) @[Cat.scala 30:58] + node _T_1389 = cat(_T_1388, _T_1387) @[Cat.scala 30:58] + node _T_1390 = cat(_T_1389, _T_1386) @[Cat.scala 30:58] + node _T_1391 = cat(UInt<64>("h2ba00000060"), UInt<64>("h69000002ce")) @[Cat.scala 30:58] + node _T_1392 = cat(UInt<64>("h302000002e3"), UInt<64>("h383000002ed")) @[Cat.scala 30:58] + node _T_1393 = cat(_T_1392, _T_1391) @[Cat.scala 30:58] + node _T_1394 = cat(UInt<64>("h50000001b3"), UInt<64>("h2840000032e")) @[Cat.scala 30:58] + node _T_1395 = cat(UInt<64>("h19700000025"), UInt<64>("ha100000146")) @[Cat.scala 30:58] + node _T_1396 = cat(_T_1395, _T_1394) @[Cat.scala 30:58] + node _T_1397 = cat(_T_1396, _T_1393) @[Cat.scala 30:58] + node _T_1398 = cat(_T_1397, _T_1390) @[Cat.scala 30:58] + node _T_1399 = cat(_T_1398, _T_1383) @[Cat.scala 30:58] + node _T_1400 = cat(_T_1399, _T_1368) @[Cat.scala 30:58] + node _T_1401 = cat(_T_1400, _T_1337) @[Cat.scala 30:58] + node _T_1402 = cat(UInt<64>("h1e0000025d"), UInt<64>("h3b200000021")) @[Cat.scala 30:58] + node _T_1403 = cat(UInt<64>("h3660000001b"), UInt<64>("h300000003a7")) @[Cat.scala 30:58] + node _T_1404 = cat(_T_1403, _T_1402) @[Cat.scala 30:58] + node _T_1405 = cat(UInt<64>("h94000001b9"), UInt<64>("h7100000058")) @[Cat.scala 30:58] + node _T_1406 = cat(UInt<64>("h9300000158"), UInt<64>("h3e00000153")) @[Cat.scala 30:58] + node _T_1407 = cat(_T_1406, _T_1405) @[Cat.scala 30:58] + node _T_1408 = cat(_T_1407, _T_1404) @[Cat.scala 30:58] + node _T_1409 = cat(UInt<64>("h34d0000016d"), UInt<64>("h3460000022a")) @[Cat.scala 30:58] + node _T_1410 = cat(UInt<64>("h8d0000027f"), UInt<64>("h1b0000003ba")) @[Cat.scala 30:58] + node _T_1411 = cat(_T_1410, _T_1409) @[Cat.scala 30:58] + node _T_1412 = cat(UInt<64>("h331000003df"), UInt<64>("hd30000018c")) @[Cat.scala 30:58] + node _T_1413 = cat(UInt<64>("h23200000152"), UInt<64>("h335000000f9")) @[Cat.scala 30:58] + node _T_1414 = cat(_T_1413, _T_1412) @[Cat.scala 30:58] + node _T_1415 = cat(_T_1414, _T_1411) @[Cat.scala 30:58] + node _T_1416 = cat(_T_1415, _T_1408) @[Cat.scala 30:58] + node _T_1417 = cat(UInt<64>("h267000003ce"), UInt<64>("h16c00000340")) @[Cat.scala 30:58] + node _T_1418 = cat(UInt<64>("h32c0000010a"), UInt<64>("h1ef00000189")) @[Cat.scala 30:58] + node _T_1419 = cat(_T_1418, _T_1417) @[Cat.scala 30:58] + node _T_1420 = cat(UInt<64>("h9f0000015c"), UInt<64>("h394000001d6")) @[Cat.scala 30:58] + node _T_1421 = cat(UInt<64>("h323000001a3"), UInt<64>("h1ae00000150")) @[Cat.scala 30:58] + node _T_1422 = cat(_T_1421, _T_1420) @[Cat.scala 30:58] + node _T_1423 = cat(_T_1422, _T_1419) @[Cat.scala 30:58] + node _T_1424 = cat(UInt<64>("h220000000d7"), UInt<64>("hb4000000f9")) @[Cat.scala 30:58] + node _T_1425 = cat(UInt<64>("h1ca00000387"), UInt<64>("h3480000021e")) @[Cat.scala 30:58] + node _T_1426 = cat(_T_1425, _T_1424) @[Cat.scala 30:58] + node _T_1427 = cat(UInt<64>("h368000002d9"), UInt<64>("h3120000027c")) @[Cat.scala 30:58] + node _T_1428 = cat(UInt<64>("h32600000334"), UInt<64>("h31b00000245")) @[Cat.scala 30:58] + node _T_1429 = cat(_T_1428, _T_1427) @[Cat.scala 30:58] + node _T_1430 = cat(_T_1429, _T_1426) @[Cat.scala 30:58] + node _T_1431 = cat(_T_1430, _T_1423) @[Cat.scala 30:58] + node _T_1432 = cat(_T_1431, _T_1416) @[Cat.scala 30:58] + node _T_1433 = cat(UInt<64>("h68000003d3"), UInt<64>("h2f60000029f")) @[Cat.scala 30:58] + node _T_1434 = cat(UInt<64>("hfe0000029e"), UInt<64>("h191000001a2")) @[Cat.scala 30:58] + node _T_1435 = cat(_T_1434, _T_1433) @[Cat.scala 30:58] + node _T_1436 = cat(UInt<64>("h8800000238"), UInt<64>("h3d800000398")) @[Cat.scala 30:58] + node _T_1437 = cat(UInt<64>("h24800000296"), UInt<64>("h2d9000002e9")) @[Cat.scala 30:58] + node _T_1438 = cat(_T_1437, _T_1436) @[Cat.scala 30:58] + node _T_1439 = cat(_T_1438, _T_1435) @[Cat.scala 30:58] + node _T_1440 = cat(UInt<64>("h19e00000181"), UInt<64>("h31a0000008b")) @[Cat.scala 30:58] + node _T_1441 = cat(UInt<64>("h2c3000000ad"), UInt<64>("h2100000039f")) @[Cat.scala 30:58] + node _T_1442 = cat(_T_1441, _T_1440) @[Cat.scala 30:58] + node _T_1443 = cat(UInt<64>("h17a0000013c"), UInt<64>("h22a000001c9")) @[Cat.scala 30:58] + node _T_1444 = cat(UInt<64>("h3d1000001dd"), UInt<64>("h2fe000000b7")) @[Cat.scala 30:58] + node _T_1445 = cat(_T_1444, _T_1443) @[Cat.scala 30:58] + node _T_1446 = cat(_T_1445, _T_1442) @[Cat.scala 30:58] + node _T_1447 = cat(_T_1446, _T_1439) @[Cat.scala 30:58] + node _T_1448 = cat(UInt<64>("h3b30000018f"), UInt<64>("hec000000c4")) @[Cat.scala 30:58] + node _T_1449 = cat(UInt<64>("ha500000325"), UInt<64>("he5000001a0")) @[Cat.scala 30:58] + node _T_1450 = cat(_T_1449, _T_1448) @[Cat.scala 30:58] + node _T_1451 = cat(UInt<64>("h690000010e"), UInt<64>("h1f9000003e4")) @[Cat.scala 30:58] + node _T_1452 = cat(UInt<64>("h31c000002b8"), UInt<64>("h2c0000002df")) @[Cat.scala 30:58] + node _T_1453 = cat(_T_1452, _T_1451) @[Cat.scala 30:58] + node _T_1454 = cat(_T_1453, _T_1450) @[Cat.scala 30:58] + node _T_1455 = cat(UInt<64>("h12f00000210"), UInt<64>("h8c00000339")) @[Cat.scala 30:58] + node _T_1456 = cat(UInt<64>("h27b0000026f"), UInt<64>("h31b00000032")) @[Cat.scala 30:58] + node _T_1457 = cat(_T_1456, _T_1455) @[Cat.scala 30:58] + node _T_1458 = cat(UInt<64>("h7700000057"), UInt<64>("h23000000219")) @[Cat.scala 30:58] + node _T_1459 = cat(UInt<64>("h21400000363"), UInt<64>("h800000126")) @[Cat.scala 30:58] + node _T_1460 = cat(_T_1459, _T_1458) @[Cat.scala 30:58] + node _T_1461 = cat(_T_1460, _T_1457) @[Cat.scala 30:58] + node _T_1462 = cat(_T_1461, _T_1454) @[Cat.scala 30:58] + node _T_1463 = cat(_T_1462, _T_1447) @[Cat.scala 30:58] + node _T_1464 = cat(_T_1463, _T_1432) @[Cat.scala 30:58] + node _T_1465 = cat(UInt<64>("h250000018e"), UInt<64>("h32e0000006e")) @[Cat.scala 30:58] + node _T_1466 = cat(UInt<64>("h2e300000286"), UInt<64>("h2480000030d")) @[Cat.scala 30:58] + node _T_1467 = cat(_T_1466, _T_1465) @[Cat.scala 30:58] + node _T_1468 = cat(UInt<64>("h2ff000003af"), UInt<64>("h26b00000177")) @[Cat.scala 30:58] + node _T_1469 = cat(UInt<64>("h390000024d"), UInt<64>("h1de00000381")) @[Cat.scala 30:58] + node _T_1470 = cat(_T_1469, _T_1468) @[Cat.scala 30:58] + node _T_1471 = cat(_T_1470, _T_1467) @[Cat.scala 30:58] + node _T_1472 = cat(UInt<64>("h31000000120"), UInt<64>("h3be0000002c")) @[Cat.scala 30:58] + node _T_1473 = cat(UInt<64>("h345000002e6"), UInt<64>("h3d90000034d")) @[Cat.scala 30:58] + node _T_1474 = cat(_T_1473, _T_1472) @[Cat.scala 30:58] + node _T_1475 = cat(UInt<64>("h430000020a"), UInt<64>("h13300000063")) @[Cat.scala 30:58] + node _T_1476 = cat(UInt<64>("h3e4000001b0"), UInt<64>("h338000001bb")) @[Cat.scala 30:58] + node _T_1477 = cat(_T_1476, _T_1475) @[Cat.scala 30:58] + node _T_1478 = cat(_T_1477, _T_1474) @[Cat.scala 30:58] + node _T_1479 = cat(_T_1478, _T_1471) @[Cat.scala 30:58] + node _T_1480 = cat(UInt<64>("hab000003a2"), UInt<64>("h2ed000000a5")) @[Cat.scala 30:58] + node _T_1481 = cat(UInt<64>("h26d000001cd"), UInt<64>("h33a0000001c")) @[Cat.scala 30:58] + node _T_1482 = cat(_T_1481, _T_1480) @[Cat.scala 30:58] + node _T_1483 = cat(UInt<64>("h33a00000110"), UInt<64>("h9b00000143")) @[Cat.scala 30:58] + node _T_1484 = cat(UInt<64>("h2b600000154"), UInt<64>("h2b00000178")) @[Cat.scala 30:58] + node _T_1485 = cat(_T_1484, _T_1483) @[Cat.scala 30:58] + node _T_1486 = cat(_T_1485, _T_1482) @[Cat.scala 30:58] + node _T_1487 = cat(UInt<64>("hec0000009e"), UInt<64>("h5000000382")) @[Cat.scala 30:58] + node _T_1488 = cat(UInt<64>("h2e8000001bb"), UInt<64>("h2eb000000a8")) @[Cat.scala 30:58] + node _T_1489 = cat(_T_1488, _T_1487) @[Cat.scala 30:58] + node _T_1490 = cat(UInt<64>("h7c00000277"), UInt<64>("h109000000c1")) @[Cat.scala 30:58] + node _T_1491 = cat(UInt<64>("h3ad00000112"), UInt<64>("h2db000003a7")) @[Cat.scala 30:58] + node _T_1492 = cat(_T_1491, _T_1490) @[Cat.scala 30:58] + node _T_1493 = cat(_T_1492, _T_1489) @[Cat.scala 30:58] + node _T_1494 = cat(_T_1493, _T_1486) @[Cat.scala 30:58] + node _T_1495 = cat(_T_1494, _T_1479) @[Cat.scala 30:58] + node _T_1496 = cat(UInt<64>("h172000000b9"), UInt<64>("h1a90000030d")) @[Cat.scala 30:58] + node _T_1497 = cat(UInt<64>("h10d00000124"), UInt<64>("h1400000026b")) @[Cat.scala 30:58] + node _T_1498 = cat(_T_1497, _T_1496) @[Cat.scala 30:58] + node _T_1499 = cat(UInt<64>("h2fb0000009c"), UInt<64>("h21e000003a5")) @[Cat.scala 30:58] + node _T_1500 = cat(UInt<64>("h39300000058"), UInt<64>("h2f00000033b")) @[Cat.scala 30:58] + node _T_1501 = cat(_T_1500, _T_1499) @[Cat.scala 30:58] + node _T_1502 = cat(_T_1501, _T_1498) @[Cat.scala 30:58] + node _T_1503 = cat(UInt<64>("h100000275"), UInt<64>("he000003db")) @[Cat.scala 30:58] + node _T_1504 = cat(UInt<64>("h3e300000020"), UInt<64>("h38a00000289")) @[Cat.scala 30:58] + node _T_1505 = cat(_T_1504, _T_1503) @[Cat.scala 30:58] + node _T_1506 = cat(UInt<64>("h230000002e8"), UInt<64>("h32900000001")) @[Cat.scala 30:58] + node _T_1507 = cat(UInt<64>("h3cc00000393"), UInt<64>("h3690000018f")) @[Cat.scala 30:58] + node _T_1508 = cat(_T_1507, _T_1506) @[Cat.scala 30:58] + node _T_1509 = cat(_T_1508, _T_1505) @[Cat.scala 30:58] + node _T_1510 = cat(_T_1509, _T_1502) @[Cat.scala 30:58] + node _T_1511 = cat(UInt<64>("h1fd0000022a"), UInt<64>("h12100000317")) @[Cat.scala 30:58] + node _T_1512 = cat(UInt<64>("h3ca00000212"), UInt<64>("h22e000003d8")) @[Cat.scala 30:58] + node _T_1513 = cat(_T_1512, _T_1511) @[Cat.scala 30:58] + node _T_1514 = cat(UInt<64>("h24300000191"), UInt<64>("h19500000258")) @[Cat.scala 30:58] + node _T_1515 = cat(UInt<64>("hfb0000021c"), UInt<64>("h125000002ab")) @[Cat.scala 30:58] + node _T_1516 = cat(_T_1515, _T_1514) @[Cat.scala 30:58] + node _T_1517 = cat(_T_1516, _T_1513) @[Cat.scala 30:58] + node _T_1518 = cat(UInt<64>("h8100000078"), UInt<64>("h35100000387")) @[Cat.scala 30:58] + node _T_1519 = cat(UInt<64>("h2cc00000209"), UInt<64>("h1c4000003e3")) @[Cat.scala 30:58] + node _T_1520 = cat(_T_1519, _T_1518) @[Cat.scala 30:58] + node _T_1521 = cat(UInt<64>("h2a6000000e0"), UInt<64>("h560000026e")) @[Cat.scala 30:58] + node _T_1522 = cat(UInt<64>("hf000000212"), UInt<64>("hb50000037f")) @[Cat.scala 30:58] + node _T_1523 = cat(_T_1522, _T_1521) @[Cat.scala 30:58] + node _T_1524 = cat(_T_1523, _T_1520) @[Cat.scala 30:58] + node _T_1525 = cat(_T_1524, _T_1517) @[Cat.scala 30:58] + node _T_1526 = cat(_T_1525, _T_1510) @[Cat.scala 30:58] + node _T_1527 = cat(_T_1526, _T_1495) @[Cat.scala 30:58] + node _T_1528 = cat(_T_1527, _T_1464) @[Cat.scala 30:58] + node _T_1529 = cat(_T_1528, _T_1401) @[Cat.scala 30:58] + node _T_1530 = cat(UInt<64>("h3190000028b"), UInt<64>("h14f00000334")) @[Cat.scala 30:58] + node _T_1531 = cat(UInt<64>("h100000060"), UInt<64>("h281000000e2")) @[Cat.scala 30:58] + node _T_1532 = cat(_T_1531, _T_1530) @[Cat.scala 30:58] + node _T_1533 = cat(UInt<64>("h3db00000239"), UInt<64>("h14000000106")) @[Cat.scala 30:58] + node _T_1534 = cat(UInt<64>("h2f20000007e"), UInt<64>("h286000000ee")) @[Cat.scala 30:58] + node _T_1535 = cat(_T_1534, _T_1533) @[Cat.scala 30:58] + node _T_1536 = cat(_T_1535, _T_1532) @[Cat.scala 30:58] + node _T_1537 = cat(UInt<64>("hcb000000bf"), UInt<64>("h3be00000262")) @[Cat.scala 30:58] + node _T_1538 = cat(UInt<64>("hb40000031c"), UInt<64>("h8e000000ee")) @[Cat.scala 30:58] + node _T_1539 = cat(_T_1538, _T_1537) @[Cat.scala 30:58] + node _T_1540 = cat(UInt<64>("ha50000023d"), UInt<64>("h12b00000374")) @[Cat.scala 30:58] + node _T_1541 = cat(UInt<64>("h3ce0000008c"), UInt<64>("h2f90000006c")) @[Cat.scala 30:58] + node _T_1542 = cat(_T_1541, _T_1540) @[Cat.scala 30:58] + node _T_1543 = cat(_T_1542, _T_1539) @[Cat.scala 30:58] + node _T_1544 = cat(_T_1543, _T_1536) @[Cat.scala 30:58] + node _T_1545 = cat(UInt<64>("h22f00000354"), UInt<64>("h28600000315")) @[Cat.scala 30:58] + node _T_1546 = cat(UInt<64>("h1a6000002c0"), UInt<64>("h26b00000017")) @[Cat.scala 30:58] + node _T_1547 = cat(_T_1546, _T_1545) @[Cat.scala 30:58] + node _T_1548 = cat(UInt<64>("h235000001e0"), UInt<64>("h1040000037a")) @[Cat.scala 30:58] + node _T_1549 = cat(UInt<64>("h1ec00000174"), UInt<64>("h21e00000034")) @[Cat.scala 30:58] + node _T_1550 = cat(_T_1549, _T_1548) @[Cat.scala 30:58] + node _T_1551 = cat(_T_1550, _T_1547) @[Cat.scala 30:58] + node _T_1552 = cat(UInt<64>("h2e900000222"), UInt<64>("h3df000000c9")) @[Cat.scala 30:58] + node _T_1553 = cat(UInt<64>("h17400000077"), UInt<64>("hcf00000198")) @[Cat.scala 30:58] + node _T_1554 = cat(_T_1553, _T_1552) @[Cat.scala 30:58] + node _T_1555 = cat(UInt<64>("h298000001d0"), UInt<64>("h3a400000285")) @[Cat.scala 30:58] + node _T_1556 = cat(UInt<64>("h21500000125"), UInt<64>("h2200000051")) @[Cat.scala 30:58] + node _T_1557 = cat(_T_1556, _T_1555) @[Cat.scala 30:58] + node _T_1558 = cat(_T_1557, _T_1554) @[Cat.scala 30:58] + node _T_1559 = cat(_T_1558, _T_1551) @[Cat.scala 30:58] + node _T_1560 = cat(_T_1559, _T_1544) @[Cat.scala 30:58] + node _T_1561 = cat(UInt<64>("h38c00000370"), UInt<64>("h1de00000034")) @[Cat.scala 30:58] + node _T_1562 = cat(UInt<64>("h21000002e8"), UInt<64>("hcb000000e0")) @[Cat.scala 30:58] + node _T_1563 = cat(_T_1562, _T_1561) @[Cat.scala 30:58] + node _T_1564 = cat(UInt<64>("h16d00000376"), UInt<64>("hd6000002df")) @[Cat.scala 30:58] + node _T_1565 = cat(UInt<64>("h30d00000001"), UInt<64>("h37c000000a7")) @[Cat.scala 30:58] + node _T_1566 = cat(_T_1565, _T_1564) @[Cat.scala 30:58] + node _T_1567 = cat(_T_1566, _T_1563) @[Cat.scala 30:58] + node _T_1568 = cat(UInt<64>("h2c100000141"), UInt<64>("h2a800000214")) @[Cat.scala 30:58] + node _T_1569 = cat(UInt<64>("h3b3000001e5"), UInt<64>("h2b0000000a9")) @[Cat.scala 30:58] + node _T_1570 = cat(_T_1569, _T_1568) @[Cat.scala 30:58] + node _T_1571 = cat(UInt<64>("h32000000b1"), UInt<64>("h18200000065")) @[Cat.scala 30:58] + node _T_1572 = cat(UInt<64>("h1da000002c4"), UInt<64>("h650000002a")) @[Cat.scala 30:58] + node _T_1573 = cat(_T_1572, _T_1571) @[Cat.scala 30:58] + node _T_1574 = cat(_T_1573, _T_1570) @[Cat.scala 30:58] + node _T_1575 = cat(_T_1574, _T_1567) @[Cat.scala 30:58] + node _T_1576 = cat(UInt<64>("h2a700000393"), UInt<64>("h18f0000028e")) @[Cat.scala 30:58] + node _T_1577 = cat(UInt<64>("h3b8000000f2"), UInt<64>("h14a00000271")) @[Cat.scala 30:58] + node _T_1578 = cat(_T_1577, _T_1576) @[Cat.scala 30:58] + node _T_1579 = cat(UInt<64>("h1dd0000031b"), UInt<64>("h1d700000336")) @[Cat.scala 30:58] + node _T_1580 = cat(UInt<64>("h2c9000000fc"), UInt<64>("h2d500000281")) @[Cat.scala 30:58] + node _T_1581 = cat(_T_1580, _T_1579) @[Cat.scala 30:58] + node _T_1582 = cat(_T_1581, _T_1578) @[Cat.scala 30:58] + node _T_1583 = cat(UInt<64>("h21100000097"), UInt<64>("h3a9000000f5")) @[Cat.scala 30:58] + node _T_1584 = cat(UInt<64>("h4d0000014d"), UInt<64>("h3660000036c")) @[Cat.scala 30:58] + node _T_1585 = cat(_T_1584, _T_1583) @[Cat.scala 30:58] + node _T_1586 = cat(UInt<64>("h38b000003aa"), UInt<64>("h22100000259")) @[Cat.scala 30:58] + node _T_1587 = cat(UInt<64>("h8f0000018d"), UInt<64>("h35500000307")) @[Cat.scala 30:58] + node _T_1588 = cat(_T_1587, _T_1586) @[Cat.scala 30:58] + node _T_1589 = cat(_T_1588, _T_1585) @[Cat.scala 30:58] + node _T_1590 = cat(_T_1589, _T_1582) @[Cat.scala 30:58] + node _T_1591 = cat(_T_1590, _T_1575) @[Cat.scala 30:58] + node _T_1592 = cat(_T_1591, _T_1560) @[Cat.scala 30:58] + node _T_1593 = cat(UInt<64>("hef000002f3"), UInt<64>("h3d3000000e9")) @[Cat.scala 30:58] + node _T_1594 = cat(UInt<64>("h16d000001a8"), UInt<64>("h69000001c6")) @[Cat.scala 30:58] + node _T_1595 = cat(_T_1594, _T_1593) @[Cat.scala 30:58] + node _T_1596 = cat(UInt<64>("h36000003c2"), UInt<64>("h62000000d2")) @[Cat.scala 30:58] + node _T_1597 = cat(UInt<64>("h1b80000039b"), UInt<64>("h6200000384")) @[Cat.scala 30:58] + node _T_1598 = cat(_T_1597, _T_1596) @[Cat.scala 30:58] + node _T_1599 = cat(_T_1598, _T_1595) @[Cat.scala 30:58] + node _T_1600 = cat(UInt<64>("h13b00000211"), UInt<64>("h2fc0000028f")) @[Cat.scala 30:58] + node _T_1601 = cat(UInt<64>("h2b90000005a"), UInt<64>("h15000000253")) @[Cat.scala 30:58] + node _T_1602 = cat(_T_1601, _T_1600) @[Cat.scala 30:58] + node _T_1603 = cat(UInt<64>("h2d6000002ad"), UInt<64>("h306000001d0")) @[Cat.scala 30:58] + node _T_1604 = cat(UInt<64>("h11a000002f2"), UInt<64>("h14400000046")) @[Cat.scala 30:58] + node _T_1605 = cat(_T_1604, _T_1603) @[Cat.scala 30:58] + node _T_1606 = cat(_T_1605, _T_1602) @[Cat.scala 30:58] + node _T_1607 = cat(_T_1606, _T_1599) @[Cat.scala 30:58] + node _T_1608 = cat(UInt<64>("h26e000001ee"), UInt<64>("h21800000020")) @[Cat.scala 30:58] + node _T_1609 = cat(UInt<64>("h37a00000185"), UInt<64>("h25200000019")) @[Cat.scala 30:58] + node _T_1610 = cat(_T_1609, _T_1608) @[Cat.scala 30:58] + node _T_1611 = cat(UInt<64>("h12200000025"), UInt<64>("h4b000001e8")) @[Cat.scala 30:58] + node _T_1612 = cat(UInt<64>("h2d60000027f"), UInt<64>("h1f000000199")) @[Cat.scala 30:58] + node _T_1613 = cat(_T_1612, _T_1611) @[Cat.scala 30:58] + node _T_1614 = cat(_T_1613, _T_1610) @[Cat.scala 30:58] + node _T_1615 = cat(UInt<64>("h224000003b6"), UInt<64>("h1c10000001b")) @[Cat.scala 30:58] + node _T_1616 = cat(UInt<64>("h28400000050"), UInt<64>("h870000021b")) @[Cat.scala 30:58] + node _T_1617 = cat(_T_1616, _T_1615) @[Cat.scala 30:58] + node _T_1618 = cat(UInt<64>("h122000002d3"), UInt<64>("h3460000012f")) @[Cat.scala 30:58] + node _T_1619 = cat(UInt<64>("ha20000007d"), UInt<64>("h2ff000002de")) @[Cat.scala 30:58] + node _T_1620 = cat(_T_1619, _T_1618) @[Cat.scala 30:58] + node _T_1621 = cat(_T_1620, _T_1617) @[Cat.scala 30:58] + node _T_1622 = cat(_T_1621, _T_1614) @[Cat.scala 30:58] + node _T_1623 = cat(_T_1622, _T_1607) @[Cat.scala 30:58] + node _T_1624 = cat(UInt<64>("h1eb000000f8"), UInt<64>("h19f00000228")) @[Cat.scala 30:58] + node _T_1625 = cat(UInt<64>("h740000016a"), UInt<64>("h3d90000006b")) @[Cat.scala 30:58] + node _T_1626 = cat(_T_1625, _T_1624) @[Cat.scala 30:58] + node _T_1627 = cat(UInt<64>("h35b00000365"), UInt<64>("h26900000030")) @[Cat.scala 30:58] + node _T_1628 = cat(UInt<64>("h11a00000349"), UInt<64>("heb00000090")) @[Cat.scala 30:58] + node _T_1629 = cat(_T_1628, _T_1627) @[Cat.scala 30:58] + node _T_1630 = cat(_T_1629, _T_1626) @[Cat.scala 30:58] + node _T_1631 = cat(UInt<64>("h3910000014f"), UInt<64>("h23b000002d4")) @[Cat.scala 30:58] + node _T_1632 = cat(UInt<64>("hc200000107"), UInt<64>("h230000001d6")) @[Cat.scala 30:58] + node _T_1633 = cat(_T_1632, _T_1631) @[Cat.scala 30:58] + node _T_1634 = cat(UInt<64>("h30e00000329"), UInt<64>("hf200000157")) @[Cat.scala 30:58] + node _T_1635 = cat(UInt<64>("h2d800000153"), UInt<64>("h3d9000002a5")) @[Cat.scala 30:58] + node _T_1636 = cat(_T_1635, _T_1634) @[Cat.scala 30:58] + node _T_1637 = cat(_T_1636, _T_1633) @[Cat.scala 30:58] + node _T_1638 = cat(_T_1637, _T_1630) @[Cat.scala 30:58] + node _T_1639 = cat(UInt<64>("h1ae0000019a"), UInt<64>("h15800000150")) @[Cat.scala 30:58] + node _T_1640 = cat(UInt<64>("h2f700000038"), UInt<64>("h265000001d1")) @[Cat.scala 30:58] + node _T_1641 = cat(_T_1640, _T_1639) @[Cat.scala 30:58] + node _T_1642 = cat(UInt<64>("h135000001e5"), UInt<64>("hb00000024e")) @[Cat.scala 30:58] + node _T_1643 = cat(UInt<64>("h162000003e1"), UInt<64>("h14d00000196")) @[Cat.scala 30:58] + node _T_1644 = cat(_T_1643, _T_1642) @[Cat.scala 30:58] + node _T_1645 = cat(_T_1644, _T_1641) @[Cat.scala 30:58] + node _T_1646 = cat(UInt<64>("h2bb000000ee"), UInt<64>("h136000002ea")) @[Cat.scala 30:58] + node _T_1647 = cat(UInt<64>("h1e700000150"), UInt<64>("h2e0000020d")) @[Cat.scala 30:58] + node _T_1648 = cat(_T_1647, _T_1646) @[Cat.scala 30:58] + node _T_1649 = cat(UInt<64>("h6400000086"), UInt<64>("h1f700000100")) @[Cat.scala 30:58] + node _T_1650 = cat(UInt<64>("h10c000002d2"), UInt<64>("h18900000222")) @[Cat.scala 30:58] + node _T_1651 = cat(_T_1650, _T_1649) @[Cat.scala 30:58] + node _T_1652 = cat(_T_1651, _T_1648) @[Cat.scala 30:58] + node _T_1653 = cat(_T_1652, _T_1645) @[Cat.scala 30:58] + node _T_1654 = cat(_T_1653, _T_1638) @[Cat.scala 30:58] + node _T_1655 = cat(_T_1654, _T_1623) @[Cat.scala 30:58] + node _T_1656 = cat(_T_1655, _T_1592) @[Cat.scala 30:58] + node _T_1657 = cat(UInt<64>("h4b000003af"), UInt<64>("h13a0000016f")) @[Cat.scala 30:58] + node _T_1658 = cat(UInt<64>("h3db00000275"), UInt<64>("h1590000006a")) @[Cat.scala 30:58] + node _T_1659 = cat(_T_1658, _T_1657) @[Cat.scala 30:58] + node _T_1660 = cat(UInt<64>("h38c000000d0"), UInt<64>("h2580000018c")) @[Cat.scala 30:58] + node _T_1661 = cat(UInt<64>("h5c0000020b"), UInt<64>("h180000001ad")) @[Cat.scala 30:58] + node _T_1662 = cat(_T_1661, _T_1660) @[Cat.scala 30:58] + node _T_1663 = cat(_T_1662, _T_1659) @[Cat.scala 30:58] + node _T_1664 = cat(UInt<64>("h11500000163"), UInt<64>("h22100000082")) @[Cat.scala 30:58] + node _T_1665 = cat(UInt<64>("h15f000002a1"), UInt<64>("h29c000003de")) @[Cat.scala 30:58] + node _T_1666 = cat(_T_1665, _T_1664) @[Cat.scala 30:58] + node _T_1667 = cat(UInt<64>("h35f000002cf"), UInt<64>("h355000003df")) @[Cat.scala 30:58] + node _T_1668 = cat(UInt<64>("h6400000054"), UInt<64>("h138000001c1")) @[Cat.scala 30:58] + node _T_1669 = cat(_T_1668, _T_1667) @[Cat.scala 30:58] + node _T_1670 = cat(_T_1669, _T_1666) @[Cat.scala 30:58] + node _T_1671 = cat(_T_1670, _T_1663) @[Cat.scala 30:58] + node _T_1672 = cat(UInt<64>("h237000000d3"), UInt<64>("h21400000268")) @[Cat.scala 30:58] + node _T_1673 = cat(UInt<64>("h172000002e1"), UInt<64>("h344000002c3")) @[Cat.scala 30:58] + node _T_1674 = cat(_T_1673, _T_1672) @[Cat.scala 30:58] + node _T_1675 = cat(UInt<64>("h1cd000001c4"), UInt<64>("h3dd0000034f")) @[Cat.scala 30:58] + node _T_1676 = cat(UInt<64>("hb6000003ce"), UInt<64>("h3900000013c")) @[Cat.scala 30:58] + node _T_1677 = cat(_T_1676, _T_1675) @[Cat.scala 30:58] + node _T_1678 = cat(_T_1677, _T_1674) @[Cat.scala 30:58] + node _T_1679 = cat(UInt<64>("ha00000031c"), UInt<64>("h10c000002ea")) @[Cat.scala 30:58] + node _T_1680 = cat(UInt<64>("h160000026a"), UInt<64>("h3030000020a")) @[Cat.scala 30:58] + node _T_1681 = cat(_T_1680, _T_1679) @[Cat.scala 30:58] + node _T_1682 = cat(UInt<64>("h284000002d7"), UInt<64>("h35600000073")) @[Cat.scala 30:58] + node _T_1683 = cat(UInt<64>("h30b000000a5"), UInt<64>("h11000000e2")) @[Cat.scala 30:58] + node _T_1684 = cat(_T_1683, _T_1682) @[Cat.scala 30:58] + node _T_1685 = cat(_T_1684, _T_1681) @[Cat.scala 30:58] + node _T_1686 = cat(_T_1685, _T_1678) @[Cat.scala 30:58] + node _T_1687 = cat(_T_1686, _T_1671) @[Cat.scala 30:58] + node _T_1688 = cat(UInt<64>("h3570000033e"), UInt<64>("h38f000000c8")) @[Cat.scala 30:58] + node _T_1689 = cat(UInt<64>("h3d7000000bb"), UInt<64>("h89000002e6")) @[Cat.scala 30:58] + node _T_1690 = cat(_T_1689, _T_1688) @[Cat.scala 30:58] + node _T_1691 = cat(UInt<64>("h2350000029f"), UInt<64>("h2cd000002c1")) @[Cat.scala 30:58] + node _T_1692 = cat(UInt<64>("hfd00000376"), UInt<64>("h2cf00000311")) @[Cat.scala 30:58] + node _T_1693 = cat(_T_1692, _T_1691) @[Cat.scala 30:58] + node _T_1694 = cat(_T_1693, _T_1690) @[Cat.scala 30:58] + node _T_1695 = cat(UInt<64>("h9a00000291"), UInt<64>("h311000003c2")) @[Cat.scala 30:58] + node _T_1696 = cat(UInt<64>("hfd0000026c"), UInt<64>("hc400000125")) @[Cat.scala 30:58] + node _T_1697 = cat(_T_1696, _T_1695) @[Cat.scala 30:58] + node _T_1698 = cat(UInt<64>("h383000000ad"), UInt<64>("h1bf00000090")) @[Cat.scala 30:58] + node _T_1699 = cat(UInt<64>("h14500000048"), UInt<64>("h50000031c")) @[Cat.scala 30:58] + node _T_1700 = cat(_T_1699, _T_1698) @[Cat.scala 30:58] + node _T_1701 = cat(_T_1700, _T_1697) @[Cat.scala 30:58] + node _T_1702 = cat(_T_1701, _T_1694) @[Cat.scala 30:58] + node _T_1703 = cat(UInt<64>("h13500000050"), UInt<64>("h268000002a6")) @[Cat.scala 30:58] + node _T_1704 = cat(UInt<64>("h9f000002ad"), UInt<64>("haf00000319")) @[Cat.scala 30:58] + node _T_1705 = cat(_T_1704, _T_1703) @[Cat.scala 30:58] + node _T_1706 = cat(UInt<64>("h346000003c7"), UInt<64>("h7b0000027d")) @[Cat.scala 30:58] + node _T_1707 = cat(UInt<64>("h22600000382"), UInt<64>("h2cb000000f1")) @[Cat.scala 30:58] + node _T_1708 = cat(_T_1707, _T_1706) @[Cat.scala 30:58] + node _T_1709 = cat(_T_1708, _T_1705) @[Cat.scala 30:58] + node _T_1710 = cat(UInt<64>("h5200000174"), UInt<64>("he6000002b5")) @[Cat.scala 30:58] + node _T_1711 = cat(UInt<64>("h144000002d1"), UInt<64>("h27300000259")) @[Cat.scala 30:58] + node _T_1712 = cat(_T_1711, _T_1710) @[Cat.scala 30:58] + node _T_1713 = cat(UInt<64>("h6700000229"), UInt<64>("h39f0000018e")) @[Cat.scala 30:58] + node _T_1714 = cat(UInt<64>("h3c6000000ae"), UInt<64>("h1100000048")) @[Cat.scala 30:58] + node _T_1715 = cat(_T_1714, _T_1713) @[Cat.scala 30:58] + node _T_1716 = cat(_T_1715, _T_1712) @[Cat.scala 30:58] + node _T_1717 = cat(_T_1716, _T_1709) @[Cat.scala 30:58] + node _T_1718 = cat(_T_1717, _T_1702) @[Cat.scala 30:58] + node _T_1719 = cat(_T_1718, _T_1687) @[Cat.scala 30:58] + node _T_1720 = cat(UInt<64>("hb100000145"), UInt<64>("h9f000003d2")) @[Cat.scala 30:58] + node _T_1721 = cat(UInt<64>("h174000000b9"), UInt<64>("h2510000022e")) @[Cat.scala 30:58] + node _T_1722 = cat(_T_1721, _T_1720) @[Cat.scala 30:58] + node _T_1723 = cat(UInt<64>("h2570000035b"), UInt<64>("h189000001f9")) @[Cat.scala 30:58] + node _T_1724 = cat(UInt<64>("h1790000023d"), UInt<64>("h2e90000028b")) @[Cat.scala 30:58] + node _T_1725 = cat(_T_1724, _T_1723) @[Cat.scala 30:58] + node _T_1726 = cat(_T_1725, _T_1722) @[Cat.scala 30:58] + node _T_1727 = cat(UInt<64>("h24f0000015d"), UInt<64>("h36100000141")) @[Cat.scala 30:58] + node _T_1728 = cat(UInt<64>("h1b80000037a"), UInt<64>("h22900000190")) @[Cat.scala 30:58] + node _T_1729 = cat(_T_1728, _T_1727) @[Cat.scala 30:58] + node _T_1730 = cat(UInt<64>("h25100000375"), UInt<64>("h1590000034c")) @[Cat.scala 30:58] + node _T_1731 = cat(UInt<64>("h38c000003d4"), UInt<64>("h122000003a5")) @[Cat.scala 30:58] + node _T_1732 = cat(_T_1731, _T_1730) @[Cat.scala 30:58] + node _T_1733 = cat(_T_1732, _T_1729) @[Cat.scala 30:58] + node _T_1734 = cat(_T_1733, _T_1726) @[Cat.scala 30:58] + node _T_1735 = cat(UInt<64>("h179000003dd"), UInt<64>("h220000001c0")) @[Cat.scala 30:58] + node _T_1736 = cat(UInt<64>("h30d0000014c"), UInt<64>("h1c800000032")) @[Cat.scala 30:58] + node _T_1737 = cat(_T_1736, _T_1735) @[Cat.scala 30:58] + node _T_1738 = cat(UInt<64>("h1ef000002cc"), UInt<64>("h6e00000384")) @[Cat.scala 30:58] + node _T_1739 = cat(UInt<64>("h326000001bc"), UInt<64>("h380000002eb")) @[Cat.scala 30:58] + node _T_1740 = cat(_T_1739, _T_1738) @[Cat.scala 30:58] + node _T_1741 = cat(_T_1740, _T_1737) @[Cat.scala 30:58] + node _T_1742 = cat(UInt<64>("h2240000018a"), UInt<64>("h2bc00000006")) @[Cat.scala 30:58] + node _T_1743 = cat(UInt<64>("h1d000002bf"), UInt<64>("h1540000011d")) @[Cat.scala 30:58] + node _T_1744 = cat(_T_1743, _T_1742) @[Cat.scala 30:58] + node _T_1745 = cat(UInt<64>("h2760000028c"), UInt<64>("h33d000001c2")) @[Cat.scala 30:58] + node _T_1746 = cat(UInt<64>("h265000001e5"), UInt<64>("h22200000303")) @[Cat.scala 30:58] + node _T_1747 = cat(_T_1746, _T_1745) @[Cat.scala 30:58] + node _T_1748 = cat(_T_1747, _T_1744) @[Cat.scala 30:58] + node _T_1749 = cat(_T_1748, _T_1741) @[Cat.scala 30:58] + node _T_1750 = cat(_T_1749, _T_1734) @[Cat.scala 30:58] + node _T_1751 = cat(UInt<64>("h740000022f"), UInt<64>("h3cc00000216")) @[Cat.scala 30:58] + node _T_1752 = cat(UInt<64>("h388000001fb"), UInt<64>("h139000001e1")) @[Cat.scala 30:58] + node _T_1753 = cat(_T_1752, _T_1751) @[Cat.scala 30:58] + node _T_1754 = cat(UInt<64>("h25f00000157"), UInt<64>("h3cb000001b2")) @[Cat.scala 30:58] + node _T_1755 = cat(UInt<64>("ha900000310"), UInt<64>("h31a0000002a")) @[Cat.scala 30:58] + node _T_1756 = cat(_T_1755, _T_1754) @[Cat.scala 30:58] + node _T_1757 = cat(_T_1756, _T_1753) @[Cat.scala 30:58] + node _T_1758 = cat(UInt<64>("h1fb000001a5"), UInt<64>("h38000000361")) @[Cat.scala 30:58] + node _T_1759 = cat(UInt<64>("h1af00000367"), UInt<64>("h3940000019f")) @[Cat.scala 30:58] + node _T_1760 = cat(_T_1759, _T_1758) @[Cat.scala 30:58] + node _T_1761 = cat(UInt<64>("h93000000a2"), UInt<64>("h1530000021b")) @[Cat.scala 30:58] + node _T_1762 = cat(UInt<64>("h70000001e1"), UInt<64>("he000000069")) @[Cat.scala 30:58] + node _T_1763 = cat(_T_1762, _T_1761) @[Cat.scala 30:58] + node _T_1764 = cat(_T_1763, _T_1760) @[Cat.scala 30:58] + node _T_1765 = cat(_T_1764, _T_1757) @[Cat.scala 30:58] + node _T_1766 = cat(UInt<64>("h34200000073"), UInt<64>("h24400000253")) @[Cat.scala 30:58] + node _T_1767 = cat(UInt<64>("h3b4000003c4"), UInt<64>("h860000015e")) @[Cat.scala 30:58] + node _T_1768 = cat(_T_1767, _T_1766) @[Cat.scala 30:58] + node _T_1769 = cat(UInt<64>("h1e8000000e8"), UInt<64>("hc90000011f")) @[Cat.scala 30:58] + node _T_1770 = cat(UInt<64>("h31d0000025a"), UInt<64>("h18c0000009a")) @[Cat.scala 30:58] + node _T_1771 = cat(_T_1770, _T_1769) @[Cat.scala 30:58] + node _T_1772 = cat(_T_1771, _T_1768) @[Cat.scala 30:58] + node _T_1773 = cat(UInt<64>("h301000003af"), UInt<64>("h1de0000021b")) @[Cat.scala 30:58] + node _T_1774 = cat(UInt<64>("h1e500000079"), UInt<64>("h23e00000368")) @[Cat.scala 30:58] + node _T_1775 = cat(_T_1774, _T_1773) @[Cat.scala 30:58] + node _T_1776 = cat(UInt<64>("h2d10000032b"), UInt<64>("h1530000028c")) @[Cat.scala 30:58] + node _T_1777 = cat(UInt<64>("h3350000016a"), UInt<64>("h1c3000002eb")) @[Cat.scala 30:58] + node _T_1778 = cat(_T_1777, _T_1776) @[Cat.scala 30:58] + node _T_1779 = cat(_T_1778, _T_1775) @[Cat.scala 30:58] + node _T_1780 = cat(_T_1779, _T_1772) @[Cat.scala 30:58] + node _T_1781 = cat(_T_1780, _T_1765) @[Cat.scala 30:58] + node _T_1782 = cat(_T_1781, _T_1750) @[Cat.scala 30:58] + node _T_1783 = cat(_T_1782, _T_1719) @[Cat.scala 30:58] + node _T_1784 = cat(_T_1783, _T_1656) @[Cat.scala 30:58] + node _T_1785 = cat(UInt<64>("h38e"), UInt<64>("h2e800000154")) @[Cat.scala 30:58] + node _T_1786 = cat(UInt<64>("h1150000023c"), UInt<64>("h252000000ce")) @[Cat.scala 30:58] + node _T_1787 = cat(_T_1786, _T_1785) @[Cat.scala 30:58] + node _T_1788 = cat(UInt<64>("h2a8000003cd"), UInt<64>("h78000001f9")) @[Cat.scala 30:58] + node _T_1789 = cat(UInt<64>("h22b00000162"), UInt<64>("h2f5000003c1")) @[Cat.scala 30:58] + node _T_1790 = cat(_T_1789, _T_1788) @[Cat.scala 30:58] + node _T_1791 = cat(_T_1790, _T_1787) @[Cat.scala 30:58] + node _T_1792 = cat(UInt<64>("h20500000351"), UInt<64>("h34f00000273")) @[Cat.scala 30:58] + node _T_1793 = cat(UInt<64>("h1f90000038e"), UInt<64>("h17b000003cb")) @[Cat.scala 30:58] + node _T_1794 = cat(_T_1793, _T_1792) @[Cat.scala 30:58] + node _T_1795 = cat(UInt<64>("hf600000302"), UInt<64>("h3880000019a")) @[Cat.scala 30:58] + node _T_1796 = cat(UInt<64>("h18a0000036a"), UInt<64>("hf30000003f")) @[Cat.scala 30:58] + node _T_1797 = cat(_T_1796, _T_1795) @[Cat.scala 30:58] + node _T_1798 = cat(_T_1797, _T_1794) @[Cat.scala 30:58] + node _T_1799 = cat(_T_1798, _T_1791) @[Cat.scala 30:58] + node _T_1800 = cat(UInt<64>("hd6000001e2"), UInt<64>("h1ae0000018c")) @[Cat.scala 30:58] + node _T_1801 = cat(UInt<64>("h20c00000286"), UInt<64>("hf40000026b")) @[Cat.scala 30:58] + node _T_1802 = cat(_T_1801, _T_1800) @[Cat.scala 30:58] + node _T_1803 = cat(UInt<64>("hac00000148"), UInt<64>("h18f0000022d")) @[Cat.scala 30:58] + node _T_1804 = cat(UInt<64>("h26c00000374"), UInt<64>("h13000000043")) @[Cat.scala 30:58] + node _T_1805 = cat(_T_1804, _T_1803) @[Cat.scala 30:58] + node _T_1806 = cat(_T_1805, _T_1802) @[Cat.scala 30:58] + node _T_1807 = cat(UInt<64>("h217000003cc"), UInt<64>("h25200000200")) @[Cat.scala 30:58] + node _T_1808 = cat(UInt<64>("h9f00000201"), UInt<64>("h2ba00000006")) @[Cat.scala 30:58] + node _T_1809 = cat(_T_1808, _T_1807) @[Cat.scala 30:58] + node _T_1810 = cat(UInt<64>("h32900000232"), UInt<64>("h2ee00000372")) @[Cat.scala 30:58] + node _T_1811 = cat(UInt<64>("h4b0000016e"), UInt<64>("h1c6000002fc")) @[Cat.scala 30:58] + node _T_1812 = cat(_T_1811, _T_1810) @[Cat.scala 30:58] + node _T_1813 = cat(_T_1812, _T_1809) @[Cat.scala 30:58] + node _T_1814 = cat(_T_1813, _T_1806) @[Cat.scala 30:58] + node _T_1815 = cat(_T_1814, _T_1799) @[Cat.scala 30:58] + node _T_1816 = cat(UInt<64>("ha700000312"), UInt<64>("h5d000001fa")) @[Cat.scala 30:58] + node _T_1817 = cat(UInt<64>("h3550000017e"), UInt<64>("h100000033f")) @[Cat.scala 30:58] + node _T_1818 = cat(_T_1817, _T_1816) @[Cat.scala 30:58] + node _T_1819 = cat(UInt<64>("h144000001c4"), UInt<64>("h1ee0000027e")) @[Cat.scala 30:58] + node _T_1820 = cat(UInt<64>("h3400000053"), UInt<64>("h4e00000048")) @[Cat.scala 30:58] + node _T_1821 = cat(_T_1820, _T_1819) @[Cat.scala 30:58] + node _T_1822 = cat(_T_1821, _T_1818) @[Cat.scala 30:58] + node _T_1823 = cat(UInt<64>("ha000003a4"), UInt<64>("h700000003b")) @[Cat.scala 30:58] + node _T_1824 = cat(UInt<64>("h2da0000039c"), UInt<64>("h156000003a1")) @[Cat.scala 30:58] + node _T_1825 = cat(_T_1824, _T_1823) @[Cat.scala 30:58] + node _T_1826 = cat(UInt<64>("h11f00000045"), UInt<64>("h2a8000003c1")) @[Cat.scala 30:58] + node _T_1827 = cat(UInt<64>("h5c000003d9"), UInt<64>("h3c10000031d")) @[Cat.scala 30:58] + node _T_1828 = cat(_T_1827, _T_1826) @[Cat.scala 30:58] + node _T_1829 = cat(_T_1828, _T_1825) @[Cat.scala 30:58] + node _T_1830 = cat(_T_1829, _T_1822) @[Cat.scala 30:58] + node _T_1831 = cat(UInt<64>("h39000000375"), UInt<64>("h27200000356")) @[Cat.scala 30:58] + node _T_1832 = cat(UInt<64>("h35c00000185"), UInt<64>("h26800000258")) @[Cat.scala 30:58] + node _T_1833 = cat(_T_1832, _T_1831) @[Cat.scala 30:58] + node _T_1834 = cat(UInt<64>("h2e800000319"), UInt<64>("h2e8000000e8")) @[Cat.scala 30:58] + node _T_1835 = cat(UInt<64>("h26700000305"), UInt<64>("h1de000000b3")) @[Cat.scala 30:58] + node _T_1836 = cat(_T_1835, _T_1834) @[Cat.scala 30:58] + node _T_1837 = cat(_T_1836, _T_1833) @[Cat.scala 30:58] + node _T_1838 = cat(UInt<64>("h39200000307"), UInt<64>("h1fc000002b1")) @[Cat.scala 30:58] + node _T_1839 = cat(UInt<64>("h1200000008b"), UInt<64>("h32a000001ee")) @[Cat.scala 30:58] + node _T_1840 = cat(_T_1839, _T_1838) @[Cat.scala 30:58] + node _T_1841 = cat(UInt<64>("h81000001af"), UInt<64>("h3ce000000ea")) @[Cat.scala 30:58] + node _T_1842 = cat(UInt<64>("h22400000173"), UInt<64>("h2450000030c")) @[Cat.scala 30:58] + node _T_1843 = cat(_T_1842, _T_1841) @[Cat.scala 30:58] + node _T_1844 = cat(_T_1843, _T_1840) @[Cat.scala 30:58] + node _T_1845 = cat(_T_1844, _T_1837) @[Cat.scala 30:58] + node _T_1846 = cat(_T_1845, _T_1830) @[Cat.scala 30:58] + node _T_1847 = cat(_T_1846, _T_1815) @[Cat.scala 30:58] + node _T_1848 = cat(UInt<64>("h3d50000028d"), UInt<64>("h36400000016")) @[Cat.scala 30:58] + node _T_1849 = cat(UInt<64>("h26f0000032f"), UInt<64>("h10e000002e5")) @[Cat.scala 30:58] + node _T_1850 = cat(_T_1849, _T_1848) @[Cat.scala 30:58] + node _T_1851 = cat(UInt<64>("h2720000008b"), UInt<64>("h28d000001ac")) @[Cat.scala 30:58] + node _T_1852 = cat(UInt<64>("h1820000013b"), UInt<64>("h3de0000025b")) @[Cat.scala 30:58] + node _T_1853 = cat(_T_1852, _T_1851) @[Cat.scala 30:58] + node _T_1854 = cat(_T_1853, _T_1850) @[Cat.scala 30:58] + node _T_1855 = cat(UInt<64>("h1d800000379"), UInt<64>("h14300000158")) @[Cat.scala 30:58] + node _T_1856 = cat(UInt<64>("hef00000104"), UInt<64>("ha40000013d")) @[Cat.scala 30:58] + node _T_1857 = cat(_T_1856, _T_1855) @[Cat.scala 30:58] + node _T_1858 = cat(UInt<64>("h36100000179"), UInt<64>("hbd0000035d")) @[Cat.scala 30:58] + node _T_1859 = cat(UInt<64>("h16400000130"), UInt<64>("he7000001ff")) @[Cat.scala 30:58] + node _T_1860 = cat(_T_1859, _T_1858) @[Cat.scala 30:58] + node _T_1861 = cat(_T_1860, _T_1857) @[Cat.scala 30:58] + node _T_1862 = cat(_T_1861, _T_1854) @[Cat.scala 30:58] + node _T_1863 = cat(UInt<64>("h33900000023"), UInt<64>("h9800000046")) @[Cat.scala 30:58] + node _T_1864 = cat(UInt<64>("h18600000240"), UInt<64>("h14800000356")) @[Cat.scala 30:58] + node _T_1865 = cat(_T_1864, _T_1863) @[Cat.scala 30:58] + node _T_1866 = cat(UInt<64>("h2600000146"), UInt<64>("h350000001ea")) @[Cat.scala 30:58] + node _T_1867 = cat(UInt<64>("h268000001af"), UInt<64>("h1920000012f")) @[Cat.scala 30:58] + node _T_1868 = cat(_T_1867, _T_1866) @[Cat.scala 30:58] + node _T_1869 = cat(_T_1868, _T_1865) @[Cat.scala 30:58] + node _T_1870 = cat(UInt<64>("hce000002c4"), UInt<64>("h2220000032d")) @[Cat.scala 30:58] + node _T_1871 = cat(UInt<64>("h30f000003c2"), UInt<64>("h200000184")) @[Cat.scala 30:58] + node _T_1872 = cat(_T_1871, _T_1870) @[Cat.scala 30:58] + node _T_1873 = cat(UInt<64>("h32f000001ba"), UInt<64>("h37a000003c7")) @[Cat.scala 30:58] + node _T_1874 = cat(UInt<64>("h2990000033f"), UInt<64>("h33f00000031")) @[Cat.scala 30:58] + node _T_1875 = cat(_T_1874, _T_1873) @[Cat.scala 30:58] + node _T_1876 = cat(_T_1875, _T_1872) @[Cat.scala 30:58] + node _T_1877 = cat(_T_1876, _T_1869) @[Cat.scala 30:58] + node _T_1878 = cat(_T_1877, _T_1862) @[Cat.scala 30:58] + node _T_1879 = cat(UInt<64>("h5e00000141"), UInt<64>("h19a000000fb")) @[Cat.scala 30:58] + node _T_1880 = cat(UInt<64>("h1a6000000b3"), UInt<64>("hf6000002e5")) @[Cat.scala 30:58] + node _T_1881 = cat(_T_1880, _T_1879) @[Cat.scala 30:58] + node _T_1882 = cat(UInt<64>("h2a300000075"), UInt<64>("hd3000000b0")) @[Cat.scala 30:58] + node _T_1883 = cat(UInt<64>("h176000002fc"), UInt<64>("h90000020b")) @[Cat.scala 30:58] + node _T_1884 = cat(_T_1883, _T_1882) @[Cat.scala 30:58] + node _T_1885 = cat(_T_1884, _T_1881) @[Cat.scala 30:58] + node _T_1886 = cat(UInt<64>("h40000002c0"), UInt<64>("h1aa000003b8")) @[Cat.scala 30:58] + node _T_1887 = cat(UInt<64>("h2f600000324"), UInt<64>("h3500000213")) @[Cat.scala 30:58] + node _T_1888 = cat(_T_1887, _T_1886) @[Cat.scala 30:58] + node _T_1889 = cat(UInt<64>("h1f400000263"), UInt<64>("h32b00000017")) @[Cat.scala 30:58] + node _T_1890 = cat(UInt<64>("h14f00000177"), UInt<64>("h1b50000034e")) @[Cat.scala 30:58] + node _T_1891 = cat(_T_1890, _T_1889) @[Cat.scala 30:58] + node _T_1892 = cat(_T_1891, _T_1888) @[Cat.scala 30:58] + node _T_1893 = cat(_T_1892, _T_1885) @[Cat.scala 30:58] + node _T_1894 = cat(UInt<64>("hed000003cb"), UInt<64>("h14800000356")) @[Cat.scala 30:58] + node _T_1895 = cat(UInt<64>("h1d40000027f"), UInt<64>("h19f00000018")) @[Cat.scala 30:58] + node _T_1896 = cat(_T_1895, _T_1894) @[Cat.scala 30:58] + node _T_1897 = cat(UInt<64>("h235000002d3"), UInt<64>("h2ac0000013e")) @[Cat.scala 30:58] + node _T_1898 = cat(UInt<64>("h1c100000287"), UInt<64>("h13100000296")) @[Cat.scala 30:58] + node _T_1899 = cat(_T_1898, _T_1897) @[Cat.scala 30:58] + node _T_1900 = cat(_T_1899, _T_1896) @[Cat.scala 30:58] + node _T_1901 = cat(UInt<64>("h880000009e"), UInt<64>("h25500000119")) @[Cat.scala 30:58] + node _T_1902 = cat(UInt<64>("h17f00000375"), UInt<64>("h37200000126")) @[Cat.scala 30:58] + node _T_1903 = cat(_T_1902, _T_1901) @[Cat.scala 30:58] + node _T_1904 = cat(UInt<64>("h10c00000362"), UInt<64>("h3aa000002de")) @[Cat.scala 30:58] + node _T_1905 = cat(UInt<64>("h38c00000128"), UInt<64>("h73000001d7")) @[Cat.scala 30:58] + node _T_1906 = cat(_T_1905, _T_1904) @[Cat.scala 30:58] + node _T_1907 = cat(_T_1906, _T_1903) @[Cat.scala 30:58] + node _T_1908 = cat(_T_1907, _T_1900) @[Cat.scala 30:58] + node _T_1909 = cat(_T_1908, _T_1893) @[Cat.scala 30:58] + node _T_1910 = cat(_T_1909, _T_1878) @[Cat.scala 30:58] + node _T_1911 = cat(_T_1910, _T_1847) @[Cat.scala 30:58] + node _T_1912 = cat(UInt<64>("h3b8000001d8"), UInt<64>("h32000002a1")) @[Cat.scala 30:58] + node _T_1913 = cat(UInt<64>("h18d00000005"), UInt<64>("h16e000001b7")) @[Cat.scala 30:58] + node _T_1914 = cat(_T_1913, _T_1912) @[Cat.scala 30:58] + node _T_1915 = cat(UInt<64>("he7000001fa"), UInt<64>("h1010000009b")) @[Cat.scala 30:58] + node _T_1916 = cat(UInt<64>("h2300000258"), UInt<64>("h29b000003b4")) @[Cat.scala 30:58] + node _T_1917 = cat(_T_1916, _T_1915) @[Cat.scala 30:58] + node _T_1918 = cat(_T_1917, _T_1914) @[Cat.scala 30:58] + node _T_1919 = cat(UInt<64>("h1bb000000de"), UInt<64>("h3de000001bd")) @[Cat.scala 30:58] + node _T_1920 = cat(UInt<64>("h1850000015d"), UInt<64>("hd500000310")) @[Cat.scala 30:58] + node _T_1921 = cat(_T_1920, _T_1919) @[Cat.scala 30:58] + node _T_1922 = cat(UInt<64>("h26d00000096"), UInt<64>("hd000003af")) @[Cat.scala 30:58] + node _T_1923 = cat(UInt<64>("h264000001bc"), UInt<64>("h340000016e")) @[Cat.scala 30:58] + node _T_1924 = cat(_T_1923, _T_1922) @[Cat.scala 30:58] + node _T_1925 = cat(_T_1924, _T_1921) @[Cat.scala 30:58] + node _T_1926 = cat(_T_1925, _T_1918) @[Cat.scala 30:58] + node _T_1927 = cat(UInt<64>("h3b9000002d0"), UInt<64>("h3a60000025c")) @[Cat.scala 30:58] + node _T_1928 = cat(UInt<64>("h1ce000003cc"), UInt<64>("h33c00000154")) @[Cat.scala 30:58] + node _T_1929 = cat(_T_1928, _T_1927) @[Cat.scala 30:58] + node _T_1930 = cat(UInt<64>("h32c00000141"), UInt<64>("h26d0000038f")) @[Cat.scala 30:58] + node _T_1931 = cat(UInt<64>("h2a000000032"), UInt<64>("h20a000001b3")) @[Cat.scala 30:58] + node _T_1932 = cat(_T_1931, _T_1930) @[Cat.scala 30:58] + node _T_1933 = cat(_T_1932, _T_1929) @[Cat.scala 30:58] + node _T_1934 = cat(UInt<64>("h139000002f9"), UInt<64>("h390000004e")) @[Cat.scala 30:58] + node _T_1935 = cat(UInt<64>("h37000000ee"), UInt<64>("h160000003b6")) @[Cat.scala 30:58] + node _T_1936 = cat(_T_1935, _T_1934) @[Cat.scala 30:58] + node _T_1937 = cat(UInt<64>("h2f1000000e2"), UInt<64>("h3cc0000001b")) @[Cat.scala 30:58] + node _T_1938 = cat(UInt<64>("h36f000000b0"), UInt<64>("h1a0000000c9")) @[Cat.scala 30:58] + node _T_1939 = cat(_T_1938, _T_1937) @[Cat.scala 30:58] + node _T_1940 = cat(_T_1939, _T_1936) @[Cat.scala 30:58] + node _T_1941 = cat(_T_1940, _T_1933) @[Cat.scala 30:58] + node _T_1942 = cat(_T_1941, _T_1926) @[Cat.scala 30:58] + node _T_1943 = cat(UInt<64>("h23c000001c2"), UInt<64>("h3600000036d")) @[Cat.scala 30:58] + node _T_1944 = cat(UInt<64>("h2d100000063"), UInt<64>("ha30000036f")) @[Cat.scala 30:58] + node _T_1945 = cat(_T_1944, _T_1943) @[Cat.scala 30:58] + node _T_1946 = cat(UInt<64>("h2830000001f"), UInt<64>("hc0000008f")) @[Cat.scala 30:58] + node _T_1947 = cat(UInt<64>("h3c800000303"), UInt<64>("h1fb0000032c")) @[Cat.scala 30:58] + node _T_1948 = cat(_T_1947, _T_1946) @[Cat.scala 30:58] + node _T_1949 = cat(_T_1948, _T_1945) @[Cat.scala 30:58] + node _T_1950 = cat(UInt<64>("h348000001e8"), UInt<64>("h30d0000020f")) @[Cat.scala 30:58] + node _T_1951 = cat(UInt<64>("h276000000c2"), UInt<64>("hf20000031d")) @[Cat.scala 30:58] + node _T_1952 = cat(_T_1951, _T_1950) @[Cat.scala 30:58] + node _T_1953 = cat(UInt<64>("h31b000003c6"), UInt<64>("h32a00000125")) @[Cat.scala 30:58] + node _T_1954 = cat(UInt<64>("h37500000159"), UInt<64>("h1b300000114")) @[Cat.scala 30:58] + node _T_1955 = cat(_T_1954, _T_1953) @[Cat.scala 30:58] + node _T_1956 = cat(_T_1955, _T_1952) @[Cat.scala 30:58] + node _T_1957 = cat(_T_1956, _T_1949) @[Cat.scala 30:58] + node _T_1958 = cat(UInt<64>("h2b8000000c5"), UInt<64>("h2570000019d")) @[Cat.scala 30:58] + node _T_1959 = cat(UInt<64>("h5d00000074"), UInt<64>("h28300000182")) @[Cat.scala 30:58] + node _T_1960 = cat(_T_1959, _T_1958) @[Cat.scala 30:58] + node _T_1961 = cat(UInt<64>("h311000002a8"), UInt<64>("h2c600000142")) @[Cat.scala 30:58] + node _T_1962 = cat(UInt<64>("h24500000229"), UInt<64>("h700000021a")) @[Cat.scala 30:58] + node _T_1963 = cat(_T_1962, _T_1961) @[Cat.scala 30:58] + node _T_1964 = cat(_T_1963, _T_1960) @[Cat.scala 30:58] + node _T_1965 = cat(UInt<64>("h39b0000036a"), UInt<64>("hc000003c0")) @[Cat.scala 30:58] + node _T_1966 = cat(UInt<64>("h28c000001fa"), UInt<64>("h26700000030")) @[Cat.scala 30:58] + node _T_1967 = cat(_T_1966, _T_1965) @[Cat.scala 30:58] + node _T_1968 = cat(UInt<64>("h1050000021b"), UInt<64>("h16700000382")) @[Cat.scala 30:58] + node _T_1969 = cat(UInt<64>("h261000002fc"), UInt<64>("he9000001ef")) @[Cat.scala 30:58] + node _T_1970 = cat(_T_1969, _T_1968) @[Cat.scala 30:58] + node _T_1971 = cat(_T_1970, _T_1967) @[Cat.scala 30:58] + node _T_1972 = cat(_T_1971, _T_1964) @[Cat.scala 30:58] + node _T_1973 = cat(_T_1972, _T_1957) @[Cat.scala 30:58] + node _T_1974 = cat(_T_1973, _T_1942) @[Cat.scala 30:58] + node _T_1975 = cat(UInt<64>("h21b0000011e"), UInt<64>("h2ae00000325")) @[Cat.scala 30:58] + node _T_1976 = cat(UInt<64>("h23000000344"), UInt<64>("h76000001b0")) @[Cat.scala 30:58] + node _T_1977 = cat(_T_1976, _T_1975) @[Cat.scala 30:58] + node _T_1978 = cat(UInt<64>("h1400000339"), UInt<64>("h2e3000000c0")) @[Cat.scala 30:58] + node _T_1979 = cat(UInt<64>("h3d00000024a"), UInt<64>("h13d0000030a")) @[Cat.scala 30:58] + node _T_1980 = cat(_T_1979, _T_1978) @[Cat.scala 30:58] + node _T_1981 = cat(_T_1980, _T_1977) @[Cat.scala 30:58] + node _T_1982 = cat(UInt<64>("h18200000160"), UInt<64>("h23d00000167")) @[Cat.scala 30:58] + node _T_1983 = cat(UInt<64>("h2970000000b"), UInt<64>("h304000002ea")) @[Cat.scala 30:58] + node _T_1984 = cat(_T_1983, _T_1982) @[Cat.scala 30:58] + node _T_1985 = cat(UInt<64>("hd400000005"), UInt<64>("h1f8000002ed")) @[Cat.scala 30:58] + node _T_1986 = cat(UInt<64>("h38b00000283"), UInt<64>("h37800000198")) @[Cat.scala 30:58] + node _T_1987 = cat(_T_1986, _T_1985) @[Cat.scala 30:58] + node _T_1988 = cat(_T_1987, _T_1984) @[Cat.scala 30:58] + node _T_1989 = cat(_T_1988, _T_1981) @[Cat.scala 30:58] + node _T_1990 = cat(UInt<64>("h2e100000170"), UInt<64>("h1a4000001b9")) @[Cat.scala 30:58] + node _T_1991 = cat(UInt<64>("h19000000a9"), UInt<64>("h20400000061")) @[Cat.scala 30:58] + node _T_1992 = cat(_T_1991, _T_1990) @[Cat.scala 30:58] + node _T_1993 = cat(UInt<64>("h31d0000020f"), UInt<64>("hdb00000167")) @[Cat.scala 30:58] + node _T_1994 = cat(UInt<64>("h1c400000045"), UInt<64>("h2cc000002a0")) @[Cat.scala 30:58] + node _T_1995 = cat(_T_1994, _T_1993) @[Cat.scala 30:58] + node _T_1996 = cat(_T_1995, _T_1992) @[Cat.scala 30:58] + node _T_1997 = cat(UInt<64>("h2ab0000012a"), UInt<64>("h2b400000370")) @[Cat.scala 30:58] + node _T_1998 = cat(UInt<64>("h32f00000147"), UInt<64>("h1cb0000012c")) @[Cat.scala 30:58] + node _T_1999 = cat(_T_1998, _T_1997) @[Cat.scala 30:58] + node _T_2000 = cat(UInt<64>("h2640000033d"), UInt<64>("h1430000039b")) @[Cat.scala 30:58] + node _T_2001 = cat(UInt<64>("h74000001f1"), UInt<64>("hf700000330")) @[Cat.scala 30:58] + node _T_2002 = cat(_T_2001, _T_2000) @[Cat.scala 30:58] + node _T_2003 = cat(_T_2002, _T_1999) @[Cat.scala 30:58] + node _T_2004 = cat(_T_2003, _T_1996) @[Cat.scala 30:58] + node _T_2005 = cat(_T_2004, _T_1989) @[Cat.scala 30:58] + node _T_2006 = cat(UInt<64>("h119000003d5"), UInt<64>("h160000000f3")) @[Cat.scala 30:58] + node _T_2007 = cat(UInt<64>("h122000002c9"), UInt<64>("h2e200000395")) @[Cat.scala 30:58] + node _T_2008 = cat(_T_2007, _T_2006) @[Cat.scala 30:58] + node _T_2009 = cat(UInt<64>("h285000001f7"), UInt<64>("h38d0000028d")) @[Cat.scala 30:58] + node _T_2010 = cat(UInt<64>("h3a40000021f"), UInt<64>("h27100000196")) @[Cat.scala 30:58] + node _T_2011 = cat(_T_2010, _T_2009) @[Cat.scala 30:58] + node _T_2012 = cat(_T_2011, _T_2008) @[Cat.scala 30:58] + node _T_2013 = cat(UInt<64>("h2ad00000130"), UInt<64>("hdc0000006c")) @[Cat.scala 30:58] + node _T_2014 = cat(UInt<64>("h36c000003ba"), UInt<64>("h175000001d0")) @[Cat.scala 30:58] + node _T_2015 = cat(_T_2014, _T_2013) @[Cat.scala 30:58] + node _T_2016 = cat(UInt<64>("h19c00000322"), UInt<64>("h28600000056")) @[Cat.scala 30:58] + node _T_2017 = cat(UInt<64>("h2980000001c"), UInt<64>("h3bb000001be")) @[Cat.scala 30:58] + node _T_2018 = cat(_T_2017, _T_2016) @[Cat.scala 30:58] + node _T_2019 = cat(_T_2018, _T_2015) @[Cat.scala 30:58] + node _T_2020 = cat(_T_2019, _T_2012) @[Cat.scala 30:58] + node _T_2021 = cat(UInt<64>("h30f0000028f"), UInt<64>("h3520000021b")) @[Cat.scala 30:58] + node _T_2022 = cat(UInt<64>("h2c3000001d6"), UInt<64>("h1880000001c")) @[Cat.scala 30:58] + node _T_2023 = cat(_T_2022, _T_2021) @[Cat.scala 30:58] + node _T_2024 = cat(UInt<64>("h20b000003ad"), UInt<64>("h1a6000002df")) @[Cat.scala 30:58] + node _T_2025 = cat(UInt<64>("h25000001c3"), UInt<64>("h2aa00000262")) @[Cat.scala 30:58] + node _T_2026 = cat(_T_2025, _T_2024) @[Cat.scala 30:58] + node _T_2027 = cat(_T_2026, _T_2023) @[Cat.scala 30:58] + node _T_2028 = cat(UInt<64>("h2b000000ed"), UInt<64>("h9c000002a0")) @[Cat.scala 30:58] + node _T_2029 = cat(UInt<64>("h2c9"), UInt<64>("h2ff000002fe")) @[Cat.scala 30:58] + node _T_2030 = cat(_T_2029, _T_2028) @[Cat.scala 30:58] + node _T_2031 = cat(UInt<64>("h14f00000234"), UInt<64>("h1c6000001c6")) @[Cat.scala 30:58] + node _T_2032 = cat(UInt<64>("h2ed000002ed"), UInt<64>("hbb000000bb")) @[Cat.scala 30:58] + node _T_2033 = cat(_T_2032, _T_2031) @[Cat.scala 30:58] + node _T_2034 = cat(_T_2033, _T_2030) @[Cat.scala 30:58] + node _T_2035 = cat(_T_2034, _T_2027) @[Cat.scala 30:58] + node _T_2036 = cat(_T_2035, _T_2020) @[Cat.scala 30:58] + node _T_2037 = cat(_T_2036, _T_2005) @[Cat.scala 30:58] + node _T_2038 = cat(_T_2037, _T_1974) @[Cat.scala 30:58] + node _T_2039 = cat(_T_2038, _T_1911) @[Cat.scala 30:58] + node _T_2040 = cat(UInt<64>("h840000015e"), UInt<64>("h16d0000016d")) @[Cat.scala 30:58] + node _T_2041 = cat(UInt<64>("hd800000248"), UInt<64>("h9900000084")) @[Cat.scala 30:58] + node _T_2042 = cat(_T_2041, _T_2040) @[Cat.scala 30:58] + node _T_2043 = cat(UInt<64>("hd20000026d"), UInt<64>("hd800000248")) @[Cat.scala 30:58] + node _T_2044 = cat(UInt<64>("h23c0000023c"), UInt<64>("hd2000000d2")) @[Cat.scala 30:58] + node _T_2045 = cat(_T_2044, _T_2043) @[Cat.scala 30:58] + node _T_2046 = cat(_T_2045, _T_2042) @[Cat.scala 30:58] + node _T_2047 = cat(UInt<64>("h25100000251"), UInt<64>("h2510000037a")) @[Cat.scala 30:58] + node _T_2048 = cat(UInt<64>("he4000002b6"), UInt<64>("h2b6000002b6")) @[Cat.scala 30:58] + node _T_2049 = cat(_T_2048, _T_2047) @[Cat.scala 30:58] + node _T_2050 = cat(UInt<64>("h2ee00000074"), UInt<64>("h6e0000006e")) @[Cat.scala 30:58] + node _T_2051 = cat(UInt<64>("h1f4000001aa"), UInt<64>("h28600000128")) @[Cat.scala 30:58] + node _T_2052 = cat(_T_2051, _T_2050) @[Cat.scala 30:58] + node _T_2053 = cat(_T_2052, _T_2049) @[Cat.scala 30:58] + node _T_2054 = cat(_T_2053, _T_2046) @[Cat.scala 30:58] + node _T_2055 = cat(UInt<64>("h293000001b4"), UInt<64>("h1b4000001aa")) @[Cat.scala 30:58] + node _T_2056 = cat(UInt<64>("h32c00000306"), UInt<64>("h306000002bd")) @[Cat.scala 30:58] + node _T_2057 = cat(_T_2056, _T_2055) @[Cat.scala 30:58] + node _T_2058 = cat(UInt<64>("h2b8000002a6"), UInt<64>("h2a6000002a6")) @[Cat.scala 30:58] + node _T_2059 = cat(UInt<64>("h1da000001da"), UInt<64>("h234000002b8")) @[Cat.scala 30:58] + node _T_2060 = cat(_T_2059, _T_2058) @[Cat.scala 30:58] + node _T_2061 = cat(_T_2060, _T_2057) @[Cat.scala 30:58] + node _T_2062 = cat(UInt<64>("h21b0000021b"), UInt<64>("h110000001da")) @[Cat.scala 30:58] + node _T_2063 = cat(UInt<64>("hcb000001fd"), UInt<64>("h23900000239")) @[Cat.scala 30:58] + node _T_2064 = cat(_T_2063, _T_2062) @[Cat.scala 30:58] + node _T_2065 = cat(UInt<64>("h2bf000002bf"), UInt<64>("h118000000cb")) @[Cat.scala 30:58] + node _T_2066 = cat(UInt<64>("h1ff000001ff"), UInt<64>("h25e0000029d")) @[Cat.scala 30:58] + node _T_2067 = cat(_T_2066, _T_2065) @[Cat.scala 30:58] + node _T_2068 = cat(_T_2067, _T_2064) @[Cat.scala 30:58] + node _T_2069 = cat(_T_2068, _T_2061) @[Cat.scala 30:58] + node _T_2070 = cat(_T_2069, _T_2054) @[Cat.scala 30:58] + node _T_2071 = cat(UInt<64>("h25000000291"), UInt<64>("h29100000227")) @[Cat.scala 30:58] + node _T_2072 = cat(UInt<64>("h2390000010b"), UInt<64>("h239000000c3")) @[Cat.scala 30:58] + node _T_2073 = cat(_T_2072, _T_2071) @[Cat.scala 30:58] + node _T_2074 = cat(UInt<64>("h24800000151"), UInt<64>("h3200000010b")) @[Cat.scala 30:58] + node _T_2075 = cat(UInt<64>("h28300000386"), UInt<64>("h28300000248")) @[Cat.scala 30:58] + node _T_2076 = cat(_T_2075, _T_2074) @[Cat.scala 30:58] + node _T_2077 = cat(_T_2076, _T_2073) @[Cat.scala 30:58] + node _T_2078 = cat(UInt<64>("h1e9000001e9"), UInt<64>("h17000000170")) @[Cat.scala 30:58] + node _T_2079 = cat(UInt<64>("h2500000033a"), UInt<64>("h1480000033a")) @[Cat.scala 30:58] + node _T_2080 = cat(_T_2079, _T_2078) @[Cat.scala 30:58] + node _T_2081 = cat(UInt<64>("h18400000184"), UInt<64>("h250000003a5")) @[Cat.scala 30:58] + node _T_2082 = cat(UInt<64>("h28900000289"), UInt<64>("h2890000021f")) @[Cat.scala 30:58] + node _T_2083 = cat(_T_2082, _T_2081) @[Cat.scala 30:58] + node _T_2084 = cat(_T_2083, _T_2080) @[Cat.scala 30:58] + node _T_2085 = cat(_T_2084, _T_2077) @[Cat.scala 30:58] + node _T_2086 = cat(UInt<64>("h32e00000289"), UInt<64>("h3d300000236")) @[Cat.scala 30:58] + node _T_2087 = cat(UInt<64>("hb5000000b5"), UInt<64>("h29100000291")) @[Cat.scala 30:58] + node _T_2088 = cat(_T_2087, _T_2086) @[Cat.scala 30:58] + node _T_2089 = cat(UInt<64>("h35b0000035b"), UInt<64>("hd0000000b5")) @[Cat.scala 30:58] + node _T_2090 = cat(UInt<64>("h2c000000120"), UInt<64>("h27500000275")) @[Cat.scala 30:58] + node _T_2091 = cat(_T_2090, _T_2089) @[Cat.scala 30:58] + node _T_2092 = cat(_T_2091, _T_2088) @[Cat.scala 30:58] + node _T_2093 = cat(UInt<64>("hfd0000015d"), UInt<64>("h2c00000015d")) @[Cat.scala 30:58] + node _T_2094 = cat(UInt<64>("h2cb00000376"), UInt<64>("h2cb000000fd")) @[Cat.scala 30:58] + node _T_2095 = cat(_T_2094, _T_2093) @[Cat.scala 30:58] + node _T_2096 = cat(UInt<64>("h21a0000019f"), UInt<64>("h19f000001ae")) @[Cat.scala 30:58] + node _T_2097 = cat(UInt<64>("h2bc000002f9"), UInt<64>("h2bc00000240")) @[Cat.scala 30:58] + node _T_2098 = cat(_T_2097, _T_2096) @[Cat.scala 30:58] + node _T_2099 = cat(_T_2098, _T_2095) @[Cat.scala 30:58] + node _T_2100 = cat(_T_2099, _T_2092) @[Cat.scala 30:58] + node _T_2101 = cat(_T_2100, _T_2085) @[Cat.scala 30:58] + node _T_2102 = cat(_T_2101, _T_2070) @[Cat.scala 30:58] + node _T_2103 = cat(UInt<64>("h1de000001de"), UInt<64>("hf1000000f1")) @[Cat.scala 30:58] + node _T_2104 = cat(UInt<64>("h2b5000001f3"), UInt<64>("h1f3000001de")) @[Cat.scala 30:58] + node _T_2105 = cat(_T_2104, _T_2103) @[Cat.scala 30:58] + node _T_2106 = cat(UInt<64>("h1a0000001a0"), UInt<64>("h1a000000193")) @[Cat.scala 30:58] + node _T_2107 = cat(UInt<64>("h26c000002a4"), UInt<64>("h128000001bc")) @[Cat.scala 30:58] + node _T_2108 = cat(_T_2107, _T_2106) @[Cat.scala 30:58] + node _T_2109 = cat(_T_2108, _T_2105) @[Cat.scala 30:58] + node _T_2110 = cat(UInt<64>("he0000000e0"), UInt<64>("h13d0000026c")) @[Cat.scala 30:58] + node _T_2111 = cat(UInt<64>("h21c0000021c"), UInt<64>("h21c0000015f")) @[Cat.scala 30:58] + node _T_2112 = cat(_T_2111, _T_2110) @[Cat.scala 30:58] + node _T_2113 = cat(UInt<64>("h20f000000a9"), UInt<64>("ha900000120")) @[Cat.scala 30:58] + node _T_2114 = cat(UInt<64>("h18500000185"), UInt<64>("h20f0000025e")) @[Cat.scala 30:58] + node _T_2115 = cat(_T_2114, _T_2113) @[Cat.scala 30:58] + node _T_2116 = cat(_T_2115, _T_2112) @[Cat.scala 30:58] + node _T_2117 = cat(_T_2116, _T_2109) @[Cat.scala 30:58] + node _T_2118 = cat(UInt<64>("h2d0000001c7"), UInt<64>("h31c00000185")) @[Cat.scala 30:58] + node _T_2119 = cat(UInt<64>("h2e90000016f"), UInt<64>("h2d0000001c7")) @[Cat.scala 30:58] + node _T_2120 = cat(_T_2119, _T_2118) @[Cat.scala 30:58] + node _T_2121 = cat(UInt<64>("h24800000166"), UInt<64>("h1660000016f")) @[Cat.scala 30:58] + node _T_2122 = cat(UInt<64>("h3550000010f"), UInt<64>("h10f00000248")) @[Cat.scala 30:58] + node _T_2123 = cat(_T_2122, _T_2121) @[Cat.scala 30:58] + node _T_2124 = cat(_T_2123, _T_2120) @[Cat.scala 30:58] + node _T_2125 = cat(UInt<64>("h21300000193"), UInt<64>("h31400000355")) @[Cat.scala 30:58] + node _T_2126 = cat(UInt<64>("h1cd00000205"), UInt<64>("h20500000205")) @[Cat.scala 30:58] + node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 30:58] + node _T_2128 = cat(UInt<64>("h16600000307"), UInt<64>("h1cd0000022f")) @[Cat.scala 30:58] + node _T_2129 = cat(UInt<64>("h2ac0000014c"), UInt<64>("h14c00000166")) @[Cat.scala 30:58] + node _T_2130 = cat(_T_2129, _T_2128) @[Cat.scala 30:58] + node _T_2131 = cat(_T_2130, _T_2127) @[Cat.scala 30:58] + node _T_2132 = cat(_T_2131, _T_2124) @[Cat.scala 30:58] + node _T_2133 = cat(_T_2132, _T_2117) @[Cat.scala 30:58] + node _T_2134 = cat(UInt<64>("h1be00000256"), UInt<64>("h2ac000002ac")) @[Cat.scala 30:58] + node _T_2135 = cat(UInt<64>("h1370000007d"), UInt<64>("h1370000008f")) @[Cat.scala 30:58] + node _T_2136 = cat(_T_2135, _T_2134) @[Cat.scala 30:58] + node _T_2137 = cat(UInt<64>("h22d000003a5"), UInt<64>("h2e7000002e7")) @[Cat.scala 30:58] + node _T_2138 = cat(UInt<64>("h22d0000022d"), UInt<64>("h22d0000031f")) @[Cat.scala 30:58] + node _T_2139 = cat(_T_2138, _T_2137) @[Cat.scala 30:58] + node _T_2140 = cat(_T_2139, _T_2136) @[Cat.scala 30:58] + node _T_2141 = cat(UInt<64>("h28800000288"), UInt<64>("h31c00000229")) @[Cat.scala 30:58] + node _T_2142 = cat(UInt<64>("h29a0000037b"), UInt<64>("h37b00000288")) @[Cat.scala 30:58] + node _T_2143 = cat(_T_2142, _T_2141) @[Cat.scala 30:58] + node _T_2144 = cat(UInt<64>("h20200000031"), UInt<64>("h2020000011f")) @[Cat.scala 30:58] + node _T_2145 = cat(UInt<64>("h3550000005f"), UInt<64>("h22d00000056")) @[Cat.scala 30:58] + node _T_2146 = cat(_T_2145, _T_2144) @[Cat.scala 30:58] + node _T_2147 = cat(_T_2146, _T_2143) @[Cat.scala 30:58] + node _T_2148 = cat(_T_2147, _T_2140) @[Cat.scala 30:58] + node _T_2149 = cat(UInt<64>("h1b8000001b9"), UInt<64>("h1b9000001b9")) @[Cat.scala 30:58] + node _T_2150 = cat(UInt<64>("h18c00000266"), UInt<64>("h2660000024b")) @[Cat.scala 30:58] + node _T_2151 = cat(_T_2150, _T_2149) @[Cat.scala 30:58] + node _T_2152 = cat(UInt<64>("h1100000118"), UInt<64>("h1180000017e")) @[Cat.scala 30:58] + node _T_2153 = cat(UInt<64>("h12300000333"), UInt<64>("haa00000328")) @[Cat.scala 30:58] + node _T_2154 = cat(_T_2153, _T_2152) @[Cat.scala 30:58] + node _T_2155 = cat(_T_2154, _T_2151) @[Cat.scala 30:58] + node _T_2156 = cat(UInt<64>("h1c20000017c"), UInt<64>("h15800000158")) @[Cat.scala 30:58] + node _T_2157 = cat(UInt<64>("h39500000200"), UInt<64>("h20000000200")) @[Cat.scala 30:58] + node _T_2158 = cat(_T_2157, _T_2156) @[Cat.scala 30:58] + node _T_2159 = cat(UInt<64>("h3280000021b"), UInt<64>("h21b00000395")) @[Cat.scala 30:58] + node _T_2160 = cat(UInt<64>("h21900000372"), UInt<64>("h37700000372")) @[Cat.scala 30:58] + node _T_2161 = cat(_T_2160, _T_2159) @[Cat.scala 30:58] + node _T_2162 = cat(_T_2161, _T_2158) @[Cat.scala 30:58] + node _T_2163 = cat(_T_2162, _T_2155) @[Cat.scala 30:58] + node _T_2164 = cat(_T_2163, _T_2148) @[Cat.scala 30:58] + node _T_2165 = cat(_T_2164, _T_2133) @[Cat.scala 30:58] + node _T_2166 = cat(_T_2165, _T_2102) @[Cat.scala 30:58] + node _T_2167 = cat(UInt<64>("h2bd000002bd"), UInt<64>("h26400000219")) @[Cat.scala 30:58] + node _T_2168 = cat(UInt<64>("h1df000001df"), UInt<64>("h1df000002bd")) @[Cat.scala 30:58] + node _T_2169 = cat(_T_2168, _T_2167) @[Cat.scala 30:58] + node _T_2170 = cat(UInt<64>("h1600000016"), UInt<64>("h9700000237")) @[Cat.scala 30:58] + node _T_2171 = cat(UInt<64>("h29900000238"), UInt<64>("h23800000238")) @[Cat.scala 30:58] + node _T_2172 = cat(_T_2171, _T_2170) @[Cat.scala 30:58] + node _T_2173 = cat(_T_2172, _T_2169) @[Cat.scala 30:58] + node _T_2174 = cat(UInt<64>("h1b2000001a7"), UInt<64>("h1a700000299")) @[Cat.scala 30:58] + node _T_2175 = cat(UInt<64>("h1180000009e"), UInt<64>("h118000001b2")) @[Cat.scala 30:58] + node _T_2176 = cat(_T_2175, _T_2174) @[Cat.scala 30:58] + node _T_2177 = cat(UInt<64>("h2b0000000f7"), UInt<64>("h18b00000054")) @[Cat.scala 30:58] + node _T_2178 = cat(UInt<64>("h1dc000001b3"), UInt<64>("h1dc000000f7")) @[Cat.scala 30:58] + node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 30:58] + node _T_2180 = cat(_T_2179, _T_2176) @[Cat.scala 30:58] + node _T_2181 = cat(_T_2180, _T_2173) @[Cat.scala 30:58] + node _T_2182 = cat(UInt<64>("h2d900000318"), UInt<64>("h31800000318")) @[Cat.scala 30:58] + node _T_2183 = cat(UInt<64>("hec0000019e"), UInt<64>("h109000001e6")) @[Cat.scala 30:58] + node _T_2184 = cat(_T_2183, _T_2182) @[Cat.scala 30:58] + node _T_2185 = cat(UInt<64>("hd600000171"), UInt<64>("hec00000171")) @[Cat.scala 30:58] + node _T_2186 = cat(UInt<64>("h1f700000206"), UInt<64>("hb400000206")) @[Cat.scala 30:58] + node _T_2187 = cat(_T_2186, _T_2185) @[Cat.scala 30:58] + node _T_2188 = cat(_T_2187, _T_2184) @[Cat.scala 30:58] + node _T_2189 = cat(UInt<64>("h11c00000254"), UInt<64>("h254000002aa")) @[Cat.scala 30:58] + node _T_2190 = cat(UInt<64>("h1f3000001f3"), UInt<64>("h10800000108")) @[Cat.scala 30:58] + node _T_2191 = cat(_T_2190, _T_2189) @[Cat.scala 30:58] + node _T_2192 = cat(UInt<64>("h25700000257"), UInt<64>("h15a0000015a")) @[Cat.scala 30:58] + node _T_2193 = cat(UInt<64>("h2db000002db"), UInt<64>("hd7000000d7")) @[Cat.scala 30:58] + node _T_2194 = cat(_T_2193, _T_2192) @[Cat.scala 30:58] + node _T_2195 = cat(_T_2194, _T_2191) @[Cat.scala 30:58] + node _T_2196 = cat(_T_2195, _T_2188) @[Cat.scala 30:58] + node _T_2197 = cat(_T_2196, _T_2181) @[Cat.scala 30:58] + node _T_2198 = cat(UInt<64>("hfb0000026b"), UInt<64>("h292000002b0")) @[Cat.scala 30:58] + node _T_2199 = cat(UInt<64>("h22b0000022b"), UInt<64>("h83000000fb")) @[Cat.scala 30:58] + node _T_2200 = cat(_T_2199, _T_2198) @[Cat.scala 30:58] + node _T_2201 = cat(UInt<64>("h21000000210"), UInt<64>("h29b0000022b")) @[Cat.scala 30:58] + node _T_2202 = cat(UInt<64>("h1e7000001e7"), UInt<64>("h1e700000210")) @[Cat.scala 30:58] + node _T_2203 = cat(_T_2202, _T_2201) @[Cat.scala 30:58] + node _T_2204 = cat(_T_2203, _T_2200) @[Cat.scala 30:58] + node _T_2205 = cat(UInt<64>("h11f0000011f"), UInt<64>("h2f1000002f1")) @[Cat.scala 30:58] + node _T_2206 = cat(UInt<64>("he00000130"), UInt<64>("h27200000272")) @[Cat.scala 30:58] + node _T_2207 = cat(_T_2206, _T_2205) @[Cat.scala 30:58] + node _T_2208 = cat(UInt<64>("h193000002dd"), UInt<64>("h19300000130")) @[Cat.scala 30:58] + node _T_2209 = cat(UInt<64>("h2bf000002bf"), UInt<64>("h2bf000002dd")) @[Cat.scala 30:58] + node _T_2210 = cat(_T_2209, _T_2208) @[Cat.scala 30:58] + node _T_2211 = cat(_T_2210, _T_2207) @[Cat.scala 30:58] + node _T_2212 = cat(_T_2211, _T_2204) @[Cat.scala 30:58] + node _T_2213 = cat(UInt<64>("h196000002d2"), UInt<64>("h332000002d2")) @[Cat.scala 30:58] + node _T_2214 = cat(UInt<64>("h3580000036a"), UInt<64>("h36a00000196")) @[Cat.scala 30:58] + node _T_2215 = cat(_T_2214, _T_2213) @[Cat.scala 30:58] + node _T_2216 = cat(UInt<64>("h560000005b"), UInt<64>("h2ec000002ec")) @[Cat.scala 30:58] + node _T_2217 = cat(UInt<64>("h2940000017a"), UInt<64>("h17a0000005b")) @[Cat.scala 30:58] + node _T_2218 = cat(_T_2217, _T_2216) @[Cat.scala 30:58] + node _T_2219 = cat(_T_2218, _T_2215) @[Cat.scala 30:58] + node _T_2220 = cat(UInt<64>("h9900000099"), UInt<64>("h9900000069")) @[Cat.scala 30:58] + node _T_2221 = cat(UInt<64>("h19c0000028b"), UInt<64>("h790000017d")) @[Cat.scala 30:58] + node _T_2222 = cat(_T_2221, _T_2220) @[Cat.scala 30:58] + node _T_2223 = cat(UInt<64>("hec00000164"), UInt<64>("h19c00000339")) @[Cat.scala 30:58] + node _T_2224 = cat(UInt<64>("h1a700000094"), UInt<64>("h9400000094")) @[Cat.scala 30:58] + node _T_2225 = cat(_T_2224, _T_2223) @[Cat.scala 30:58] + node _T_2226 = cat(_T_2225, _T_2222) @[Cat.scala 30:58] + node _T_2227 = cat(_T_2226, _T_2219) @[Cat.scala 30:58] + node _T_2228 = cat(_T_2227, _T_2212) @[Cat.scala 30:58] + node _T_2229 = cat(_T_2228, _T_2197) @[Cat.scala 30:58] + node _T_2230 = cat(UInt<64>("h26d000000d8"), UInt<64>("hd80000008c")) @[Cat.scala 30:58] + node _T_2231 = cat(UInt<64>("h21500000169"), UInt<64>("h1690000026d")) @[Cat.scala 30:58] + node _T_2232 = cat(_T_2231, _T_2230) @[Cat.scala 30:58] + node _T_2233 = cat(UInt<64>("h287000002cb"), UInt<64>("h2f5000002f5")) @[Cat.scala 30:58] + node _T_2234 = cat(UInt<64>("h25000000250"), UInt<64>("h28700000287")) @[Cat.scala 30:58] + node _T_2235 = cat(_T_2234, _T_2233) @[Cat.scala 30:58] + node _T_2236 = cat(_T_2235, _T_2232) @[Cat.scala 30:58] + node _T_2237 = cat(UInt<64>("had000000ad"), UInt<64>("h2aa00000250")) @[Cat.scala 30:58] + node _T_2238 = cat(UInt<64>("h1ed00000079"), UInt<64>("h3f0000003f")) @[Cat.scala 30:58] + node _T_2239 = cat(_T_2238, _T_2237) @[Cat.scala 30:58] + node _T_2240 = cat(UInt<64>("h2f600000219"), UInt<64>("h21900000085")) @[Cat.scala 30:58] + node _T_2241 = cat(UInt<64>("h28300000283"), UInt<64>("h283000002f6")) @[Cat.scala 30:58] + node _T_2242 = cat(_T_2241, _T_2240) @[Cat.scala 30:58] + node _T_2243 = cat(_T_2242, _T_2239) @[Cat.scala 30:58] + node _T_2244 = cat(_T_2243, _T_2236) @[Cat.scala 30:58] + node _T_2245 = cat(UInt<64>("h12f00000081"), UInt<64>("h19f000001b2")) @[Cat.scala 30:58] + node _T_2246 = cat(UInt<64>("h34f000001b6"), UInt<64>("h12f00000081")) @[Cat.scala 30:58] + node _T_2247 = cat(_T_2246, _T_2245) @[Cat.scala 30:58] + node _T_2248 = cat(UInt<64>("hff000000ff"), UInt<64>("h1b50000034f")) @[Cat.scala 30:58] + node _T_2249 = cat(UInt<64>("h2a300000199"), UInt<64>("h1de0000010d")) @[Cat.scala 30:58] + node _T_2250 = cat(_T_2249, _T_2248) @[Cat.scala 30:58] + node _T_2251 = cat(_T_2250, _T_2247) @[Cat.scala 30:58] + node _T_2252 = cat(UInt<64>("h2cf00000274"), UInt<64>("h2a300000274")) @[Cat.scala 30:58] + node _T_2253 = cat(UInt<64>("h1c200000225"), UInt<64>("h22500000225")) @[Cat.scala 30:58] + node _T_2254 = cat(_T_2253, _T_2252) @[Cat.scala 30:58] + node _T_2255 = cat(UInt<64>("hab00000234"), UInt<64>("h23400000234")) @[Cat.scala 30:58] + node _T_2256 = cat(UInt<64>("h28600000286"), UInt<64>("h9b0000009b")) @[Cat.scala 30:58] + node _T_2257 = cat(_T_2256, _T_2255) @[Cat.scala 30:58] + node _T_2258 = cat(_T_2257, _T_2254) @[Cat.scala 30:58] + node _T_2259 = cat(_T_2258, _T_2251) @[Cat.scala 30:58] + node _T_2260 = cat(_T_2259, _T_2244) @[Cat.scala 30:58] + node _T_2261 = cat(UInt<64>("h1fd000001f5"), UInt<64>("h1c4000001f5")) @[Cat.scala 30:58] + node _T_2262 = cat(UInt<64>("h2f1000002f1"), UInt<64>("h1fd000001fd")) @[Cat.scala 30:58] + node _T_2263 = cat(_T_2262, _T_2261) @[Cat.scala 30:58] + node _T_2264 = cat(UInt<64>("hca00000051"), UInt<64>("h51000001aa")) @[Cat.scala 30:58] + node _T_2265 = cat(UInt<64>("h9900000099"), UInt<64>("h1e3000001e3")) @[Cat.scala 30:58] + node _T_2266 = cat(_T_2265, _T_2264) @[Cat.scala 30:58] + node _T_2267 = cat(_T_2266, _T_2263) @[Cat.scala 30:58] + node _T_2268 = cat(UInt<64>("h16500000186"), UInt<64>("h18600000153")) @[Cat.scala 30:58] + node _T_2269 = cat(UInt<64>("h2590000039a"), UInt<64>("hab00000165")) @[Cat.scala 30:58] + node _T_2270 = cat(_T_2269, _T_2268) @[Cat.scala 30:58] + node _T_2271 = cat(UInt<64>("h1f000000148"), UInt<64>("h14800000259")) @[Cat.scala 30:58] + node _T_2272 = cat(UInt<64>("h204000001ba"), UInt<64>("h1ba000001f0")) @[Cat.scala 30:58] + node _T_2273 = cat(_T_2272, _T_2271) @[Cat.scala 30:58] + node _T_2274 = cat(_T_2273, _T_2270) @[Cat.scala 30:58] + node _T_2275 = cat(_T_2274, _T_2267) @[Cat.scala 30:58] + node _T_2276 = cat(UInt<64>("h11400000114"), UInt<64>("h28100000281")) @[Cat.scala 30:58] + node _T_2277 = cat(UInt<64>("h25800000258"), UInt<64>("h31200000312")) @[Cat.scala 30:58] + node _T_2278 = cat(_T_2277, _T_2276) @[Cat.scala 30:58] + node _T_2279 = cat(UInt<64>("h37700000367"), UInt<64>("h34a0000025b")) @[Cat.scala 30:58] + node _T_2280 = cat(UInt<64>("h19400000113"), UInt<64>("h26200000377")) @[Cat.scala 30:58] + node _T_2281 = cat(_T_2280, _T_2279) @[Cat.scala 30:58] + node _T_2282 = cat(_T_2281, _T_2278) @[Cat.scala 30:58] + node _T_2283 = cat(UInt<64>("h2e9000000ea"), UInt<64>("hea000000ed")) @[Cat.scala 30:58] + node _T_2284 = cat(UInt<64>("h1650000020e"), UInt<64>("h235000002e9")) @[Cat.scala 30:58] + node _T_2285 = cat(_T_2284, _T_2283) @[Cat.scala 30:58] + node _T_2286 = cat(UInt<64>("h1b900000323"), UInt<64>("h1b900000165")) @[Cat.scala 30:58] + node _T_2287 = cat(UInt<64>("h2f0000002ef"), UInt<64>("h2ef000002ef")) @[Cat.scala 30:58] + node _T_2288 = cat(_T_2287, _T_2286) @[Cat.scala 30:58] + node _T_2289 = cat(_T_2288, _T_2285) @[Cat.scala 30:58] + node _T_2290 = cat(_T_2289, _T_2282) @[Cat.scala 30:58] + node _T_2291 = cat(_T_2290, _T_2275) @[Cat.scala 30:58] + node _T_2292 = cat(_T_2291, _T_2260) @[Cat.scala 30:58] + node _T_2293 = cat(_T_2292, _T_2229) @[Cat.scala 30:58] + node _T_2294 = cat(_T_2293, _T_2166) @[Cat.scala 30:58] + node _T_2295 = cat(UInt<64>("h2c5000001ca"), UInt<64>("h2d600000118")) @[Cat.scala 30:58] + node _T_2296 = cat(UInt<64>("hc9000001c6"), UInt<64>("h1c6000001ca")) @[Cat.scala 30:58] + node _T_2297 = cat(_T_2296, _T_2295) @[Cat.scala 30:58] + node _T_2298 = cat(UInt<64>("h35000001cb"), UInt<64>("h1cb000001cb")) @[Cat.scala 30:58] + node _T_2299 = cat(UInt<64>("h17900000179"), UInt<64>("hfd00000035")) @[Cat.scala 30:58] + node _T_2300 = cat(_T_2299, _T_2298) @[Cat.scala 30:58] + node _T_2301 = cat(_T_2300, _T_2297) @[Cat.scala 30:58] + node _T_2302 = cat(UInt<64>("h1a0000001fc"), UInt<64>("h8d00000179")) @[Cat.scala 30:58] + node _T_2303 = cat(UInt<64>("h1e0000002eb"), UInt<64>("h2eb000002bc")) @[Cat.scala 30:58] + node _T_2304 = cat(_T_2303, _T_2302) @[Cat.scala 30:58] + node _T_2305 = cat(UInt<64>("h1f3000001f3"), UInt<64>("h1de000001e0")) @[Cat.scala 30:58] + node _T_2306 = cat(UInt<64>("hb4000000b4"), UInt<64>("h2c5000002c5")) @[Cat.scala 30:58] + node _T_2307 = cat(_T_2306, _T_2305) @[Cat.scala 30:58] + node _T_2308 = cat(_T_2307, _T_2304) @[Cat.scala 30:58] + node _T_2309 = cat(_T_2308, _T_2301) @[Cat.scala 30:58] + node _T_2310 = cat(UInt<64>("h2d5000002b3"), UInt<64>("h1e200000173")) @[Cat.scala 30:58] + node _T_2311 = cat(UInt<64>("hba000003b1"), UInt<64>("h2d500000369")) @[Cat.scala 30:58] + node _T_2312 = cat(_T_2311, _T_2310) @[Cat.scala 30:58] + node _T_2313 = cat(UInt<64>("h2d1000002d1"), UInt<64>("h20e0000020e")) @[Cat.scala 30:58] + node _T_2314 = cat(UInt<64>("hf7000001b3"), UInt<64>("h1b3000001b3")) @[Cat.scala 30:58] + node _T_2315 = cat(_T_2314, _T_2313) @[Cat.scala 30:58] + node _T_2316 = cat(_T_2315, _T_2312) @[Cat.scala 30:58] + node _T_2317 = cat(UInt<64>("h1d0000001f1"), UInt<64>("h1d0000000f7")) @[Cat.scala 30:58] + node _T_2318 = cat(UInt<64>("h15c0000015c"), UInt<64>("h16a0000016a")) @[Cat.scala 30:58] + node _T_2319 = cat(_T_2318, _T_2317) @[Cat.scala 30:58] + node _T_2320 = cat(UInt<64>("h78000000fa"), UInt<64>("he9000000fa")) @[Cat.scala 30:58] + node _T_2321 = cat(UInt<64>("h23d0000023d"), UInt<64>("hfa000000fa")) @[Cat.scala 30:58] + node _T_2322 = cat(_T_2321, _T_2320) @[Cat.scala 30:58] + node _T_2323 = cat(_T_2322, _T_2319) @[Cat.scala 30:58] + node _T_2324 = cat(_T_2323, _T_2316) @[Cat.scala 30:58] + node _T_2325 = cat(_T_2324, _T_2309) @[Cat.scala 30:58] + node _T_2326 = cat(UInt<64>("h2e7000002ed"), UInt<64>("hc30000023d")) @[Cat.scala 30:58] + node _T_2327 = cat(UInt<64>("h1b7000001f6"), UInt<64>("h1f6000002e7")) @[Cat.scala 30:58] + node _T_2328 = cat(_T_2327, _T_2326) @[Cat.scala 30:58] + node _T_2329 = cat(UInt<64>("haa00000193"), UInt<64>("h19300000337")) @[Cat.scala 30:58] + node _T_2330 = cat(UInt<64>("h27900000279"), UInt<64>("ha0000000a0")) @[Cat.scala 30:58] + node _T_2331 = cat(_T_2330, _T_2329) @[Cat.scala 30:58] + node _T_2332 = cat(_T_2331, _T_2328) @[Cat.scala 30:58] + node _T_2333 = cat(UInt<64>("h140000000ca"), UInt<64>("h12100000121")) @[Cat.scala 30:58] + node _T_2334 = cat(UInt<64>("h27c0000027c"), UInt<64>("h140000000ca")) @[Cat.scala 30:58] + node _T_2335 = cat(_T_2334, _T_2333) @[Cat.scala 30:58] + node _T_2336 = cat(UInt<64>("h18a0000018a"), UInt<64>("h7600000076")) @[Cat.scala 30:58] + node _T_2337 = cat(UInt<64>("h33000000330"), UInt<64>("h6b0000006b")) @[Cat.scala 30:58] + node _T_2338 = cat(_T_2337, _T_2336) @[Cat.scala 30:58] + node _T_2339 = cat(_T_2338, _T_2335) @[Cat.scala 30:58] + node _T_2340 = cat(_T_2339, _T_2332) @[Cat.scala 30:58] + node _T_2341 = cat(UInt<64>("h9d0000009d"), UInt<64>("h18400000184")) @[Cat.scala 30:58] + node _T_2342 = cat(UInt<64>("h2ba00000010"), UInt<64>("h1000000024")) @[Cat.scala 30:58] + node _T_2343 = cat(_T_2342, _T_2341) @[Cat.scala 30:58] + node _T_2344 = cat(UInt<64>("h2a5000000cc"), UInt<64>("h2b7000002ba")) @[Cat.scala 30:58] + node _T_2345 = cat(UInt<64>("h2560000023e"), UInt<64>("h2560000023e")) @[Cat.scala 30:58] + node _T_2346 = cat(_T_2345, _T_2344) @[Cat.scala 30:58] + node _T_2347 = cat(_T_2346, _T_2343) @[Cat.scala 30:58] + node _T_2348 = cat(UInt<64>("h2ea0000020e"), UInt<64>("h3380000020e")) @[Cat.scala 30:58] + node _T_2349 = cat(UInt<64>("h1ff000001ce"), UInt<64>("h1ce000000ef")) @[Cat.scala 30:58] + node _T_2350 = cat(_T_2349, _T_2348) @[Cat.scala 30:58] + node _T_2351 = cat(UInt<64>("h216000002c2"), UInt<64>("h216000002ba")) @[Cat.scala 30:58] + node _T_2352 = cat(UInt<64>("h1ac00000054"), UInt<64>("h1ac000001b8")) @[Cat.scala 30:58] + node _T_2353 = cat(_T_2352, _T_2351) @[Cat.scala 30:58] + node _T_2354 = cat(_T_2353, _T_2350) @[Cat.scala 30:58] + node _T_2355 = cat(_T_2354, _T_2347) @[Cat.scala 30:58] + node _T_2356 = cat(_T_2355, _T_2340) @[Cat.scala 30:58] + node _T_2357 = cat(_T_2356, _T_2325) @[Cat.scala 30:58] + node _T_2358 = cat(UInt<64>("h2d60000031f"), UInt<64>("h2dc000002dc")) @[Cat.scala 30:58] + node _T_2359 = cat(UInt<64>("h17500000200"), UInt<64>("h223000002be")) @[Cat.scala 30:58] + node _T_2360 = cat(_T_2359, _T_2358) @[Cat.scala 30:58] + node _T_2361 = cat(UInt<64>("hd7000001ec"), UInt<64>("h1ec00000175")) @[Cat.scala 30:58] + node _T_2362 = cat(UInt<64>("h5300000053"), UInt<64>("hd7000000d7")) @[Cat.scala 30:58] + node _T_2363 = cat(_T_2362, _T_2361) @[Cat.scala 30:58] + node _T_2364 = cat(_T_2363, _T_2360) @[Cat.scala 30:58] + node _T_2365 = cat(UInt<64>("h1ad00000067"), UInt<64>("h6700000067")) @[Cat.scala 30:58] + node _T_2366 = cat(UInt<64>("h28300000291"), UInt<64>("h2910000031a")) @[Cat.scala 30:58] + node _T_2367 = cat(_T_2366, _T_2365) @[Cat.scala 30:58] + node _T_2368 = cat(UInt<64>("h34200000370"), UInt<64>("h37000000283")) @[Cat.scala 30:58] + node _T_2369 = cat(UInt<64>("h20c000001ce"), UInt<64>("h29300000293")) @[Cat.scala 30:58] + node _T_2370 = cat(_T_2369, _T_2368) @[Cat.scala 30:58] + node _T_2371 = cat(_T_2370, _T_2367) @[Cat.scala 30:58] + node _T_2372 = cat(_T_2371, _T_2364) @[Cat.scala 30:58] + node _T_2373 = cat(UInt<64>("h23100000072"), UInt<64>("h72000001ce")) @[Cat.scala 30:58] + node _T_2374 = cat(UInt<64>("h12f0000012f"), UInt<64>("h21100000231")) @[Cat.scala 30:58] + node _T_2375 = cat(_T_2374, _T_2373) @[Cat.scala 30:58] + node _T_2376 = cat(UInt<64>("h19900000388"), UInt<64>("h2ca000002ca")) @[Cat.scala 30:58] + node _T_2377 = cat(UInt<64>("h19700000197"), UInt<64>("h18300000183")) @[Cat.scala 30:58] + node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 30:58] + node _T_2379 = cat(_T_2378, _T_2375) @[Cat.scala 30:58] + node _T_2380 = cat(UInt<64>("h22f000001b4"), UInt<64>("h13100000131")) @[Cat.scala 30:58] + node _T_2381 = cat(UInt<64>("h25000000250"), UInt<64>("h38500000385")) @[Cat.scala 30:58] + node _T_2382 = cat(_T_2381, _T_2380) @[Cat.scala 30:58] + node _T_2383 = cat(UInt<64>("h1f100000199"), UInt<64>("h2b300000200")) @[Cat.scala 30:58] + node _T_2384 = cat(UInt<64>("h1ab000000ca"), UInt<64>("hca0000012e")) @[Cat.scala 30:58] + node _T_2385 = cat(_T_2384, _T_2383) @[Cat.scala 30:58] + node _T_2386 = cat(_T_2385, _T_2382) @[Cat.scala 30:58] + node _T_2387 = cat(_T_2386, _T_2379) @[Cat.scala 30:58] + node _T_2388 = cat(_T_2387, _T_2372) @[Cat.scala 30:58] + node _T_2389 = cat(UInt<64>("h1e000000265"), UInt<64>("h3ac00000265")) @[Cat.scala 30:58] + node _T_2390 = cat(UInt<64>("h2ac00000209"), UInt<64>("h1e0000001e0")) @[Cat.scala 30:58] + node _T_2391 = cat(_T_2390, _T_2389) @[Cat.scala 30:58] + node _T_2392 = cat(UInt<64>("h263000000b9"), UInt<64>("h263000002ac")) @[Cat.scala 30:58] + node _T_2393 = cat(UInt<64>("h6b0000006b"), UInt<64>("h13800000138")) @[Cat.scala 30:58] + node _T_2394 = cat(_T_2393, _T_2392) @[Cat.scala 30:58] + node _T_2395 = cat(_T_2394, _T_2391) @[Cat.scala 30:58] + node _T_2396 = cat(UInt<64>("h18300000183"), UInt<64>("h1120000006f")) @[Cat.scala 30:58] + node _T_2397 = cat(UInt<64>("h1e6000000f2"), UInt<64>("hb9000000f2")) @[Cat.scala 30:58] + node _T_2398 = cat(_T_2397, _T_2396) @[Cat.scala 30:58] + node _T_2399 = cat(UInt<64>("h2ba00000069"), UInt<64>("h69000001e6")) @[Cat.scala 30:58] + node _T_2400 = cat(UInt<64>("h30200000302"), UInt<64>("h2ed000002ed")) @[Cat.scala 30:58] + node _T_2401 = cat(_T_2400, _T_2399) @[Cat.scala 30:58] + node _T_2402 = cat(_T_2401, _T_2398) @[Cat.scala 30:58] + node _T_2403 = cat(_T_2402, _T_2395) @[Cat.scala 30:58] + node _T_2404 = cat(UInt<64>("h146000001b3"), UInt<64>("h28400000302")) @[Cat.scala 30:58] + node _T_2405 = cat(UInt<64>("h25000000a1"), UInt<64>("ha1000000a1")) @[Cat.scala 30:58] + node _T_2406 = cat(_T_2405, _T_2404) @[Cat.scala 30:58] + node _T_2407 = cat(UInt<64>("h25d0000025d"), UInt<64>("h25d00000197")) @[Cat.scala 30:58] + node _T_2408 = cat(UInt<64>("h5800000300"), UInt<64>("h30000000300")) @[Cat.scala 30:58] + node _T_2409 = cat(_T_2408, _T_2407) @[Cat.scala 30:58] + node _T_2410 = cat(_T_2409, _T_2406) @[Cat.scala 30:58] + node _T_2411 = cat(UInt<64>("h15300000094"), UInt<64>("h7100000071")) @[Cat.scala 30:58] + node _T_2412 = cat(UInt<64>("h15800000093"), UInt<64>("h15300000094")) @[Cat.scala 30:58] + node _T_2413 = cat(_T_2412, _T_2411) @[Cat.scala 30:58] + node _T_2414 = cat(UInt<64>("h34d00000346"), UInt<64>("h22a0000022a")) @[Cat.scala 30:58] + node _T_2415 = cat(UInt<64>("h18c000001b0"), UInt<64>("h27f0000034d")) @[Cat.scala 30:58] + node _T_2416 = cat(_T_2415, _T_2414) @[Cat.scala 30:58] + node _T_2417 = cat(_T_2416, _T_2413) @[Cat.scala 30:58] + node _T_2418 = cat(_T_2417, _T_2410) @[Cat.scala 30:58] + node _T_2419 = cat(_T_2418, _T_2403) @[Cat.scala 30:58] + node _T_2420 = cat(_T_2419, _T_2388) @[Cat.scala 30:58] + node _T_2421 = cat(_T_2420, _T_2357) @[Cat.scala 30:58] + node _T_2422 = cat(UInt<64>("h33100000331"), UInt<64>("h18c000000d3")) @[Cat.scala 30:58] + node _T_2423 = cat(UInt<64>("h23200000232"), UInt<64>("h15200000331")) @[Cat.scala 30:58] + node _T_2424 = cat(_T_2423, _T_2422) @[Cat.scala 30:58] + node _T_2425 = cat(UInt<64>("h26700000267"), UInt<64>("h34000000232")) @[Cat.scala 30:58] + node _T_2426 = cat(UInt<64>("h1d6000001ef"), UInt<64>("h189000001ef")) @[Cat.scala 30:58] + node _T_2427 = cat(_T_2426, _T_2425) @[Cat.scala 30:58] + node _T_2428 = cat(_T_2427, _T_2424) @[Cat.scala 30:58] + node _T_2429 = cat(UInt<64>("h1500000015c"), UInt<64>("h1d60000032c")) @[Cat.scala 30:58] + node _T_2430 = cat(UInt<64>("h1a3000001ae"), UInt<64>("h1a300000150")) @[Cat.scala 30:58] + node _T_2431 = cat(_T_2430, _T_2429) @[Cat.scala 30:58] + node _T_2432 = cat(UInt<64>("h21e000000d7"), UInt<64>("hd7000000f9")) @[Cat.scala 30:58] + node _T_2433 = cat(UInt<64>("h27c00000348"), UInt<64>("h34800000220")) @[Cat.scala 30:58] + node _T_2434 = cat(_T_2433, _T_2432) @[Cat.scala 30:58] + node _T_2435 = cat(_T_2434, _T_2431) @[Cat.scala 30:58] + node _T_2436 = cat(_T_2435, _T_2428) @[Cat.scala 30:58] + node _T_2437 = cat(UInt<64>("h2d900000312"), UInt<64>("h2d90000027c")) @[Cat.scala 30:58] + node _T_2438 = cat(UInt<64>("h32600000326"), UInt<64>("h31b0000031b")) @[Cat.scala 30:58] + node _T_2439 = cat(_T_2438, _T_2437) @[Cat.scala 30:58] + node _T_2440 = cat(UInt<64>("h1a2000002f6"), UInt<64>("h2f6000002f6")) @[Cat.scala 30:58] + node _T_2441 = cat(UInt<64>("h29e00000191"), UInt<64>("h1a200000191")) @[Cat.scala 30:58] + node _T_2442 = cat(_T_2441, _T_2440) @[Cat.scala 30:58] + node _T_2443 = cat(_T_2442, _T_2439) @[Cat.scala 30:58] + node _T_2444 = cat(UInt<64>("h23800000238"), UInt<64>("h39800000398")) @[Cat.scala 30:58] + node _T_2445 = cat(UInt<64>("h24800000296"), UInt<64>("h2d9000002d9")) @[Cat.scala 30:58] + node _T_2446 = cat(_T_2445, _T_2444) @[Cat.scala 30:58] + node _T_2447 = cat(UInt<64>("h19e0000019e"), UInt<64>("h18100000248")) @[Cat.scala 30:58] + node _T_2448 = cat(UInt<64>("h1c900000210"), UInt<64>("h21000000210")) @[Cat.scala 30:58] + node _T_2449 = cat(_T_2448, _T_2447) @[Cat.scala 30:58] + node _T_2450 = cat(_T_2449, _T_2446) @[Cat.scala 30:58] + node _T_2451 = cat(_T_2450, _T_2443) @[Cat.scala 30:58] + node _T_2452 = cat(_T_2451, _T_2436) @[Cat.scala 30:58] + node _T_2453 = cat(UInt<64>("h13c0000017a"), UInt<64>("h1c90000022a")) @[Cat.scala 30:58] + node _T_2454 = cat(UInt<64>("h1dd000002fe"), UInt<64>("h1dd0000017a")) @[Cat.scala 30:58] + node _T_2455 = cat(_T_2454, _T_2453) @[Cat.scala 30:58] + node _T_2456 = cat(UInt<64>("h1a00000018f"), UInt<64>("hec000000ec")) @[Cat.scala 30:58] + node _T_2457 = cat(UInt<64>("h325000000e5"), UInt<64>("h1a0000001a0")) @[Cat.scala 30:58] + node _T_2458 = cat(_T_2457, _T_2456) @[Cat.scala 30:58] + node _T_2459 = cat(_T_2458, _T_2455) @[Cat.scala 30:58] + node _T_2460 = cat(UInt<64>("h10e0000010e"), UInt<64>("h1f9000001f9")) @[Cat.scala 30:58] + node _T_2461 = cat(UInt<64>("h31c000002c0"), UInt<64>("h2c0000002c0")) @[Cat.scala 30:58] + node _T_2462 = cat(_T_2461, _T_2460) @[Cat.scala 30:58] + node _T_2463 = cat(UInt<64>("h12f0000012f"), UInt<64>("h2100000031c")) @[Cat.scala 30:58] + node _T_2464 = cat(UInt<64>("h26f0000027b"), UInt<64>("h26f0000012f")) @[Cat.scala 30:58] + node _T_2465 = cat(_T_2464, _T_2463) @[Cat.scala 30:58] + node _T_2466 = cat(_T_2465, _T_2462) @[Cat.scala 30:58] + node _T_2467 = cat(_T_2466, _T_2459) @[Cat.scala 30:58] + node _T_2468 = cat(UInt<64>("h7700000077"), UInt<64>("h21900000230")) @[Cat.scala 30:58] + node _T_2469 = cat(UInt<64>("h21400000214"), UInt<64>("h12600000077")) @[Cat.scala 30:58] + node _T_2470 = cat(_T_2469, _T_2468) @[Cat.scala 30:58] + node _T_2471 = cat(UInt<64>("h18e0000018e"), UInt<64>("h18e00000214")) @[Cat.scala 30:58] + node _T_2472 = cat(UInt<64>("h28600000286"), UInt<64>("h28600000248")) @[Cat.scala 30:58] + node _T_2473 = cat(_T_2472, _T_2471) @[Cat.scala 30:58] + node _T_2474 = cat(_T_2473, _T_2470) @[Cat.scala 30:58] + node _T_2475 = cat(UInt<64>("h381000002ff"), UInt<64>("h26b0000026b")) @[Cat.scala 30:58] + node _T_2476 = cat(UInt<64>("h39000001de"), UInt<64>("h24d000002ff")) @[Cat.scala 30:58] + node _T_2477 = cat(_T_2476, _T_2475) @[Cat.scala 30:58] + node _T_2478 = cat(UInt<64>("h31000000310"), UInt<64>("h12000000039")) @[Cat.scala 30:58] + node _T_2479 = cat(UInt<64>("h2e600000345"), UInt<64>("h34d0000034d")) @[Cat.scala 30:58] + node _T_2480 = cat(_T_2479, _T_2478) @[Cat.scala 30:58] + node _T_2481 = cat(_T_2480, _T_2477) @[Cat.scala 30:58] + node _T_2482 = cat(_T_2481, _T_2474) @[Cat.scala 30:58] + node _T_2483 = cat(_T_2482, _T_2467) @[Cat.scala 30:58] + node _T_2484 = cat(_T_2483, _T_2452) @[Cat.scala 30:58] + node _T_2485 = cat(UInt<64>("h1bb00000133"), UInt<64>("h13300000133")) @[Cat.scala 30:58] + node _T_2486 = cat(UInt<64>("h1b000000338"), UInt<64>("h1bb000001bb")) @[Cat.scala 30:58] + node _T_2487 = cat(_T_2486, _T_2485) @[Cat.scala 30:58] + node _T_2488 = cat(UInt<64>("hab000002ed"), UInt<64>("h2ed000002ed")) @[Cat.scala 30:58] + node _T_2489 = cat(UInt<64>("h1cd0000026d"), UInt<64>("h1cd000000ab")) @[Cat.scala 30:58] + node _T_2490 = cat(_T_2489, _T_2488) @[Cat.scala 30:58] + node _T_2491 = cat(_T_2490, _T_2487) @[Cat.scala 30:58] + node _T_2492 = cat(UInt<64>("h17800000110"), UInt<64>("h11000000143")) @[Cat.scala 30:58] + node _T_2493 = cat(UInt<64>("h2b600000154"), UInt<64>("h15400000178")) @[Cat.scala 30:58] + node _T_2494 = cat(_T_2493, _T_2492) @[Cat.scala 30:58] + node _T_2495 = cat(UInt<64>("ha80000009e"), UInt<64>("h9e000002b6")) @[Cat.scala 30:58] + node _T_2496 = cat(UInt<64>("h1bb000002e8"), UInt<64>("h1bb000000ec")) @[Cat.scala 30:58] + node _T_2497 = cat(_T_2496, _T_2495) @[Cat.scala 30:58] + node _T_2498 = cat(_T_2497, _T_2494) @[Cat.scala 30:58] + node _T_2499 = cat(_T_2498, _T_2491) @[Cat.scala 30:58] + node _T_2500 = cat(UInt<64>("h27700000109"), UInt<64>("h10900000109")) @[Cat.scala 30:58] + node _T_2501 = cat(UInt<64>("h30d000002db"), UInt<64>("h2db000002db")) @[Cat.scala 30:58] + node _T_2502 = cat(_T_2501, _T_2500) @[Cat.scala 30:58] + node _T_2503 = cat(UInt<64>("h17200000172"), UInt<64>("h1a90000030d")) @[Cat.scala 30:58] + node _T_2504 = cat(UInt<64>("h12400000124"), UInt<64>("h14000000172")) @[Cat.scala 30:58] + node _T_2505 = cat(_T_2504, _T_2503) @[Cat.scala 30:58] + node _T_2506 = cat(_T_2505, _T_2502) @[Cat.scala 30:58] + node _T_2507 = cat(UInt<64>("h2fb0000021e"), UInt<64>("h21e0000021e")) @[Cat.scala 30:58] + node _T_2508 = cat(UInt<64>("h393000002f0"), UInt<64>("h2f0000002fb")) @[Cat.scala 30:58] + node _T_2509 = cat(_T_2508, _T_2507) @[Cat.scala 30:58] + node _T_2510 = cat(UInt<64>("h2750000000e"), UInt<64>("h27500000393")) @[Cat.scala 30:58] + node _T_2511 = cat(UInt<64>("h200000038a"), UInt<64>("h28900000289")) @[Cat.scala 30:58] + node _T_2512 = cat(_T_2511, _T_2510) @[Cat.scala 30:58] + node _T_2513 = cat(_T_2512, _T_2509) @[Cat.scala 30:58] + node _T_2514 = cat(_T_2513, _T_2506) @[Cat.scala 30:58] + node _T_2515 = cat(_T_2514, _T_2499) @[Cat.scala 30:58] + node _T_2516 = cat(UInt<64>("h230000002e8"), UInt<64>("h2e800000329")) @[Cat.scala 30:58] + node _T_2517 = cat(UInt<64>("h39300000393"), UInt<64>("h36900000230")) @[Cat.scala 30:58] + node _T_2518 = cat(_T_2517, _T_2516) @[Cat.scala 30:58] + node _T_2519 = cat(UInt<64>("h22a000001fd"), UInt<64>("h22a00000317")) @[Cat.scala 30:58] + node _T_2520 = cat(UInt<64>("h2580000022e"), UInt<64>("h22e0000022e")) @[Cat.scala 30:58] + node _T_2521 = cat(_T_2520, _T_2519) @[Cat.scala 30:58] + node _T_2522 = cat(_T_2521, _T_2518) @[Cat.scala 30:58] + node _T_2523 = cat(UInt<64>("h24300000195"), UInt<64>("h19500000258")) @[Cat.scala 30:58] + node _T_2524 = cat(UInt<64>("h21c00000125"), UInt<64>("h21c00000243")) @[Cat.scala 30:58] + node _T_2525 = cat(_T_2524, _T_2523) @[Cat.scala 30:58] + node _T_2526 = cat(UInt<64>("h8100000081"), UInt<64>("h35100000351")) @[Cat.scala 30:58] + node _T_2527 = cat(UInt<64>("h26e00000209"), UInt<64>("h209000001c4")) @[Cat.scala 30:58] + node _T_2528 = cat(_T_2527, _T_2526) @[Cat.scala 30:58] + node _T_2529 = cat(_T_2528, _T_2525) @[Cat.scala 30:58] + node _T_2530 = cat(_T_2529, _T_2522) @[Cat.scala 30:58] + node _T_2531 = cat(UInt<64>("h2a6000000e0"), UInt<64>("he00000026e")) @[Cat.scala 30:58] + node _T_2532 = cat(UInt<64>("h212000000f0"), UInt<64>("h212000002a6")) @[Cat.scala 30:58] + node _T_2533 = cat(_T_2532, _T_2531) @[Cat.scala 30:58] + node _T_2534 = cat(UInt<64>("h28b0000028b"), UInt<64>("h28b0000014f")) @[Cat.scala 30:58] + node _T_2535 = cat(UInt<64>("h6000000060"), UInt<64>("he200000281")) @[Cat.scala 30:58] + node _T_2536 = cat(_T_2535, _T_2534) @[Cat.scala 30:58] + node _T_2537 = cat(_T_2536, _T_2533) @[Cat.scala 30:58] + node _T_2538 = cat(UInt<64>("h23900000239"), UInt<64>("h14000000106")) @[Cat.scala 30:58] + node _T_2539 = cat(UInt<64>("h26200000286"), UInt<64>("hee00000286")) @[Cat.scala 30:58] + node _T_2540 = cat(_T_2539, _T_2538) @[Cat.scala 30:58] + node _T_2541 = cat(UInt<64>("hcb000000cb"), UInt<64>("h262000002f2")) @[Cat.scala 30:58] + node _T_2542 = cat(UInt<64>("h31c000000b4"), UInt<64>("hee000000cb")) @[Cat.scala 30:58] + node _T_2543 = cat(_T_2542, _T_2541) @[Cat.scala 30:58] + node _T_2544 = cat(_T_2543, _T_2540) @[Cat.scala 30:58] + node _T_2545 = cat(_T_2544, _T_2537) @[Cat.scala 30:58] + node _T_2546 = cat(_T_2545, _T_2530) @[Cat.scala 30:58] + node _T_2547 = cat(_T_2546, _T_2515) @[Cat.scala 30:58] + node _T_2548 = cat(_T_2547, _T_2484) @[Cat.scala 30:58] + node _T_2549 = cat(_T_2548, _T_2421) @[Cat.scala 30:58] + node _T_2550 = cat(UInt<64>("ha50000012b"), UInt<64>("h23d0000012b")) @[Cat.scala 30:58] + node _T_2551 = cat(UInt<64>("h315000002f9"), UInt<64>("h8c000000a5")) @[Cat.scala 30:58] + node _T_2552 = cat(_T_2551, _T_2550) @[Cat.scala 30:58] + node _T_2553 = cat(UInt<64>("h22f00000286"), UInt<64>("h31500000315")) @[Cat.scala 30:58] + node _T_2554 = cat(UInt<64>("h2c00000026b"), UInt<64>("h26b0000022f")) @[Cat.scala 30:58] + node _T_2555 = cat(_T_2554, _T_2553) @[Cat.scala 30:58] + node _T_2556 = cat(_T_2555, _T_2552) @[Cat.scala 30:58] + node _T_2557 = cat(UInt<64>("h1e0000001e0"), UInt<64>("h1e0000001a6")) @[Cat.scala 30:58] + node _T_2558 = cat(UInt<64>("h174000001ec"), UInt<64>("h1740000021e")) @[Cat.scala 30:58] + node _T_2559 = cat(_T_2558, _T_2557) @[Cat.scala 30:58] + node _T_2560 = cat(UInt<64>("h222000002e9"), UInt<64>("h222000001ec")) @[Cat.scala 30:58] + node _T_2561 = cat(UInt<64>("h174000000cf"), UInt<64>("hcf00000198")) @[Cat.scala 30:58] + node _T_2562 = cat(_T_2561, _T_2560) @[Cat.scala 30:58] + node _T_2563 = cat(_T_2562, _T_2559) @[Cat.scala 30:58] + node _T_2564 = cat(_T_2563, _T_2556) @[Cat.scala 30:58] + node _T_2565 = cat(UInt<64>("h1d000000298"), UInt<64>("h28500000285")) @[Cat.scala 30:58] + node _T_2566 = cat(UInt<64>("h12500000125"), UInt<64>("h5100000051")) @[Cat.scala 30:58] + node _T_2567 = cat(_T_2566, _T_2565) @[Cat.scala 30:58] + node _T_2568 = cat(UInt<64>("h37000000370"), UInt<64>("h1de000001de")) @[Cat.scala 30:58] + node _T_2569 = cat(UInt<64>("h2df000000cb"), UInt<64>("he0000000e0")) @[Cat.scala 30:58] + node _T_2570 = cat(_T_2569, _T_2568) @[Cat.scala 30:58] + node _T_2571 = cat(_T_2570, _T_2567) @[Cat.scala 30:58] + node _T_2572 = cat(UInt<64>("h16d0000016d"), UInt<64>("h2df000000d6")) @[Cat.scala 30:58] + node _T_2573 = cat(UInt<64>("h2140000030d"), UInt<64>("ha70000016d")) @[Cat.scala 30:58] + node _T_2574 = cat(_T_2573, _T_2572) @[Cat.scala 30:58] + node _T_2575 = cat(UInt<64>("h141000002a8"), UInt<64>("h214000002a8")) @[Cat.scala 30:58] + node _T_2576 = cat(UInt<64>("h1e5000002b0"), UInt<64>("h1e5000002b0")) @[Cat.scala 30:58] + node _T_2577 = cat(_T_2576, _T_2575) @[Cat.scala 30:58] + node _T_2578 = cat(_T_2577, _T_2574) @[Cat.scala 30:58] + node _T_2579 = cat(_T_2578, _T_2571) @[Cat.scala 30:58] + node _T_2580 = cat(_T_2579, _T_2564) @[Cat.scala 30:58] + node _T_2581 = cat(UInt<64>("h32000000b1"), UInt<64>("hb100000182")) @[Cat.scala 30:58] + node _T_2582 = cat(UInt<64>("h28e000001da"), UInt<64>("h6500000032")) @[Cat.scala 30:58] + node _T_2583 = cat(_T_2582, _T_2581) @[Cat.scala 30:58] + node _T_2584 = cat(UInt<64>("h2a7000002a7"), UInt<64>("h28e000001da")) @[Cat.scala 30:58] + node _T_2585 = cat(UInt<64>("h3360000014a"), UInt<64>("h14a00000271")) @[Cat.scala 30:58] + node _T_2586 = cat(_T_2585, _T_2584) @[Cat.scala 30:58] + node _T_2587 = cat(_T_2586, _T_2583) @[Cat.scala 30:58] + node _T_2588 = cat(UInt<64>("h281000001dd"), UInt<64>("h31b00000336")) @[Cat.scala 30:58] + node _T_2589 = cat(UInt<64>("hfc000002c9"), UInt<64>("h28100000281")) @[Cat.scala 30:58] + node _T_2590 = cat(_T_2589, _T_2588) @[Cat.scala 30:58] + node _T_2591 = cat(UInt<64>("h21100000211"), UInt<64>("hf5000002c9")) @[Cat.scala 30:58] + node _T_2592 = cat(UInt<64>("h14d0000014d"), UInt<64>("h36600000366")) @[Cat.scala 30:58] + node _T_2593 = cat(_T_2592, _T_2591) @[Cat.scala 30:58] + node _T_2594 = cat(_T_2593, _T_2590) @[Cat.scala 30:58] + node _T_2595 = cat(_T_2594, _T_2587) @[Cat.scala 30:58] + node _T_2596 = cat(UInt<64>("h38b0000038b"), UInt<64>("h25900000221")) @[Cat.scala 30:58] + node _T_2597 = cat(UInt<64>("he90000018d"), UInt<64>("h30700000355")) @[Cat.scala 30:58] + node _T_2598 = cat(_T_2597, _T_2596) @[Cat.scala 30:58] + node _T_2599 = cat(UInt<64>("h1c6000002f3"), UInt<64>("h2f3000000e9")) @[Cat.scala 30:58] + node _T_2600 = cat(UInt<64>("h16d0000016d"), UInt<64>("h1a8000000ef")) @[Cat.scala 30:58] + node _T_2601 = cat(_T_2600, _T_2599) @[Cat.scala 30:58] + node _T_2602 = cat(_T_2601, _T_2598) @[Cat.scala 30:58] + node _T_2603 = cat(UInt<64>("h38400000062"), UInt<64>("hd2000000d2")) @[Cat.scala 30:58] + node _T_2604 = cat(UInt<64>("h28f000001b8"), UInt<64>("h38400000062")) @[Cat.scala 30:58] + node _T_2605 = cat(_T_2604, _T_2603) @[Cat.scala 30:58] + node _T_2606 = cat(UInt<64>("h21100000211"), UInt<64>("h28f0000028f")) @[Cat.scala 30:58] + node _T_2607 = cat(UInt<64>("h1d000000150"), UInt<64>("h15000000150")) @[Cat.scala 30:58] + node _T_2608 = cat(_T_2607, _T_2606) @[Cat.scala 30:58] + node _T_2609 = cat(_T_2608, _T_2605) @[Cat.scala 30:58] + node _T_2610 = cat(_T_2609, _T_2602) @[Cat.scala 30:58] + node _T_2611 = cat(_T_2610, _T_2595) @[Cat.scala 30:58] + node _T_2612 = cat(_T_2611, _T_2580) @[Cat.scala 30:58] + node _T_2613 = cat(UInt<64>("h2ad000002d6"), UInt<64>("h2ad000002b9")) @[Cat.scala 30:58] + node _T_2614 = cat(UInt<64>("h11a00000144"), UInt<64>("h14400000144")) @[Cat.scala 30:58] + node _T_2615 = cat(_T_2614, _T_2613) @[Cat.scala 30:58] + node _T_2616 = cat(UInt<64>("h1ee00000218"), UInt<64>("h1ee0000011a")) @[Cat.scala 30:58] + node _T_2617 = cat(UInt<64>("h1e800000252"), UInt<64>("h18500000252")) @[Cat.scala 30:58] + node _T_2618 = cat(_T_2617, _T_2616) @[Cat.scala 30:58] + node _T_2619 = cat(_T_2618, _T_2615) @[Cat.scala 30:58] + node _T_2620 = cat(UInt<64>("h1220000004b"), UInt<64>("h4b000001e8")) @[Cat.scala 30:58] + node _T_2621 = cat(UInt<64>("h27f0000027f"), UInt<64>("h1f000000199")) @[Cat.scala 30:58] + node _T_2622 = cat(_T_2621, _T_2620) @[Cat.scala 30:58] + node _T_2623 = cat(UInt<64>("h22400000224"), UInt<64>("h1c1000001c1")) @[Cat.scala 30:58] + node _T_2624 = cat(UInt<64>("h12f00000087"), UInt<64>("h870000021b")) @[Cat.scala 30:58] + node _T_2625 = cat(_T_2624, _T_2623) @[Cat.scala 30:58] + node _T_2626 = cat(_T_2625, _T_2622) @[Cat.scala 30:58] + node _T_2627 = cat(_T_2626, _T_2619) @[Cat.scala 30:58] + node _T_2628 = cat(UInt<64>("h2d3000002d3"), UInt<64>("h2d300000284")) @[Cat.scala 30:58] + node _T_2629 = cat(UInt<64>("ha2000000a2"), UInt<64>("h2de000002de")) @[Cat.scala 30:58] + node _T_2630 = cat(_T_2629, _T_2628) @[Cat.scala 30:58] + node _T_2631 = cat(UInt<64>("hf80000019f"), UInt<64>("h19f0000019f")) @[Cat.scala 30:58] + node _T_2632 = cat(UInt<64>("h740000016a"), UInt<64>("h16a000001eb")) @[Cat.scala 30:58] + node _T_2633 = cat(_T_2632, _T_2631) @[Cat.scala 30:58] + node _T_2634 = cat(_T_2633, _T_2630) @[Cat.scala 30:58] + node _T_2635 = cat(UInt<64>("h35b0000035b"), UInt<64>("h26900000074")) @[Cat.scala 30:58] + node _T_2636 = cat(UInt<64>("h2d40000011a"), UInt<64>("heb000000eb")) @[Cat.scala 30:58] + node _T_2637 = cat(_T_2636, _T_2635) @[Cat.scala 30:58] + node _T_2638 = cat(UInt<64>("h1d60000023b"), UInt<64>("h23b0000023b")) @[Cat.scala 30:58] + node _T_2639 = cat(UInt<64>("h10700000107"), UInt<64>("h1d600000230")) @[Cat.scala 30:58] + node _T_2640 = cat(_T_2639, _T_2638) @[Cat.scala 30:58] + node _T_2641 = cat(_T_2640, _T_2637) @[Cat.scala 30:58] + node _T_2642 = cat(_T_2641, _T_2634) @[Cat.scala 30:58] + node _T_2643 = cat(_T_2642, _T_2627) @[Cat.scala 30:58] + node _T_2644 = cat(UInt<64>("h30e0000030e"), UInt<64>("h157000000f2")) @[Cat.scala 30:58] + node _T_2645 = cat(UInt<64>("h153000002d8"), UInt<64>("h2a50000030e")) @[Cat.scala 30:58] + node _T_2646 = cat(_T_2645, _T_2644) @[Cat.scala 30:58] + node _T_2647 = cat(UInt<64>("h1ae0000019a"), UInt<64>("h15800000158")) @[Cat.scala 30:58] + node _T_2648 = cat(UInt<64>("h24e00000265"), UInt<64>("h1d1000001d1")) @[Cat.scala 30:58] + node _T_2649 = cat(_T_2648, _T_2647) @[Cat.scala 30:58] + node _T_2650 = cat(_T_2649, _T_2646) @[Cat.scala 30:58] + node _T_2651 = cat(UInt<64>("h19600000135"), UInt<64>("h1e50000024e")) @[Cat.scala 30:58] + node _T_2652 = cat(UInt<64>("h2ea00000162"), UInt<64>("h1960000014d")) @[Cat.scala 30:58] + node _T_2653 = cat(_T_2652, _T_2651) @[Cat.scala 30:58] + node _T_2654 = cat(UInt<64>("h20d00000136"), UInt<64>("h13600000162")) @[Cat.scala 30:58] + node _T_2655 = cat(UInt<64>("h15000000150"), UInt<64>("h1500000020d")) @[Cat.scala 30:58] + node _T_2656 = cat(_T_2655, _T_2654) @[Cat.scala 30:58] + node _T_2657 = cat(_T_2656, _T_2653) @[Cat.scala 30:58] + node _T_2658 = cat(_T_2657, _T_2650) @[Cat.scala 30:58] + node _T_2659 = cat(UInt<64>("h8600000086"), UInt<64>("h100000001e7")) @[Cat.scala 30:58] + node _T_2660 = cat(UInt<64>("h16f00000189"), UInt<64>("h22200000189")) @[Cat.scala 30:58] + node _T_2661 = cat(_T_2660, _T_2659) @[Cat.scala 30:58] + node _T_2662 = cat(UInt<64>("h6a0000013a"), UInt<64>("h16f0000013a")) @[Cat.scala 30:58] + node _T_2663 = cat(UInt<64>("h27500000275"), UInt<64>("h1590000006a")) @[Cat.scala 30:58] + node _T_2664 = cat(_T_2663, _T_2662) @[Cat.scala 30:58] + node _T_2665 = cat(_T_2664, _T_2661) @[Cat.scala 30:58] + node _T_2666 = cat(UInt<64>("h1ad00000258"), UInt<64>("h18c00000258")) @[Cat.scala 30:58] + node _T_2667 = cat(UInt<64>("h8200000180"), UInt<64>("h1ad000001ad")) @[Cat.scala 30:58] + node _T_2668 = cat(_T_2667, _T_2666) @[Cat.scala 30:58] + node _T_2669 = cat(UInt<64>("h16300000163"), UInt<64>("h16300000082")) @[Cat.scala 30:58] + node _T_2670 = cat(UInt<64>("h2a10000029c"), UInt<64>("h2a10000029c")) @[Cat.scala 30:58] + node _T_2671 = cat(_T_2670, _T_2669) @[Cat.scala 30:58] + node _T_2672 = cat(_T_2671, _T_2668) @[Cat.scala 30:58] + node _T_2673 = cat(_T_2672, _T_2665) @[Cat.scala 30:58] + node _T_2674 = cat(_T_2673, _T_2658) @[Cat.scala 30:58] + node _T_2675 = cat(_T_2674, _T_2643) @[Cat.scala 30:58] + node _T_2676 = cat(_T_2675, _T_2612) @[Cat.scala 30:58] + node _T_2677 = cat(UInt<64>("h2cf00000355"), UInt<64>("h35500000355")) @[Cat.scala 30:58] + node _T_2678 = cat(UInt<64>("h6400000064"), UInt<64>("h138000001c1")) @[Cat.scala 30:58] + node _T_2679 = cat(_T_2678, _T_2677) @[Cat.scala 30:58] + node _T_2680 = cat(UInt<64>("h23700000214"), UInt<64>("h21400000214")) @[Cat.scala 30:58] + node _T_2681 = cat(UInt<64>("h2e1000002e1"), UInt<64>("h2e1000002c3")) @[Cat.scala 30:58] + node _T_2682 = cat(_T_2681, _T_2680) @[Cat.scala 30:58] + node _T_2683 = cat(_T_2682, _T_2679) @[Cat.scala 30:58] + node _T_2684 = cat(UInt<64>("h1c4000001cd"), UInt<64>("h34f0000034f")) @[Cat.scala 30:58] + node _T_2685 = cat(UInt<64>("h2ea00000390"), UInt<64>("h390000001cd")) @[Cat.scala 30:58] + node _T_2686 = cat(_T_2685, _T_2684) @[Cat.scala 30:58] + node _T_2687 = cat(UInt<64>("h20a0000010c"), UInt<64>("h2ea0000010c")) @[Cat.scala 30:58] + node _T_2688 = cat(UInt<64>("h730000026a"), UInt<64>("h26a0000020a")) @[Cat.scala 30:58] + node _T_2689 = cat(_T_2688, _T_2687) @[Cat.scala 30:58] + node _T_2690 = cat(_T_2689, _T_2686) @[Cat.scala 30:58] + node _T_2691 = cat(_T_2690, _T_2683) @[Cat.scala 30:58] + node _T_2692 = cat(UInt<64>("h284000002d7"), UInt<64>("h2d700000073")) @[Cat.scala 30:58] + node _T_2693 = cat(UInt<64>("hc8000000a5"), UInt<64>("ha5000000e2")) @[Cat.scala 30:58] + node _T_2694 = cat(_T_2693, _T_2692) @[Cat.scala 30:58] + node _T_2695 = cat(UInt<64>("h33e00000357"), UInt<64>("h33e0000030b")) @[Cat.scala 30:58] + node _T_2696 = cat(UInt<64>("h2c1000000bb"), UInt<64>("hbb000002e6")) @[Cat.scala 30:58] + node _T_2697 = cat(_T_2696, _T_2695) @[Cat.scala 30:58] + node _T_2698 = cat(_T_2697, _T_2694) @[Cat.scala 30:58] + node _T_2699 = cat(UInt<64>("h29f0000029f"), UInt<64>("h2c1000002cd")) @[Cat.scala 30:58] + node _T_2700 = cat(UInt<64>("h376000002cf"), UInt<64>("h311000002cf")) @[Cat.scala 30:58] + node _T_2701 = cat(_T_2700, _T_2699) @[Cat.scala 30:58] + node _T_2702 = cat(UInt<64>("h12500000291"), UInt<64>("h31100000311")) @[Cat.scala 30:58] + node _T_2703 = cat(UInt<64>("hfd000000fd"), UInt<64>("h125000000c4")) @[Cat.scala 30:58] + node _T_2704 = cat(_T_2703, _T_2702) @[Cat.scala 30:58] + node _T_2705 = cat(_T_2704, _T_2701) @[Cat.scala 30:58] + node _T_2706 = cat(_T_2705, _T_2698) @[Cat.scala 30:58] + node _T_2707 = cat(_T_2706, _T_2691) @[Cat.scala 30:58] + node _T_2708 = cat(UInt<64>("h31c000001bf"), UInt<64>("had000000fd")) @[Cat.scala 30:58] + node _T_2709 = cat(UInt<64>("h14500000048"), UInt<64>("h480000031c")) @[Cat.scala 30:58] + node _T_2710 = cat(_T_2709, _T_2708) @[Cat.scala 30:58] + node _T_2711 = cat(UInt<64>("h13500000135"), UInt<64>("h26800000268")) @[Cat.scala 30:58] + node _T_2712 = cat(UInt<64>("h27d000000af"), UInt<64>("h2ad00000135")) @[Cat.scala 30:58] + node _T_2713 = cat(_T_2712, _T_2711) @[Cat.scala 30:58] + node _T_2714 = cat(_T_2713, _T_2710) @[Cat.scala 30:58] + node _T_2715 = cat(UInt<64>("h34600000346"), UInt<64>("h27d0000009f")) @[Cat.scala 30:58] + node _T_2716 = cat(UInt<64>("h2b5000002cb"), UInt<64>("h2cb000002cb")) @[Cat.scala 30:58] + node _T_2717 = cat(_T_2716, _T_2715) @[Cat.scala 30:58] + node _T_2718 = cat(UInt<64>("h174000000e6"), UInt<64>("h17400000226")) @[Cat.scala 30:58] + node _T_2719 = cat(UInt<64>("h18e00000273"), UInt<64>("h27300000259")) @[Cat.scala 30:58] + node _T_2720 = cat(_T_2719, _T_2718) @[Cat.scala 30:58] + node _T_2721 = cat(_T_2720, _T_2717) @[Cat.scala 30:58] + node _T_2722 = cat(_T_2721, _T_2714) @[Cat.scala 30:58] + node _T_2723 = cat(UInt<64>("h6700000229"), UInt<64>("h2290000018e")) @[Cat.scala 30:58] + node _T_2724 = cat(UInt<64>("h3c6000000ae"), UInt<64>("h4800000048")) @[Cat.scala 30:58] + node _T_2725 = cat(_T_2724, _T_2723) @[Cat.scala 30:58] + node _T_2726 = cat(UInt<64>("h145000000b1"), UInt<64>("h145000003c6")) @[Cat.scala 30:58] + node _T_2727 = cat(UInt<64>("h17400000174"), UInt<64>("h22e0000022e")) @[Cat.scala 30:58] + node _T_2728 = cat(_T_2727, _T_2726) @[Cat.scala 30:58] + node _T_2729 = cat(_T_2728, _T_2725) @[Cat.scala 30:58] + node _T_2730 = cat(UInt<64>("h28b00000257"), UInt<64>("h1f900000189")) @[Cat.scala 30:58] + node _T_2731 = cat(UInt<64>("h1790000023d"), UInt<64>("h28b0000028b")) @[Cat.scala 30:58] + node _T_2732 = cat(_T_2731, _T_2730) @[Cat.scala 30:58] + node _T_2733 = cat(UInt<64>("h1900000024f"), UInt<64>("h15d00000179")) @[Cat.scala 30:58] + node _T_2734 = cat(UInt<64>("h34c00000229"), UInt<64>("h22900000229")) @[Cat.scala 30:58] + node _T_2735 = cat(_T_2734, _T_2733) @[Cat.scala 30:58] + node _T_2736 = cat(_T_2735, _T_2732) @[Cat.scala 30:58] + node _T_2737 = cat(_T_2736, _T_2729) @[Cat.scala 30:58] + node _T_2738 = cat(_T_2737, _T_2722) @[Cat.scala 30:58] + node _T_2739 = cat(_T_2738, _T_2707) @[Cat.scala 30:58] + node _T_2740 = cat(UInt<64>("h37500000251"), UInt<64>("h34c000001b8")) @[Cat.scala 30:58] + node _T_2741 = cat(UInt<64>("h38c0000038c"), UInt<64>("h3a500000251")) @[Cat.scala 30:58] + node _T_2742 = cat(_T_2741, _T_2740) @[Cat.scala 30:58] + node _T_2743 = cat(UInt<64>("h17900000220"), UInt<64>("h22000000220")) @[Cat.scala 30:58] + node _T_2744 = cat(UInt<64>("h30d000001c8"), UInt<64>("h14c00000179")) @[Cat.scala 30:58] + node _T_2745 = cat(_T_2744, _T_2743) @[Cat.scala 30:58] + node _T_2746 = cat(_T_2745, _T_2742) @[Cat.scala 30:58] + node _T_2747 = cat(UInt<64>("h2cc000001ef"), UInt<64>("h2cc0000030d")) @[Cat.scala 30:58] + node _T_2748 = cat(UInt<64>("h1bc00000326"), UInt<64>("h2eb000002eb")) @[Cat.scala 30:58] + node _T_2749 = cat(_T_2748, _T_2747) @[Cat.scala 30:58] + node _T_2750 = cat(UInt<64>("h18a00000224"), UInt<64>("h18a000002bc")) @[Cat.scala 30:58] + node _T_2751 = cat(UInt<64>("h1c200000154"), UInt<64>("h15400000154")) @[Cat.scala 30:58] + node _T_2752 = cat(_T_2751, _T_2750) @[Cat.scala 30:58] + node _T_2753 = cat(_T_2752, _T_2749) @[Cat.scala 30:58] + node _T_2754 = cat(_T_2753, _T_2746) @[Cat.scala 30:58] + node _T_2755 = cat(UInt<64>("h28c0000028c"), UInt<64>("h28c000001c2")) @[Cat.scala 30:58] + node _T_2756 = cat(UInt<64>("h21600000222"), UInt<64>("h22200000276")) @[Cat.scala 30:58] + node _T_2757 = cat(_T_2756, _T_2755) @[Cat.scala 30:58] + node _T_2758 = cat(UInt<64>("h1e10000022f"), UInt<64>("h22f00000265")) @[Cat.scala 30:58] + node _T_2759 = cat(UInt<64>("h1fb000001fb"), UInt<64>("h1e100000139")) @[Cat.scala 30:58] + node _T_2760 = cat(_T_2759, _T_2758) @[Cat.scala 30:58] + node _T_2761 = cat(_T_2760, _T_2757) @[Cat.scala 30:58] + node _T_2762 = cat(UInt<64>("h1570000025f"), UInt<64>("h1b200000388")) @[Cat.scala 30:58] + node _T_2763 = cat(UInt<64>("h31000000310"), UInt<64>("h3100000025f")) @[Cat.scala 30:58] + node _T_2764 = cat(_T_2763, _T_2762) @[Cat.scala 30:58] + node _T_2765 = cat(UInt<64>("h1a5000001fb"), UInt<64>("h36100000361")) @[Cat.scala 30:58] + node _T_2766 = cat(UInt<64>("h21b00000367"), UInt<64>("h367000001fb")) @[Cat.scala 30:58] + node _T_2767 = cat(_T_2766, _T_2765) @[Cat.scala 30:58] + node _T_2768 = cat(_T_2767, _T_2764) @[Cat.scala 30:58] + node _T_2769 = cat(_T_2768, _T_2761) @[Cat.scala 30:58] + node _T_2770 = cat(_T_2769, _T_2754) @[Cat.scala 30:58] + node _T_2771 = cat(UInt<64>("h93000000a2"), UInt<64>("h153000001af")) @[Cat.scala 30:58] + node _T_2772 = cat(UInt<64>("h1e1000000e0"), UInt<64>("he000000093")) @[Cat.scala 30:58] + node _T_2773 = cat(_T_2772, _T_2771) @[Cat.scala 30:58] + node _T_2774 = cat(UInt<64>("h15e00000244"), UInt<64>("h24400000244")) @[Cat.scala 30:58] + node _T_2775 = cat(UInt<64>("h3b4000003b4"), UInt<64>("h15e0000015e")) @[Cat.scala 30:58] + node _T_2776 = cat(_T_2775, _T_2774) @[Cat.scala 30:58] + node _T_2777 = cat(_T_2776, _T_2773) @[Cat.scala 30:58] + node _T_2778 = cat(UInt<64>("he8000000e8"), UInt<64>("he80000011f")) @[Cat.scala 30:58] + node _T_2779 = cat(UInt<64>("h25a0000025a"), UInt<64>("h18c0000018c")) @[Cat.scala 30:58] + node _T_2780 = cat(_T_2779, _T_2778) @[Cat.scala 30:58] + node _T_2781 = cat(UInt<64>("h36800000301"), UInt<64>("h21b0000021b")) @[Cat.scala 30:58] + node _T_2782 = cat(UInt<64>("h1e5000001e5"), UInt<64>("h23e00000301")) @[Cat.scala 30:58] + node _T_2783 = cat(_T_2782, _T_2781) @[Cat.scala 30:58] + node _T_2784 = cat(_T_2783, _T_2780) @[Cat.scala 30:58] + node _T_2785 = cat(_T_2784, _T_2777) @[Cat.scala 30:58] + node _T_2786 = cat(UInt<64>("h2eb000002d1"), UInt<64>("h28c000001e5")) @[Cat.scala 30:58] + node _T_2787 = cat(UInt<64>("h16a000001c3"), UInt<64>("h1c3000002d1")) @[Cat.scala 30:58] + node _T_2788 = cat(_T_2787, _T_2786) @[Cat.scala 30:58] + node _T_2789 = cat(UInt<64>("hce000002e8"), UInt<64>("h2e8000002e8")) @[Cat.scala 30:58] + node _T_2790 = cat(UInt<64>("h1f90000023c"), UInt<64>("h23c000000ce")) @[Cat.scala 30:58] + node _T_2791 = cat(_T_2790, _T_2789) @[Cat.scala 30:58] + node _T_2792 = cat(_T_2791, _T_2788) @[Cat.scala 30:58] + node _T_2793 = cat(UInt<64>("h3c1000002a8"), UInt<64>("h1f900000115")) @[Cat.scala 30:58] + node _T_2794 = cat(UInt<64>("h22b0000022b"), UInt<64>("h2f5000002f5")) @[Cat.scala 30:58] + node _T_2795 = cat(_T_2794, _T_2793) @[Cat.scala 30:58] + node _T_2796 = cat(UInt<64>("h3510000034f"), UInt<64>("h34f00000273")) @[Cat.scala 30:58] + node _T_2797 = cat(UInt<64>("h1f9000001f9"), UInt<64>("h38e00000205")) @[Cat.scala 30:58] + node _T_2798 = cat(_T_2797, _T_2796) @[Cat.scala 30:58] + node _T_2799 = cat(_T_2798, _T_2795) @[Cat.scala 30:58] + node _T_2800 = cat(_T_2799, _T_2792) @[Cat.scala 30:58] + node _T_2801 = cat(_T_2800, _T_2785) @[Cat.scala 30:58] + node _T_2802 = cat(_T_2801, _T_2770) @[Cat.scala 30:58] + node _T_2803 = cat(_T_2802, _T_2739) @[Cat.scala 30:58] + node _T_2804 = cat(_T_2803, _T_2676) @[Cat.scala 30:58] + node _T_2805 = cat(UInt<64>("hf600000302"), UInt<64>("h302000001f9")) @[Cat.scala 30:58] + node _T_2806 = cat(UInt<64>("h18c0000018a"), UInt<64>("hf3000000f3")) @[Cat.scala 30:58] + node _T_2807 = cat(_T_2806, _T_2805) @[Cat.scala 30:58] + node _T_2808 = cat(UInt<64>("h1e2000001ae"), UInt<64>("h1ae0000018c")) @[Cat.scala 30:58] + node _T_2809 = cat(UInt<64>("h22d0000020c"), UInt<64>("h26b000000f4")) @[Cat.scala 30:58] + node _T_2810 = cat(_T_2809, _T_2808) @[Cat.scala 30:58] + node _T_2811 = cat(_T_2810, _T_2807) @[Cat.scala 30:58] + node _T_2812 = cat(UInt<64>("hac00000148"), UInt<64>("h18f0000020c")) @[Cat.scala 30:58] + node _T_2813 = cat(UInt<64>("h26c0000026c"), UInt<64>("h130000000ac")) @[Cat.scala 30:58] + node _T_2814 = cat(_T_2813, _T_2812) @[Cat.scala 30:58] + node _T_2815 = cat(UInt<64>("h21700000252"), UInt<64>("h25200000252")) @[Cat.scala 30:58] + node _T_2816 = cat(UInt<64>("h20100000201"), UInt<64>("h20100000217")) @[Cat.scala 30:58] + node _T_2817 = cat(_T_2816, _T_2815) @[Cat.scala 30:58] + node _T_2818 = cat(_T_2817, _T_2814) @[Cat.scala 30:58] + node _T_2819 = cat(_T_2818, _T_2811) @[Cat.scala 30:58] + node _T_2820 = cat(UInt<64>("h2fc000002ee"), UInt<64>("h2ee000002ee")) @[Cat.scala 30:58] + node _T_2821 = cat(UInt<64>("h16e0000016e"), UInt<64>("h1c6000002fc")) @[Cat.scala 30:58] + node _T_2822 = cat(_T_2821, _T_2820) @[Cat.scala 30:58] + node _T_2823 = cat(UInt<64>("h312000000a7"), UInt<64>("h1fa0000005d")) @[Cat.scala 30:58] + node _T_2824 = cat(UInt<64>("h27e0000017e"), UInt<64>("h17e000000a7")) @[Cat.scala 30:58] + node _T_2825 = cat(_T_2824, _T_2823) @[Cat.scala 30:58] + node _T_2826 = cat(_T_2825, _T_2822) @[Cat.scala 30:58] + node _T_2827 = cat(UInt<64>("h144000001c4"), UInt<64>("h1ee0000027e")) @[Cat.scala 30:58] + node _T_2828 = cat(UInt<64>("h3b0000004e"), UInt<64>("h4e0000004e")) @[Cat.scala 30:58] + node _T_2829 = cat(_T_2828, _T_2827) @[Cat.scala 30:58] + node _T_2830 = cat(UInt<64>("h3a100000070"), UInt<64>("h700000003b")) @[Cat.scala 30:58] + node _T_2831 = cat(UInt<64>("h39c000002da"), UInt<64>("h39c00000156")) @[Cat.scala 30:58] + node _T_2832 = cat(_T_2831, _T_2830) @[Cat.scala 30:58] + node _T_2833 = cat(_T_2832, _T_2829) @[Cat.scala 30:58] + node _T_2834 = cat(_T_2833, _T_2826) @[Cat.scala 30:58] + node _T_2835 = cat(_T_2834, _T_2819) @[Cat.scala 30:58] + node _T_2836 = cat(UInt<64>("h11f0000011f"), UInt<64>("h2a8000002da")) @[Cat.scala 30:58] + node _T_2837 = cat(UInt<64>("h356000003c1"), UInt<64>("h3c10000031d")) @[Cat.scala 30:58] + node _T_2838 = cat(_T_2837, _T_2836) @[Cat.scala 30:58] + node _T_2839 = cat(UInt<64>("h37500000375"), UInt<64>("h35600000272")) @[Cat.scala 30:58] + node _T_2840 = cat(UInt<64>("h18500000268"), UInt<64>("h25800000268")) @[Cat.scala 30:58] + node _T_2841 = cat(_T_2840, _T_2839) @[Cat.scala 30:58] + node _T_2842 = cat(_T_2841, _T_2838) @[Cat.scala 30:58] + node _T_2843 = cat(UInt<64>("h2e8000002e8"), UInt<64>("h2e8000002e8")) @[Cat.scala 30:58] + node _T_2844 = cat(UInt<64>("h2b100000267"), UInt<64>("h1de000001de")) @[Cat.scala 30:58] + node _T_2845 = cat(_T_2844, _T_2843) @[Cat.scala 30:58] + node _T_2846 = cat(UInt<64>("h30700000307"), UInt<64>("h2b100000267")) @[Cat.scala 30:58] + node _T_2847 = cat(UInt<64>("hea00000120"), UInt<64>("h1ee0000032a")) @[Cat.scala 30:58] + node _T_2848 = cat(_T_2847, _T_2846) @[Cat.scala 30:58] + node _T_2849 = cat(_T_2848, _T_2845) @[Cat.scala 30:58] + node _T_2850 = cat(_T_2849, _T_2842) @[Cat.scala 30:58] + node _T_2851 = cat(UInt<64>("h1af000001af"), UInt<64>("h1af00000120")) @[Cat.scala 30:58] + node _T_2852 = cat(UInt<64>("h17300000224"), UInt<64>("h24500000245")) @[Cat.scala 30:58] + node _T_2853 = cat(_T_2852, _T_2851) @[Cat.scala 30:58] + node _T_2854 = cat(UInt<64>("h2e500000364"), UInt<64>("h28d00000224")) @[Cat.scala 30:58] + node _T_2855 = cat(UInt<64>("h26f0000026f"), UInt<64>("h2e5000002e5")) @[Cat.scala 30:58] + node _T_2856 = cat(_T_2855, _T_2854) @[Cat.scala 30:58] + node _T_2857 = cat(_T_2856, _T_2853) @[Cat.scala 30:58] + node _T_2858 = cat(UInt<64>("h25b00000272"), UInt<64>("h1ac0000026f")) @[Cat.scala 30:58] + node _T_2859 = cat(UInt<64>("h15800000182"), UInt<64>("h25b00000272")) @[Cat.scala 30:58] + node _T_2860 = cat(_T_2859, _T_2858) @[Cat.scala 30:58] + node _T_2861 = cat(UInt<64>("h1d8000001d8"), UInt<64>("h15800000158")) @[Cat.scala 30:58] + node _T_2862 = cat(UInt<64>("h104000000ef"), UInt<64>("h1040000013d")) @[Cat.scala 30:58] + node _T_2863 = cat(_T_2862, _T_2861) @[Cat.scala 30:58] + node _T_2864 = cat(_T_2863, _T_2860) @[Cat.scala 30:58] + node _T_2865 = cat(_T_2864, _T_2857) @[Cat.scala 30:58] + node _T_2866 = cat(_T_2865, _T_2850) @[Cat.scala 30:58] + node _T_2867 = cat(_T_2866, _T_2835) @[Cat.scala 30:58] + node _T_2868 = cat(UInt<64>("h1ff00000179"), UInt<64>("h179000000ef")) @[Cat.scala 30:58] + node _T_2869 = cat(UInt<64>("h13000000130"), UInt<64>("h130000001ff")) @[Cat.scala 30:58] + node _T_2870 = cat(_T_2869, _T_2868) @[Cat.scala 30:58] + node _T_2871 = cat(UInt<64>("h33900000098"), UInt<64>("h4600000098")) @[Cat.scala 30:58] + node _T_2872 = cat(UInt<64>("h1ea00000186"), UInt<64>("h24000000339")) @[Cat.scala 30:58] + node _T_2873 = cat(_T_2872, _T_2871) @[Cat.scala 30:58] + node _T_2874 = cat(_T_2873, _T_2870) @[Cat.scala 30:58] + node _T_2875 = cat(UInt<64>("h12f00000146"), UInt<64>("h1ea000001ea")) @[Cat.scala 30:58] + node _T_2876 = cat(UInt<64>("h268000001af"), UInt<64>("h1920000012f")) @[Cat.scala 30:58] + node _T_2877 = cat(_T_2876, _T_2875) @[Cat.scala 30:58] + node _T_2878 = cat(UInt<64>("h18400000222"), UInt<64>("h2c400000268")) @[Cat.scala 30:58] + node _T_2879 = cat(UInt<64>("h3c20000030f"), UInt<64>("h184000000ce")) @[Cat.scala 30:58] + node _T_2880 = cat(_T_2879, _T_2878) @[Cat.scala 30:58] + node _T_2881 = cat(_T_2880, _T_2877) @[Cat.scala 30:58] + node _T_2882 = cat(_T_2881, _T_2874) @[Cat.scala 30:58] + node _T_2883 = cat(UInt<64>("h1ba0000032f"), UInt<64>("h37a0000037a")) @[Cat.scala 30:58] + node _T_2884 = cat(UInt<64>("h2990000033f"), UInt<64>("h33f0000032f")) @[Cat.scala 30:58] + node _T_2885 = cat(_T_2884, _T_2883) @[Cat.scala 30:58] + node _T_2886 = cat(UInt<64>("h14100000141"), UInt<64>("h1410000019a")) @[Cat.scala 30:58] + node _T_2887 = cat(UInt<64>("hb3000000f6"), UInt<64>("hf6000000f6")) @[Cat.scala 30:58] + node _T_2888 = cat(_T_2887, _T_2886) @[Cat.scala 30:58] + node _T_2889 = cat(_T_2888, _T_2885) @[Cat.scala 30:58] + node _T_2890 = cat(UInt<64>("h20b000000d3"), UInt<64>("hb0000000d3")) @[Cat.scala 30:58] + node _T_2891 = cat(UInt<64>("h2fc00000176"), UInt<64>("h20b0000020b")) @[Cat.scala 30:58] + node _T_2892 = cat(_T_2891, _T_2890) @[Cat.scala 30:58] + node _T_2893 = cat(UInt<64>("h213000001aa"), UInt<64>("h2c0000001aa")) @[Cat.scala 30:58] + node _T_2894 = cat(UInt<64>("h2f6000002f6"), UInt<64>("h21300000040")) @[Cat.scala 30:58] + node _T_2895 = cat(_T_2894, _T_2893) @[Cat.scala 30:58] + node _T_2896 = cat(_T_2895, _T_2892) @[Cat.scala 30:58] + node _T_2897 = cat(_T_2896, _T_2889) @[Cat.scala 30:58] + node _T_2898 = cat(_T_2897, _T_2882) @[Cat.scala 30:58] + node _T_2899 = cat(UInt<64>("h26300000263"), UInt<64>("h263000002f6")) @[Cat.scala 30:58] + node _T_2900 = cat(UInt<64>("h17700000177"), UInt<64>("h1b5000001f4")) @[Cat.scala 30:58] + node _T_2901 = cat(_T_2900, _T_2899) @[Cat.scala 30:58] + node _T_2902 = cat(UInt<64>("hed00000148"), UInt<64>("h3560000014f")) @[Cat.scala 30:58] + node _T_2903 = cat(UInt<64>("h1d4000001d4"), UInt<64>("h19f000000ed")) @[Cat.scala 30:58] + node _T_2904 = cat(_T_2903, _T_2902) @[Cat.scala 30:58] + node _T_2905 = cat(_T_2904, _T_2901) @[Cat.scala 30:58] + node _T_2906 = cat(UInt<64>("h296000002ac"), UInt<64>("h2ac000001d4")) @[Cat.scala 30:58] + node _T_2907 = cat(UInt<64>("h1c1000001c1"), UInt<64>("h28700000235")) @[Cat.scala 30:58] + node _T_2908 = cat(_T_2907, _T_2906) @[Cat.scala 30:58] + node _T_2909 = cat(UInt<64>("h9e0000009e"), UInt<64>("h119000001c1")) @[Cat.scala 30:58] + node _T_2910 = cat(UInt<64>("h2de00000372"), UInt<64>("h37200000126")) @[Cat.scala 30:58] + node _T_2911 = cat(_T_2910, _T_2909) @[Cat.scala 30:58] + node _T_2912 = cat(_T_2911, _T_2908) @[Cat.scala 30:58] + node _T_2913 = cat(_T_2912, _T_2905) @[Cat.scala 30:58] + node _T_2914 = cat(UInt<64>("h1d700000362"), UInt<64>("h362000002de")) @[Cat.scala 30:58] + node _T_2915 = cat(UInt<64>("h2a100000128"), UInt<64>("h1280000010c")) @[Cat.scala 30:58] + node _T_2916 = cat(_T_2915, _T_2914) @[Cat.scala 30:58] + node _T_2917 = cat(UInt<64>("h1d8000001d8"), UInt<64>("h1d8000002a1")) @[Cat.scala 30:58] + node _T_2918 = cat(UInt<64>("h9b0000016e"), UInt<64>("h16e000001b7")) @[Cat.scala 30:58] + node _T_2919 = cat(_T_2918, _T_2917) @[Cat.scala 30:58] + node _T_2920 = cat(_T_2919, _T_2916) @[Cat.scala 30:58] + node _T_2921 = cat(UInt<64>("h1fa00000101"), UInt<64>("h10100000101")) @[Cat.scala 30:58] + node _T_2922 = cat(UInt<64>("h1bd00000258"), UInt<64>("h29b0000029b")) @[Cat.scala 30:58] + node _T_2923 = cat(_T_2922, _T_2921) @[Cat.scala 30:58] + node _T_2924 = cat(UInt<64>("h1bb000001bb"), UInt<64>("h1bd000001bd")) @[Cat.scala 30:58] + node _T_2925 = cat(UInt<64>("h1850000015d"), UInt<64>("h15d000001bb")) @[Cat.scala 30:58] + node _T_2926 = cat(_T_2925, _T_2924) @[Cat.scala 30:58] + node _T_2927 = cat(_T_2926, _T_2923) @[Cat.scala 30:58] + node _T_2928 = cat(_T_2927, _T_2920) @[Cat.scala 30:58] + node _T_2929 = cat(_T_2928, _T_2913) @[Cat.scala 30:58] + node _T_2930 = cat(_T_2929, _T_2898) @[Cat.scala 30:58] + node _T_2931 = cat(_T_2930, _T_2867) @[Cat.scala 30:58] + node _T_2932 = cat(UInt<64>("h16e00000096"), UInt<64>("h9600000185")) @[Cat.scala 30:58] + node _T_2933 = cat(UInt<64>("h25c000001bc"), UInt<64>("h16e0000016e")) @[Cat.scala 30:58] + node _T_2934 = cat(_T_2933, _T_2932) @[Cat.scala 30:58] + node _T_2935 = cat(UInt<64>("h2d0000003a6"), UInt<64>("h2d000000264")) @[Cat.scala 30:58] + node _T_2936 = cat(UInt<64>("h38f0000033c"), UInt<64>("h33c0000033c")) @[Cat.scala 30:58] + node _T_2937 = cat(_T_2936, _T_2935) @[Cat.scala 30:58] + node _T_2938 = cat(_T_2937, _T_2934) @[Cat.scala 30:58] + node _T_2939 = cat(UInt<64>("h1b30000026d"), UInt<64>("h26d0000026d")) @[Cat.scala 30:58] + node _T_2940 = cat(UInt<64>("h4e0000020a"), UInt<64>("h1b30000020a")) @[Cat.scala 30:58] + node _T_2941 = cat(_T_2940, _T_2939) @[Cat.scala 30:58] + node _T_2942 = cat(UInt<64>("h2f900000139"), UInt<64>("h4e0000004e")) @[Cat.scala 30:58] + node _T_2943 = cat(UInt<64>("h37000000ee"), UInt<64>("h16000000160")) @[Cat.scala 30:58] + node _T_2944 = cat(_T_2943, _T_2942) @[Cat.scala 30:58] + node _T_2945 = cat(_T_2944, _T_2941) @[Cat.scala 30:58] + node _T_2946 = cat(_T_2945, _T_2938) @[Cat.scala 30:58] + node _T_2947 = cat(UInt<64>("he2000002f1"), UInt<64>("he200000037")) @[Cat.scala 30:58] + node _T_2948 = cat(UInt<64>("h36d000001a0"), UInt<64>("hc9000001a0")) @[Cat.scala 30:58] + node _T_2949 = cat(_T_2948, _T_2947) @[Cat.scala 30:58] + node _T_2950 = cat(UInt<64>("h23c0000023c"), UInt<64>("h3600000036d")) @[Cat.scala 30:58] + node _T_2951 = cat(UInt<64>("h8f000000a3"), UInt<64>("ha30000023c")) @[Cat.scala 30:58] + node _T_2952 = cat(_T_2951, _T_2950) @[Cat.scala 30:58] + node _T_2953 = cat(_T_2952, _T_2949) @[Cat.scala 30:58] + node _T_2954 = cat(UInt<64>("h2830000001f"), UInt<64>("h1f0000008f")) @[Cat.scala 30:58] + node _T_2955 = cat(UInt<64>("h30300000303"), UInt<64>("h30300000283")) @[Cat.scala 30:58] + node _T_2956 = cat(_T_2955, _T_2954) @[Cat.scala 30:58] + node _T_2957 = cat(UInt<64>("h31d0000030d"), UInt<64>("h20f0000030d")) @[Cat.scala 30:58] + node _T_2958 = cat(UInt<64>("h125000000f2"), UInt<64>("hf20000031d")) @[Cat.scala 30:58] + node _T_2959 = cat(_T_2958, _T_2957) @[Cat.scala 30:58] + node _T_2960 = cat(_T_2959, _T_2956) @[Cat.scala 30:58] + node _T_2961 = cat(_T_2960, _T_2953) @[Cat.scala 30:58] + node _T_2962 = cat(_T_2961, _T_2946) @[Cat.scala 30:58] + node _T_2963 = cat(UInt<64>("h31b0000032a"), UInt<64>("h32a00000276")) @[Cat.scala 30:58] + node _T_2964 = cat(UInt<64>("h19d000001b3"), UInt<64>("h159000001b3")) @[Cat.scala 30:58] + node _T_2965 = cat(_T_2964, _T_2963) @[Cat.scala 30:58] + node _T_2966 = cat(UInt<64>("h18200000257"), UInt<64>("h19d00000257")) @[Cat.scala 30:58] + node _T_2967 = cat(UInt<64>("h7400000074"), UInt<64>("h18200000283")) @[Cat.scala 30:58] + node _T_2968 = cat(_T_2967, _T_2966) @[Cat.scala 30:58] + node _T_2969 = cat(_T_2968, _T_2965) @[Cat.scala 30:58] + node _T_2970 = cat(UInt<64>("h2a8000002c6"), UInt<64>("h2a800000142")) @[Cat.scala 30:58] + node _T_2971 = cat(UInt<64>("h24500000229"), UInt<64>("h21a0000021a")) @[Cat.scala 30:58] + node _T_2972 = cat(_T_2971, _T_2970) @[Cat.scala 30:58] + node _T_2973 = cat(UInt<64>("h36a0000036a"), UInt<64>("h36a00000245")) @[Cat.scala 30:58] + node _T_2974 = cat(UInt<64>("h28c00000267"), UInt<64>("h1fa00000267")) @[Cat.scala 30:58] + node _T_2975 = cat(_T_2974, _T_2973) @[Cat.scala 30:58] + node _T_2976 = cat(_T_2975, _T_2972) @[Cat.scala 30:58] + node _T_2977 = cat(_T_2976, _T_2969) @[Cat.scala 30:58] + node _T_2978 = cat(UInt<64>("h1ef00000167"), UInt<64>("h21b0000028c")) @[Cat.scala 30:58] + node _T_2979 = cat(UInt<64>("h2fc00000261"), UInt<64>("h1ef00000105")) @[Cat.scala 30:58] + node _T_2980 = cat(_T_2979, _T_2978) @[Cat.scala 30:58] + node _T_2981 = cat(UInt<64>("h1b00000021b"), UInt<64>("h2ae000002ae")) @[Cat.scala 30:58] + node _T_2982 = cat(UInt<64>("h23000000230"), UInt<64>("h1b0000001b0")) @[Cat.scala 30:58] + node _T_2983 = cat(_T_2982, _T_2981) @[Cat.scala 30:58] + node _T_2984 = cat(_T_2983, _T_2980) @[Cat.scala 30:58] + node _T_2985 = cat(UInt<64>("h30a000002e3"), UInt<64>("h2e300000230")) @[Cat.scala 30:58] + node _T_2986 = cat(UInt<64>("h24a0000024a"), UInt<64>("h24a0000013d")) @[Cat.scala 30:58] + node _T_2987 = cat(_T_2986, _T_2985) @[Cat.scala 30:58] + node _T_2988 = cat(UInt<64>("h18200000182"), UInt<64>("h1670000023d")) @[Cat.scala 30:58] + node _T_2989 = cat(UInt<64>("h29700000297"), UInt<64>("h2ea000002ea")) @[Cat.scala 30:58] + node _T_2990 = cat(_T_2989, _T_2988) @[Cat.scala 30:58] + node _T_2991 = cat(_T_2990, _T_2987) @[Cat.scala 30:58] + node _T_2992 = cat(_T_2991, _T_2984) @[Cat.scala 30:58] + node _T_2993 = cat(_T_2992, _T_2977) @[Cat.scala 30:58] + node _T_2994 = cat(_T_2993, _T_2962) @[Cat.scala 30:58] + node _T_2995 = cat(UInt<64>("hd4000000d4"), UInt<64>("h1f800000297")) @[Cat.scala 30:58] + node _T_2996 = cat(UInt<64>("h28300000378"), UInt<64>("h28300000198")) @[Cat.scala 30:58] + node _T_2997 = cat(_T_2996, _T_2995) @[Cat.scala 30:58] + node _T_2998 = cat(UInt<64>("h170000001a4"), UInt<64>("h1a4000001b9")) @[Cat.scala 30:58] + node _T_2999 = cat(UInt<64>("ha9000000a9"), UInt<64>("ha900000204")) @[Cat.scala 30:58] + node _T_3000 = cat(_T_2999, _T_2998) @[Cat.scala 30:58] + node _T_3001 = cat(_T_3000, _T_2997) @[Cat.scala 30:58] + node _T_3002 = cat(UInt<64>("h2a00000020f"), UInt<64>("h167000000db")) @[Cat.scala 30:58] + node _T_3003 = cat(UInt<64>("h1c4000001c4"), UInt<64>("h2a0000002cc")) @[Cat.scala 30:58] + node _T_3004 = cat(_T_3003, _T_3002) @[Cat.scala 30:58] + node _T_3005 = cat(UInt<64>("h12c000002ab"), UInt<64>("h2b4000002b4")) @[Cat.scala 30:58] + node _T_3006 = cat(UInt<64>("h32f000001cb"), UInt<64>("h147000001cb")) @[Cat.scala 30:58] + node _T_3007 = cat(_T_3006, _T_3005) @[Cat.scala 30:58] + node _T_3008 = cat(_T_3007, _T_3004) @[Cat.scala 30:58] + node _T_3009 = cat(_T_3008, _T_3001) @[Cat.scala 30:58] + node _T_3010 = cat(UInt<64>("h33000000264"), UInt<64>("h33d0000032f")) @[Cat.scala 30:58] + node _T_3011 = cat(UInt<64>("hf3000000f7"), UInt<64>("h1f100000264")) @[Cat.scala 30:58] + node _T_3012 = cat(_T_3011, _T_3010) @[Cat.scala 30:58] + node _T_3013 = cat(UInt<64>("h39500000160"), UInt<64>("h160000000f3")) @[Cat.scala 30:58] + node _T_3014 = cat(UInt<64>("h28d000002c9"), UInt<64>("h2e2000002e2")) @[Cat.scala 30:58] + node _T_3015 = cat(_T_3014, _T_3013) @[Cat.scala 30:58] + node _T_3016 = cat(_T_3015, _T_3012) @[Cat.scala 30:58] + node _T_3017 = cat(UInt<64>("h1f700000285"), UInt<64>("h28d0000028d")) @[Cat.scala 30:58] + node _T_3018 = cat(UInt<64>("h21f00000271"), UInt<64>("h21f00000271")) @[Cat.scala 30:58] + node _T_3019 = cat(_T_3018, _T_3017) @[Cat.scala 30:58] + node _T_3020 = cat(UInt<64>("h1d000000130"), UInt<64>("hdc000000dc")) @[Cat.scala 30:58] + node _T_3021 = cat(UInt<64>("h36c0000036c"), UInt<64>("h1d0000001d0")) @[Cat.scala 30:58] + node _T_3022 = cat(_T_3021, _T_3020) @[Cat.scala 30:58] + node _T_3023 = cat(_T_3022, _T_3019) @[Cat.scala 30:58] + node _T_3024 = cat(_T_3023, _T_3016) @[Cat.scala 30:58] + node _T_3025 = cat(_T_3024, _T_3009) @[Cat.scala 30:58] + node _T_3026 = cat(UInt<64>("h1be00000286"), UInt<64>("h28600000286")) @[Cat.scala 30:58] + node _T_3027 = cat(UInt<64>("h21b00000298"), UInt<64>("h1be000001be")) @[Cat.scala 30:58] + node _T_3028 = cat(_T_3027, _T_3026) @[Cat.scala 30:58] + node _T_3029 = cat(UInt<64>("h28f0000030f"), UInt<64>("h28f00000298")) @[Cat.scala 30:58] + node _T_3030 = cat(UInt<64>("h2c3000001d6"), UInt<64>("h18800000188")) @[Cat.scala 30:58] + node _T_3031 = cat(_T_3030, _T_3029) @[Cat.scala 30:58] + node _T_3032 = cat(_T_3031, _T_3028) @[Cat.scala 30:58] + node _T_3033 = cat(UInt<64>("h2620000020b"), UInt<64>("h2df000002c3")) @[Cat.scala 30:58] + node _T_3034 = cat(UInt<64>("h1c3000001c3"), UInt<64>("h26200000262")) @[Cat.scala 30:58] + node _T_3035 = cat(_T_3034, _T_3033) @[Cat.scala 30:58] + node _T_3036 = cat(UInt<64>("hed0000009c"), UInt<64>("hed0000009c")) @[Cat.scala 30:58] + node _T_3037 = cat(UInt<64>("h0"), UInt<64>("h2fe000002fe")) @[Cat.scala 30:58] + node _T_3038 = cat(_T_3037, _T_3036) @[Cat.scala 30:58] + node _T_3039 = cat(_T_3038, _T_3035) @[Cat.scala 30:58] + node _T_3040 = cat(_T_3039, _T_3032) @[Cat.scala 30:58] + node _T_3041 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3042 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3043 = cat(_T_3042, _T_3041) @[Cat.scala 30:58] + node _T_3044 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3045 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3046 = cat(_T_3045, _T_3044) @[Cat.scala 30:58] + node _T_3047 = cat(_T_3046, _T_3043) @[Cat.scala 30:58] + node _T_3048 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3049 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3050 = cat(_T_3049, _T_3048) @[Cat.scala 30:58] + node _T_3051 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3052 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + node _T_3053 = cat(_T_3052, _T_3051) @[Cat.scala 30:58] + node _T_3054 = cat(_T_3053, _T_3050) @[Cat.scala 30:58] + node _T_3055 = cat(_T_3054, _T_3047) @[Cat.scala 30:58] + node _T_3056 = cat(_T_3055, _T_3040) @[Cat.scala 30:58] + node _T_3057 = cat(_T_3056, _T_3025) @[Cat.scala 30:58] + node _T_3058 = cat(_T_3057, _T_2994) @[Cat.scala 30:58] + node _T_3059 = cat(_T_3058, _T_2931) @[Cat.scala 30:58] + node _T_3060 = cat(UInt<64>("h0"), UInt<64>("h0")) @[Cat.scala 30:58] + wire _hex : UInt<16384>[13] @[TileTester.scala 44:21] + _hex[0] <= _T_254 @[TileTester.scala 44:21] + _hex[1] <= _T_509 @[TileTester.scala 44:21] + _hex[2] <= _T_764 @[TileTester.scala 44:21] + _hex[3] <= _T_1019 @[TileTester.scala 44:21] + _hex[4] <= _T_1274 @[TileTester.scala 44:21] + _hex[5] <= _T_1529 @[TileTester.scala 44:21] + _hex[6] <= _T_1784 @[TileTester.scala 44:21] + _hex[7] <= _T_2039 @[TileTester.scala 44:21] + _hex[8] <= _T_2294 @[TileTester.scala 44:21] + _hex[9] <= _T_2549 @[TileTester.scala 44:21] + _hex[10] <= _T_2804 @[TileTester.scala 44:21] + _hex[11] <= _T_3059 @[TileTester.scala 44:21] + _hex[12] <= _T_3060 @[TileTester.scala 44:21] + cmem _mem : UInt<64> [1048576] @[TileTester.scala 45:17] + reg state : UInt<3>, clock with : + reset => (reset, UInt<3>("h0")) @[TileTester.scala 47:22] + reg cycle : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[TileTester.scala 48:22] + node _T_3061 = eq(state, UInt<3>("h0")) @[TileTester.scala 49:36] + reg cntr : UInt<12>, clock with : + reset => (reset, UInt<12>("h0")) @[Counter.scala 29:33] + wire done : UInt<1> + done <= UInt<1>("h0") + when _T_3061 : @[Counter.scala 67:17] + node _T_3062 = eq(cntr, UInt<12>("hcff")) @[Counter.scala 38:24] + node _T_3063 = add(cntr, UInt<1>("h1")) @[Counter.scala 39:22] + node _T_3064 = tail(_T_3063, 1) @[Counter.scala 39:22] + cntr <= _T_3064 @[Counter.scala 39:13] + when _T_3062 : @[Counter.scala 41:21] + cntr <= UInt<1>("h0") @[Counter.scala 41:29] + done <= _T_3062 @[Counter.scala 67:24] + reg id : UInt<5>, clock with : + reset => (UInt<1>("h0"), id) @[TileTester.scala 51:15] + reg addr : UInt<32>, clock with : + reset => (UInt<1>("h0"), addr) @[TileTester.scala 52:17] + reg len : UInt<8>, clock with : + reset => (UInt<1>("h0"), len) @[TileTester.scala 53:16] + reg off : UInt<8>, clock with : + reset => (UInt<1>("h0"), off) @[TileTester.scala 54:16] + node _T_3065 = bits(dut.io.nasti.w.bits.strb, 0, 0) @[TileTester.scala 56:35] + node _T_3066 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3067 = _mem[_T_3066], clock @[TileTester.scala 56:70] + node _T_3068 = mux(_T_3065, dut.io.nasti.w.bits.data, _T_3067) @[TileTester.scala 56:10] + node _T_3069 = bits(_T_3068, 7, 0) @[TileTester.scala 56:77] + node _T_3070 = dshl(_T_3069, UInt<1>("h0")) @[TileTester.scala 56:95] + node _T_3071 = or(UInt<64>("h0"), _T_3070) @[TileTester.scala 55:100] + node _T_3072 = bits(dut.io.nasti.w.bits.strb, 1, 1) @[TileTester.scala 56:35] + node _T_3073 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3074 = _mem[_T_3073], clock @[TileTester.scala 56:70] + node _T_3075 = mux(_T_3072, dut.io.nasti.w.bits.data, _T_3074) @[TileTester.scala 56:10] + node _T_3076 = bits(_T_3075, 15, 8) @[TileTester.scala 56:77] + node _T_3077 = dshl(_T_3076, UInt<4>("h8")) @[TileTester.scala 56:95] + node _T_3078 = or(_T_3071, _T_3077) @[TileTester.scala 55:100] + node _T_3079 = bits(dut.io.nasti.w.bits.strb, 2, 2) @[TileTester.scala 56:35] + node _T_3080 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3081 = _mem[_T_3080], clock @[TileTester.scala 56:70] + node _T_3082 = mux(_T_3079, dut.io.nasti.w.bits.data, _T_3081) @[TileTester.scala 56:10] + node _T_3083 = bits(_T_3082, 23, 16) @[TileTester.scala 56:77] + node _T_3084 = dshl(_T_3083, UInt<5>("h10")) @[TileTester.scala 56:95] + node _T_3085 = or(_T_3078, _T_3084) @[TileTester.scala 55:100] + node _T_3086 = bits(dut.io.nasti.w.bits.strb, 3, 3) @[TileTester.scala 56:35] + node _T_3087 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3088 = _mem[_T_3087], clock @[TileTester.scala 56:70] + node _T_3089 = mux(_T_3086, dut.io.nasti.w.bits.data, _T_3088) @[TileTester.scala 56:10] + node _T_3090 = bits(_T_3089, 31, 24) @[TileTester.scala 56:77] + node _T_3091 = dshl(_T_3090, UInt<5>("h18")) @[TileTester.scala 56:95] + node _T_3092 = or(_T_3085, _T_3091) @[TileTester.scala 55:100] + node _T_3093 = bits(dut.io.nasti.w.bits.strb, 4, 4) @[TileTester.scala 56:35] + node _T_3094 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3095 = _mem[_T_3094], clock @[TileTester.scala 56:70] + node _T_3096 = mux(_T_3093, dut.io.nasti.w.bits.data, _T_3095) @[TileTester.scala 56:10] + node _T_3097 = bits(_T_3096, 39, 32) @[TileTester.scala 56:77] + node _T_3098 = dshl(_T_3097, UInt<6>("h20")) @[TileTester.scala 56:95] + node _T_3099 = or(_T_3092, _T_3098) @[TileTester.scala 55:100] + node _T_3100 = bits(dut.io.nasti.w.bits.strb, 5, 5) @[TileTester.scala 56:35] + node _T_3101 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3102 = _mem[_T_3101], clock @[TileTester.scala 56:70] + node _T_3103 = mux(_T_3100, dut.io.nasti.w.bits.data, _T_3102) @[TileTester.scala 56:10] + node _T_3104 = bits(_T_3103, 47, 40) @[TileTester.scala 56:77] + node _T_3105 = dshl(_T_3104, UInt<6>("h28")) @[TileTester.scala 56:95] + node _T_3106 = or(_T_3099, _T_3105) @[TileTester.scala 55:100] + node _T_3107 = bits(dut.io.nasti.w.bits.strb, 6, 6) @[TileTester.scala 56:35] + node _T_3108 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3109 = _mem[_T_3108], clock @[TileTester.scala 56:70] + node _T_3110 = mux(_T_3107, dut.io.nasti.w.bits.data, _T_3109) @[TileTester.scala 56:10] + node _T_3111 = bits(_T_3110, 55, 48) @[TileTester.scala 56:77] + node _T_3112 = dshl(_T_3111, UInt<6>("h30")) @[TileTester.scala 56:95] + node _T_3113 = or(_T_3106, _T_3112) @[TileTester.scala 55:100] + node _T_3114 = bits(dut.io.nasti.w.bits.strb, 7, 7) @[TileTester.scala 56:35] + node _T_3115 = bits(addr, 19, 0) @[TileTester.scala 56:70] + infer mport _T_3116 = _mem[_T_3115], clock @[TileTester.scala 56:70] + node _T_3117 = mux(_T_3114, dut.io.nasti.w.bits.data, _T_3116) @[TileTester.scala 56:10] + node _T_3118 = bits(_T_3117, 63, 56) @[TileTester.scala 56:77] + node _T_3119 = dshl(_T_3118, UInt<6>("h38")) @[TileTester.scala 56:95] + node write = or(_T_3113, _T_3119) @[TileTester.scala 55:100] + wire bpipe : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, id : UInt<5>, user : UInt<1>}} + bpipe.bits.user <= dut.io.nasti.b.bits.user + bpipe.bits.id <= dut.io.nasti.b.bits.id + bpipe.bits.resp <= dut.io.nasti.b.bits.resp + bpipe.valid <= dut.io.nasti.b.valid + bpipe.ready <= dut.io.nasti.b.ready + wire rpipe : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}} + rpipe.bits.user <= dut.io.nasti.r.bits.user + rpipe.bits.id <= dut.io.nasti.r.bits.id + rpipe.bits.last <= dut.io.nasti.r.bits.last + rpipe.bits.data <= dut.io.nasti.r.bits.data + rpipe.bits.resp <= dut.io.nasti.r.bits.resp + rpipe.valid <= dut.io.nasti.r.valid + rpipe.ready <= dut.io.nasti.r.ready + node _T_3120 = bits(reset, 0, 0) @[TileTester.scala 61:22] + node _T_3121 = eq(state, UInt<3>("h0")) @[TileTester.scala 61:38] + node _T_3122 = or(_T_3120, _T_3121) @[TileTester.scala 61:29] + dut.reset <= _T_3122 @[TileTester.scala 61:13] + node _T_3123 = eq(state, UInt<3>("h1")) @[TileTester.scala 62:34] + dut.io.nasti.aw.ready <= _T_3123 @[TileTester.scala 62:25] + node _T_3124 = eq(state, UInt<3>("h1")) @[TileTester.scala 63:34] + dut.io.nasti.ar.ready <= _T_3124 @[TileTester.scala 63:25] + node _T_3125 = eq(state, UInt<3>("h2")) @[TileTester.scala 64:34] + dut.io.nasti.w.ready <= _T_3125 @[TileTester.scala 64:25] + inst LatencyPipe of LatencyPipe @[TileTester.scala 161:22] + LatencyPipe.clock <= clock + LatencyPipe.reset <= reset + LatencyPipe.io.in.bits <= bpipe.bits @[TileTester.scala 162:16] + LatencyPipe.io.in.valid <= bpipe.valid @[TileTester.scala 162:16] + bpipe.ready <= LatencyPipe.io.in.ready @[TileTester.scala 162:16] + dut.io.nasti.b.bits <= LatencyPipe.io.out.bits @[TileTester.scala 65:18] + dut.io.nasti.b.valid <= LatencyPipe.io.out.valid @[TileTester.scala 65:18] + LatencyPipe.io.out.ready <= dut.io.nasti.b.ready @[TileTester.scala 65:18] + inst LatencyPipe_1 of LatencyPipe_1 @[TileTester.scala 161:22] + LatencyPipe_1.clock <= clock + LatencyPipe_1.reset <= reset + LatencyPipe_1.io.in.bits <= rpipe.bits @[TileTester.scala 162:16] + LatencyPipe_1.io.in.valid <= rpipe.valid @[TileTester.scala 162:16] + rpipe.ready <= LatencyPipe_1.io.in.ready @[TileTester.scala 162:16] + dut.io.nasti.r.bits <= LatencyPipe_1.io.out.bits @[TileTester.scala 66:18] + dut.io.nasti.r.valid <= LatencyPipe_1.io.out.valid @[TileTester.scala 66:18] + LatencyPipe_1.io.out.ready <= dut.io.nasti.r.ready @[TileTester.scala 66:18] + wire _T_3126 : { resp : UInt<2>, id : UInt<5>, user : UInt<1>} @[nasti.scala 223:17] + _T_3126 is invalid @[nasti.scala 223:17] + _T_3126.id <= id @[nasti.scala 224:10] + _T_3126.resp <= UInt<1>("h0") @[nasti.scala 225:12] + _T_3126.user <= UInt<1>("h0") @[nasti.scala 226:12] + bpipe.bits.user <= _T_3126.user @[TileTester.scala 67:15] + bpipe.bits.id <= _T_3126.id @[TileTester.scala 67:15] + bpipe.bits.resp <= _T_3126.resp @[TileTester.scala 67:15] + node _T_3127 = eq(state, UInt<3>("h3")) @[TileTester.scala 68:24] + bpipe.valid <= _T_3127 @[TileTester.scala 68:15] + node _T_3128 = add(addr, off) @[TileTester.scala 69:53] + node _T_3129 = tail(_T_3128, 1) @[TileTester.scala 69:53] + node _T_3130 = bits(_T_3129, 19, 0) @[TileTester.scala 69:47] + infer mport _T_3131 = _mem[_T_3130], clock @[TileTester.scala 69:47] + node _T_3132 = eq(off, len) @[TileTester.scala 69:65] + wire _T_3133 : { resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} @[nasti.scala 211:17] + _T_3133 is invalid @[nasti.scala 211:17] + _T_3133.id <= id @[nasti.scala 212:10] + _T_3133.data <= _T_3131 @[nasti.scala 213:12] + _T_3133.last <= _T_3132 @[nasti.scala 214:12] + _T_3133.resp <= UInt<1>("h0") @[nasti.scala 215:12] + _T_3133.user <= UInt<1>("h0") @[nasti.scala 216:12] + rpipe.bits.user <= _T_3133.user @[TileTester.scala 69:15] + rpipe.bits.id <= _T_3133.id @[TileTester.scala 69:15] + rpipe.bits.last <= _T_3133.last @[TileTester.scala 69:15] + rpipe.bits.data <= _T_3133.data @[TileTester.scala 69:15] + rpipe.bits.resp <= _T_3133.resp @[TileTester.scala 69:15] + node _T_3134 = eq(state, UInt<3>("h4")) @[TileTester.scala 70:24] + rpipe.valid <= _T_3134 @[TileTester.scala 70:15] + wire isDone : UInt<1> + isDone <= UInt<1>("h0") + wire setDone : UInt<1> + setDone <= UInt<1>("h0") + node _T_3135 = neq(state, UInt<3>("h0")) @[TileTester.scala 75:14] + when _T_3135 : @[TileTester.scala 75:25] + node _T_3136 = add(cycle, UInt<1>("h1")) @[TileTester.scala 76:20] + node _T_3137 = tail(_T_3136, 1) @[TileTester.scala 76:20] + cycle <= _T_3137 @[TileTester.scala 76:11] + node _T_3138 = lt(cycle, UInt<21>("h16e360")) @[TileTester.scala 77:18] + node _T_3139 = bits(reset, 0, 0) @[TileTester.scala 77:11] + node _T_3140 = or(_T_3138, _T_3139) @[TileTester.scala 77:11] + node _T_3141 = eq(_T_3140, UInt<1>("h0")) @[TileTester.scala 77:11] + when _T_3141 : @[TileTester.scala 77:11] + printf(clock, UInt<1>("h1"), "Assertion failed\n at TileTester.scala:77 assert(cycle < maxcycles.U)\n") @[TileTester.scala 77:11] + stop(clock, UInt<1>("h1"), 1) @[TileTester.scala 77:11] + node _T_3142 = neq(dut.io.host.tohost, UInt<1>("h0")) @[TileTester.scala 78:29] + when _T_3142 : @[TileTester.scala 78:38] + isDone <= UInt<1>("h1") @[TileTester.scala 79:14] + setDone <= isDone @[TileTester.scala 83:11] + when setDone : @[TileTester.scala 84:17] + node _T_3143 = bits(reset, 0, 0) @[TileTester.scala 85:11] + node _T_3144 = eq(_T_3143, UInt<1>("h0")) @[TileTester.scala 85:11] + when _T_3144 : @[TileTester.scala 85:11] + printf(clock, UInt<1>("h1"), "cycles: %d\n", cycle) @[TileTester.scala 85:11] + node _T_3145 = dshr(dut.io.host.tohost, UInt<1>("h1")) @[TileTester.scala 86:32] + node _T_3146 = eq(_T_3145, UInt<1>("h0")) @[TileTester.scala 86:40] + node _T_3147 = bits(reset, 0, 0) @[TileTester.scala 86:11] + node _T_3148 = or(_T_3146, _T_3147) @[TileTester.scala 86:11] + node _T_3149 = eq(_T_3148, UInt<1>("h0")) @[TileTester.scala 86:11] + when _T_3149 : @[TileTester.scala 86:11] + printf(clock, UInt<1>("h1"), "Assertion failed: * tohost: %d *\n\n at TileTester.scala:86 assert((dut.io.host.tohost >> 1.U) === 0.U,\n", dut.io.host.tohost) @[TileTester.scala 86:11] + stop(clock, UInt<1>("h1"), 1) @[TileTester.scala 86:11] + node _T_3150 = bits(reset, 0, 0) @[TileTester.scala 88:9] + node _T_3151 = eq(_T_3150, UInt<1>("h0")) @[TileTester.scala 88:9] + when _T_3151 : @[TileTester.scala 88:9] + stop(clock, UInt<1>("h1"), 0) @[TileTester.scala 88:9] + wire chunk : UInt<64> @[TileTester.scala 91:19] + node _T_3152 = dshr(cntr, UInt<4>("h8")) @[TileTester.scala 92:23] + node _T_3153 = bits(_T_3152, 3, 0) + node _T_3154 = bits(cntr, 7, 0) @[TileTester.scala 92:47] + node _T_3155 = mul(_T_3154, UInt<7>("h40")) @[TileTester.scala 92:54] + node _T_3156 = dshr(_hex[_T_3153], _T_3155) @[TileTester.scala 92:39] + chunk <= _T_3156 @[TileTester.scala 92:9] + node _T_3157 = eq(UInt<3>("h0"), state) @[Conditional.scala 37:30] + when _T_3157 : @[Conditional.scala 40:58] + infer mport _T_3158 = _mem[cntr], clock @[TileTester.scala 96:11] + _T_3158 <= chunk @[TileTester.scala 96:18] + when done : @[TileTester.scala 97:18] + state <= UInt<3>("h1") @[TileTester.scala 97:26] + else : + node _T_3159 = eq(UInt<3>("h1"), state) @[Conditional.scala 37:30] + when _T_3159 : @[Conditional.scala 39:67] + when dut.io.nasti.aw.valid : @[TileTester.scala 101:35] + node _T_3160 = dshl(UInt<1>("h1"), dut.io.nasti.aw.bits.size) @[TileTester.scala 102:21] + node _T_3161 = eq(_T_3160, UInt<4>("h8")) @[TileTester.scala 102:58] + node _T_3162 = bits(reset, 0, 0) @[TileTester.scala 102:15] + node _T_3163 = or(_T_3161, _T_3162) @[TileTester.scala 102:15] + node _T_3164 = eq(_T_3163, UInt<1>("h0")) @[TileTester.scala 102:15] + when _T_3164 : @[TileTester.scala 102:15] + printf(clock, UInt<1>("h1"), "Assertion failed\n at TileTester.scala:102 assert((1.U << dut.io.nasti.aw.bits.size).asUInt === (nastiXDataBits / 8).U)\n") @[TileTester.scala 102:15] + stop(clock, UInt<1>("h1"), 1) @[TileTester.scala 102:15] + node _T_3165 = div(dut.io.nasti.aw.bits.addr, UInt<4>("h8")) @[TileTester.scala 103:43] + addr <= _T_3165 @[TileTester.scala 103:14] + id <= dut.io.nasti.aw.bits.id @[TileTester.scala 104:12] + len <= dut.io.nasti.aw.bits.len @[TileTester.scala 105:13] + off <= UInt<1>("h0") @[TileTester.scala 106:13] + state <= UInt<3>("h2") @[TileTester.scala 107:15] + else : + when dut.io.nasti.ar.valid : @[TileTester.scala 108:41] + node _T_3166 = dshl(UInt<1>("h1"), dut.io.nasti.ar.bits.size) @[TileTester.scala 109:21] + node _T_3167 = eq(_T_3166, UInt<4>("h8")) @[TileTester.scala 109:58] + node _T_3168 = bits(reset, 0, 0) @[TileTester.scala 109:15] + node _T_3169 = or(_T_3167, _T_3168) @[TileTester.scala 109:15] + node _T_3170 = eq(_T_3169, UInt<1>("h0")) @[TileTester.scala 109:15] + when _T_3170 : @[TileTester.scala 109:15] + printf(clock, UInt<1>("h1"), "Assertion failed\n at TileTester.scala:109 assert((1.U << dut.io.nasti.ar.bits.size).asUInt === (nastiXDataBits / 8).U)\n") @[TileTester.scala 109:15] + stop(clock, UInt<1>("h1"), 1) @[TileTester.scala 109:15] + node _T_3171 = div(dut.io.nasti.ar.bits.addr, UInt<4>("h8")) @[TileTester.scala 110:43] + addr <= _T_3171 @[TileTester.scala 110:14] + id <= dut.io.nasti.aw.bits.id @[TileTester.scala 111:12] + len <= dut.io.nasti.ar.bits.len @[TileTester.scala 112:13] + off <= UInt<1>("h0") @[TileTester.scala 113:13] + state <= UInt<3>("h4") @[TileTester.scala 114:15] + else : + node _T_3172 = eq(UInt<3>("h2"), state) @[Conditional.scala 37:30] + when _T_3172 : @[Conditional.scala 39:67] + when dut.io.nasti.w.valid : @[TileTester.scala 118:34] + node _T_3173 = add(addr, off) @[TileTester.scala 119:19] + node _T_3174 = tail(_T_3173, 1) @[TileTester.scala 119:19] + node _T_3175 = bits(_T_3174, 19, 0) @[TileTester.scala 119:13] + infer mport _T_3176 = _mem[_T_3175], clock @[TileTester.scala 119:13] + _T_3176 <= write @[TileTester.scala 119:26] + node _T_3177 = eq(off, len) @[TileTester.scala 121:18] + when _T_3177 : @[TileTester.scala 121:27] + node _T_3178 = bits(reset, 0, 0) @[TileTester.scala 122:17] + node _T_3179 = or(dut.io.nasti.w.bits.last, _T_3178) @[TileTester.scala 122:17] + node _T_3180 = eq(_T_3179, UInt<1>("h0")) @[TileTester.scala 122:17] + when _T_3180 : @[TileTester.scala 122:17] + printf(clock, UInt<1>("h1"), "Assertion failed\n at TileTester.scala:122 assert(dut.io.nasti.w.bits.last)\n") @[TileTester.scala 122:17] + stop(clock, UInt<1>("h1"), 1) @[TileTester.scala 122:17] + state <= UInt<3>("h3") @[TileTester.scala 123:17] + else : + node _T_3181 = add(off, UInt<1>("h1")) @[TileTester.scala 125:22] + node _T_3182 = tail(_T_3181, 1) @[TileTester.scala 125:22] + off <= _T_3182 @[TileTester.scala 125:15] + else : + node _T_3183 = eq(UInt<3>("h3"), state) @[Conditional.scala 37:30] + when _T_3183 : @[Conditional.scala 39:67] + when bpipe.ready : @[TileTester.scala 130:25] + state <= UInt<3>("h1") @[TileTester.scala 131:15] + else : + node _T_3184 = eq(UInt<3>("h4"), state) @[Conditional.scala 37:30] + when _T_3184 : @[Conditional.scala 39:67] + when rpipe.ready : @[TileTester.scala 135:25] + node _T_3185 = eq(off, len) @[TileTester.scala 136:18] + when _T_3185 : @[TileTester.scala 136:27] + state <= UInt<3>("h1") @[TileTester.scala 137:17] + else : + node _T_3186 = add(off, UInt<1>("h1")) @[TileTester.scala 139:22] + node _T_3187 = tail(_T_3186, 1) @[TileTester.scala 139:22] + off <= _T_3187 @[TileTester.scala 139:15] diff --git a/src/test/resources/coverage/RiscVMiniTileTester.fsm.json b/src/test/resources/coverage/RiscVMiniTileTester.fsm.json new file mode 100644 index 000000000..2b05de485 --- /dev/null +++ b/src/test/resources/coverage/RiscVMiniTileTester.fsm.json @@ -0,0 +1,36 @@ +[ + { + "class":"firrtl2.annotations.EnumDefAnnotation", + "typeName":"CacheState", + "definition":{ + "sIdle":0, + "sReadCache":1, + "sWriteCache":2, + "sWriteBack":3, + "sWriteAck":4, + "sRefillReady":5, + "sRefill":6 + } + }, + { + "class":"firrtl2.annotations.EnumComponentAnnotation", + "target":"TileTester.Cache.state", + "enumTypeName":"CacheState" + }, + { + "class":"firrtl2.annotations.EnumDefAnnotation", + "typeName":"MemArbiterState", + "definition":{ + "sIdle":0, + "sICacheRead":1, + "sDCacheRead":2, + "sDCacheWrite":3, + "sDCacheAck":4 + } + }, + { + "class":"firrtl2.annotations.EnumComponentAnnotation", + "target":"TileTester.MemArbiter.state", + "enumTypeName":"MemArbiterState" + } +] diff --git a/src/test/scala/chiseltest/coverage/CodeBaseTest.scala b/src/test/scala/chiseltest/coverage/CodeBaseTest.scala new file mode 100644 index 000000000..173c355bb --- /dev/null +++ b/src/test/scala/chiseltest/coverage/CodeBaseTest.scala @@ -0,0 +1,28 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import org.scalatest.flatspec.AnyFlatSpec + +class CodeBaseTest extends AnyFlatSpec { + behavior.of("CodeBase") + + it should "read in a code base" in { + val c = new CodeBase(os.pwd / "src" / "test" / "scala") + + // get this line with only the filename + assert(c.getLine("CodeBaseTest.scala", 15).get.trim == "// get this line with only the filename") + // get this line with relative path + assert( + c.getLine("chiseltest/coverage/CodeBaseTest.scala", 17).get.trim == + "// get this line with relative path" + ) + } + + it should "by default use the same root dir as chisel" in { + val c = new CodeBase() + assert(c.root == os.pwd) + } +} diff --git a/src/test/scala/chiseltest/coverage/CompilerTest.scala b/src/test/scala/chiseltest/coverage/CompilerTest.scala index b568c432e..dc77134a8 100644 --- a/src/test/scala/chiseltest/coverage/CompilerTest.scala +++ b/src/test/scala/chiseltest/coverage/CompilerTest.scala @@ -1,8 +1,11 @@ -// SPDX-License-Identifier: Apache-2.0 +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer package chiseltest.coverage -import chisel3.Module +import chiseltest.simulator.Compiler +import chisel3.{Module, RawModule} import chisel3.stage.ChiselGeneratorAnnotation import chiseltest.ChiselScalatestTester import chiseltest.internal.TesterUtils.sanitizeFileName @@ -13,34 +16,69 @@ import firrtl2.{ EmittedVerilogCircuitAnnotation, EmittedVerilogModuleAnnotation } -import firrtl2.options.TargetDirAnnotation +import firrtl2.options.{InputAnnotationFileAnnotation, TargetDirAnnotation} +import firrtl2.stage.{FirrtlCircuitAnnotation, FirrtlFileAnnotation, FirrtlStage} import org.scalatest.TestSuite import java.io.File /** Base trait for tests that need to compile a circuit and inspect the resulting firrtl / Verilog */ -trait CompilerTest extends ChiselScalatestTester { this: TestSuite => +trait CompilerTest extends ChiselScalatestTester { + this: TestSuite => protected def annos: AnnotationSeq = Seq() + private def firrtlStage = new FirrtlStage - /** @return the emitted firrtl/Verilog source code and the annotations produced by running the ChiselStage */ - protected def compile[M <: Module](gen: => M, target: String, a: AnnotationSeq = List(), ll: String = "warn") - : (String, AnnotationSeq) = ??? - // TODO -// { -// val stage = new ChiselStage -// -// // ensure that test files don't just end up in the root directory -// val testName = sanitizeFileName(scalaTestContext.value.get.name) -// val testRunDir = TargetDirAnnotation("test_run_dir" + File.separator + testName) -// -// val r = stage.execute(Array("-X", target, "-ll", ll), ChiselGeneratorAnnotation(() => gen) +: testRunDir +: a ++: annos) -// val src = r.collect { -// case EmittedFirrtlCircuitAnnotation(a) => a -// case EmittedFirrtlModuleAnnotation(a) => a -// case EmittedVerilogCircuitAnnotation(a) => a -// case EmittedVerilogModuleAnnotation(a) => a -// }.map(_.value).mkString("") -// -// (src, r) -// } + private def stateToAnnos(state: firrtl2.CircuitState): AnnotationSeq = { + val annosWithoutCircuit = state.annotations.filterNot(_.isInstanceOf[FirrtlCircuitAnnotation]) + FirrtlCircuitAnnotation(state.circuit) +: annosWithoutCircuit + } + + private def toLowFirrtl(state: firrtl2.CircuitState): AnnotationSeq = { + Compiler.requireTargetDir(state.annotations) + val inAnnos = stateToAnnos(state) + firrtlStage.execute(Array("-E", "low"), inAnnos) + } + protected def compile[M <: RawModule]( + gen: => M, + target: String = "low", + a: AnnotationSeq = List(), + ll: String = "warn" + ): (String, AnnotationSeq) = { + val (hi, _) = Compiler.elaborate(() => gen, testRunDir +: a ++: annos, Seq()) + Compiler.requireTargetDir(hi.annotations) + val res = firrtlStage.execute(Array("-E", target), stateToAnnos(hi)) + (extractSource(res), res) + } + + protected def compileFile( + firrtlFile: os.Path, + annoFile: os.Path, + target: String, + a: AnnotationSeq = List(), + ll: String = "warn" + ): (String, AnnotationSeq) = { + assert(os.exists(firrtlFile), firrtlFile.toString()) + assert(os.exists(annoFile), annoFile.toString()) + val stage = new FirrtlStage + val fileAnnos = Seq(FirrtlFileAnnotation(firrtlFile.toString()), InputAnnotationFileAnnotation(annoFile.toString())) + val r = stage.execute(Array("-E", target, "-ll", ll), fileAnnos ++: testRunDir +: a ++: annos) + (extractSource(r), r) + } + + private def extractSource(annos: AnnotationSeq): String = { + val src = annos.collect { + case EmittedFirrtlCircuitAnnotation(a) => a + case EmittedFirrtlModuleAnnotation(a) => a + case EmittedVerilogCircuitAnnotation(a) => a + case EmittedVerilogModuleAnnotation(a) => a + }.map(_.value).mkString("") + src + } + + private def testRunDir: TargetDirAnnotation = { + // ensure that test files don't just end up in the root directory + val testName = sanitizeFileName(scalaTestContext.value.get.name) + val testRunDir = TargetDirAnnotation("test_run_dir" + File.separator + testName) + testRunDir + } } diff --git a/src/test/scala/chiseltest/coverage/CoverValuesTest.scala b/src/test/scala/chiseltest/coverage/CoverValuesTest.scala new file mode 100644 index 000000000..2bf51bbb3 --- /dev/null +++ b/src/test/scala/chiseltest/coverage/CoverValuesTest.scala @@ -0,0 +1,83 @@ +package chiseltest.coverage + +import chisel3._ +import org.scalatest.flatspec.AnyFlatSpec +import treadle2.TreadleTester + +import scala.collection.mutable + +object dontTouchMem { + def apply(mem: MemBase[_]): Unit = { + chisel3.experimental.annotate(new chisel3.experimental.ChiselAnnotation { + override def toFirrtl: firrtl.annotations.Annotation = firrtl.transforms.DontTouchAnnotation(mem.toTarget) + }) + } +} + +object coverValues { + private val CounterResolution = 32 + private val MaxCount = (BigInt(1) << CounterResolution) - 1 + def apply(signal: UInt, name: String): Unit = { + val bits = signal.getWidth + val entries = BigInt(1) << bits + val counter = SyncReadMem(entries, UInt(CounterResolution.W), SyncReadMem.WriteFirst) + // name counter and mark it as don't touch in order to be able to access it through the simulator + dontTouchMem(counter.suggestName(name)) + // it takes one cycle to read the current count + val prev_count = counter.read(signal) + val prev_signal = RegNext(signal) + // we update the counter after the read cycle + val prev_count_plus_one = Mux(prev_count === MaxCount.U, prev_count, prev_count + 1.U) + // we need to only start recording 1 cycle after reset + val reset = Module.reset.asBool + val delayedReset = RegNext(reset) + when(!reset && !delayedReset) { + counter.write(prev_signal, prev_count_plus_one) + } + } +} + +class CoverValuesMockUp(signalBits: Int) extends Module { + val signal = IO(Input(UInt(signalBits.W))) + coverValues(signal, "cnt") +} + +class CoverValuesTest extends AnyFlatSpec with CompilerTest { + behavior.of("cover-values") + + it should "count how often a signal is covered" in { + val SignalBits = 4 + + // we need to use treadle in order to be able to read out memories + val (src, r) = compile(new CoverValuesMockUp(SignalBits)) + // println(src) + val dut = TreadleTester(r :+ treadle2.WriteVcdAnnotation) + + // generate some signal value + val rnd = new scala.util.Random(0) + val values = (0 until 100).map(_ => BigInt(4, rnd)) + + // reset circuit + dut.poke("reset", 1) + dut.step(1) + dut.poke("reset", 0) + + // apply values + values.foreach { value => + dut.poke("signal", value) + dut.step() + } + dut.step() // update counts + dut.finish // finish simulation, save VCD + + // calculate expected counts + val counts = mutable.HashMap[BigInt, Int]() + values.foreach { ii => counts(ii) = counts.getOrElse(ii, 0) + 1 } + val expectedCounts = (0 until (1 << SignalBits)).map(ii => counts.getOrElse(ii, 0)) + + // get back counts from mem + val hwCounts = (0 until (1 << SignalBits)).map(ii => dut.peekMemory("cnt", ii).toInt) + assert(hwCounts == expectedCounts) + } + +} diff --git a/src/test/scala/chiseltest/coverage/CoverageTest.scala b/src/test/scala/chiseltest/coverage/CoverageTest.scala new file mode 100644 index 000000000..5a714282d --- /dev/null +++ b/src/test/scala/chiseltest/coverage/CoverageTest.scala @@ -0,0 +1,19 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import firrtl2.ir +import org.scalatest.flatspec.AnyFlatSpec + +class CoverageTest extends AnyFlatSpec { + + "parseFileInfo" should "be robust" in { + assert( + Coverage.parseFileInfo(ir.FileInfo("Atomics.scala 35:16 Atomics.scala 35:16")) == + Seq("Atomics.scala" -> 35, "Atomics.scala" -> 35) + ) + } + +} diff --git a/src/test/scala/chiseltest/coverage/FsmCoverageTest.scala b/src/test/scala/chiseltest/coverage/FsmCoverageTest.scala new file mode 100644 index 000000000..1cb1c1090 --- /dev/null +++ b/src/test/scala/chiseltest/coverage/FsmCoverageTest.scala @@ -0,0 +1,98 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import chisel3._ +import chiseltest._ +import chiseltest.coverage.circuits.FifoRegister +import firrtl2._ +import firrtl2.options.Dependency +import firrtl2.stage.RunFirrtlTransformAnnotation +import org.scalatest.flatspec.AnyFlatSpec + +class FsmCoverageTest extends AnyFlatSpec with ChiselScalatestTester { + behavior.of("FsmCoverage") + + it should "accurately count the states and transitions" in { + val r = runTest() + + val data = FsmCoverage.processCoverage(r) + assert(data.length == 1, "There is exactly one FSM in the design!") + + val fsm = data.head + assert(fsm.name == "FifoRegister.stateReg") + assert(fsm.states.map(_._1) == List("Empty", "Full")) + assert( + fsm.transitions.map(_._1) == List("Empty" -> "Empty", "Empty" -> "Full", "Full" -> "Empty", "Full" -> "Full") + ) + + val totalCycles = 15 // excludes single reset cycle in the beginning + assert(fsm.states.map(_._2).sum == totalCycles, "We are in exactly one state each cycle!") + assert( + fsm.transitions.map(_._2).sum == totalCycles - 1, + "We take exactly one transition every cycle besides the first one" + ) + + val t = fsm.transitions.toMap + assert(t("Empty" -> "Empty") == 6) + assert(t("Empty" -> "Full") == 4) + assert(t("Full" -> "Empty") == 3) + assert(t("Full" -> "Full") == 1) + } + + private def runTest(): AnnotationSeq = { + val rand = new scala.util.Random(0) + val r = test(new FifoRegister(8)).withAnnotations(FsmCoverage.annotations ++ Seq(WriteVcdAnnotation)) { dut => + (0 until 4).foreach { _ => + // push until full + while (dut.io.enq.ready.peek().litToBoolean) { + dut.io.enq.bits.poke(BigInt(8, rand).U) + val skip = rand.nextBoolean() + dut.io.enq.valid.poke((!skip).B) + dut.io.deq.ready.poke(false.B) + dut.clock.step() + } + + // pop until empty + while (dut.io.deq.valid.peek().litToBoolean) { + dut.io.enq.valid.poke(false.B) + val skip = rand.nextBoolean() + dut.io.deq.ready.poke((!skip).B) + dut.clock.step() + } + } + } + r.getAnnotationSeq + } +} + +class FsmCoverageInstrumentationTest extends AnyFlatSpec with CompilerTest { + behavior.of("FsmCoverage Instrumentation") + + override protected def annos = Seq(RunFirrtlTransformAnnotation(Dependency(FsmCoveragePass))) + + it should "add cover statements" in { + val (result, rAnnos) = compile(new FifoRegister(8), "low") + // println(result) + val l = result.split('\n').map(_.trim).map(_.split('@').head.trim) + + // we expect six custom cover points (2 states, 4 transitions) + assert(l.contains("""cover(clock, eq(stateReg, UInt<1>("h0")), not(reset), "") : stateReg_Empty""")) + assert(l.contains("""cover(clock, eq(stateReg, UInt<1>("h1")), not(reset), "") : stateReg_Full""")) + assert( + l.contains( + """cover(clock, and(eq(stateReg_prev, UInt<1>("h0")), eq(stateReg, UInt<1>("h1"))), stateReg_t_valid, "") : stateReg_Empty_to_Full""" + ) + ) + val coverCount = l.count(_.contains("cover(")) + assert(coverCount == 6) + + // we should have 1 coverage annotation for 2 + 4 (cover) + 1 (stateReg) targets + val a = rAnnos.collect { case a: FsmCoverageAnnotation => a } + assert(a.size == 1) + assert(a.head.targets.length == (2 + 4 + 1)) + } + +} diff --git a/src/test/scala/chiseltest/coverage/FsmInfoPassTests.scala b/src/test/scala/chiseltest/coverage/FsmInfoPassTests.scala new file mode 100644 index 000000000..50d683df4 --- /dev/null +++ b/src/test/scala/chiseltest/coverage/FsmInfoPassTests.scala @@ -0,0 +1,196 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import chisel3._ +import chisel3.util._ +import chiseltest.coverage.circuits.FifoRegister +import firrtl2._ +import firrtl2.options.Dependency +import firrtl2.stage.RunFirrtlTransformAnnotation +import org.scalatest.flatspec.AnyFlatSpec + +object FsmState extends ChiselEnum { + val A, B, C = Value +} + +class ExampleFsm1 extends Module { + val in = IO(Input(Bool())) + val out = IO(Output(UInt(3.W))) + import FsmState._ + + val state = RegInit(A) + switch(state) { + is(A) { state := Mux(in, A, B) } + is(B) { + when(in) { state := B }.otherwise { state := C } + } + } + out := state.asUInt +} + +class FsmInfoPassTests extends AnyFlatSpec with CompilerTest { + + override protected def annos = Seq(RunFirrtlTransformAnnotation(Dependency(FsmInfoPass))) + + private def getSingleInfo(rAnnos: AnnotationSeq): FsmInfoAnnotation = { + val infos = rAnnos.collect { case a: FsmInfoAnnotation => a } + assert(infos.length == 1, "expected exactly one info since there is only one FSM in the design") + infos.head + } + + it should "properly analyze the FIFO register FSM" in { + val (_, rAnnos) = compile(new FifoRegister(8), "low") + val info = getSingleInfo(rAnnos) + + checkInfo( + info, + states = Seq(0 -> "Empty", 1 -> "Full"), + start = Some("Empty"), + transitions = Seq( + "Empty" -> "Empty", + "Empty" -> "Full", + "Full" -> "Empty", + "Full" -> "Full" + ) + ) + } + + it should "analyze the Example FSM 1" in { + val (_, rAnnos) = compile(new ExampleFsm1, "low") + val info = getSingleInfo(rAnnos) + + checkInfo( + info, + states = Seq(0 -> "A", 1 -> "B", 2 -> "C"), + start = Some("A"), + transitions = Seq( + "A" -> "A", + "A" -> "B", + "B" -> "B", + "B" -> "C", + "C" -> "C" + ) + ) + } + + val ResourceDir = os.pwd / "src" / "test" / "resources" / "coverage" + + it should "properly analyze the FSMs in RISC-V Mini" in { + val (_, rAnnos) = + compileFile(ResourceDir / "RiscVMiniTileTester.fir", ResourceDir / "RiscVMiniTileTester.fsm.json", "low") + val infos = rAnnos.collect { case a: FsmInfoAnnotation => a } + + // The Cache has a state machine + val cacheInfo = infos.find(_.target.toString().contains("Cache")).get + checkInfo( + cacheInfo, + states = Seq( + 0 -> "sIdle", + 1 -> "sReadCache", + 2 -> "sWriteCache", + 3 -> "sWriteBack", + 4 -> "sWriteAck", + 5 -> "sRefillReady", + 6 -> "sRefill" + ), + start = Some("sIdle"), + // transitions from a manual analysis + transitions = Seq( + // is(sIdle) + "sIdle" -> "sIdle", // !io.cpu.req.valid + "sIdle" -> "sWriteCache", // io.cpu.req.valid && io.cpu.req.bits.mask.orR + "sIdle" -> "sReadCache", // io.cpu.req.valid && !io.cpu.req.bits.mask.orR + // is(sReadCache) + "sReadCache" -> "sWriteCache", // hit && io.cpu.req.valid && io.cpu.req.bits.mask.orR + "sReadCache" -> "sReadCache", // hit && io.cpu.req.valid && !io.cpu.req.bits.mask.orR + "sReadCache" -> "sIdle", // hit && !io.cpu.req.valid + "sReadCache" -> "sWriteBack", // !hit && io.nasti.aw.fire + "sReadCache" -> "sRefill", // !hit && !io.nasti.aw.fire && io.nasti.ar.fire + "sReadCache" -> "sReadCache", // !hit && !io.nasti.aw.fire && !io.nasti.ar.fire + // is(sWriteCache) + "sWriteCache" -> "sIdle", // (hit || is_alloc_reg || io.cpu.abort) + "sWriteCache" -> "sWriteBack", // !(hit || is_alloc_reg || io.cpu.abort) && io.nasti.aw.fire + "sWriteCache" -> "sRefill", // !(hit || is_alloc_reg || io.cpu.abort) && !io.nasti.aw.fire && io.nasti.ar.fire + "sWriteCache" -> "sWriteCache", // !(hit || is_alloc_reg || io.cpu.abort) && !io.nasti.aw.fire && !io.nasti.ar.fire + // is(sWriteBack) + "sWriteBack" -> "sWriteAck", // write_wrap_out + "sWriteBack" -> "sWriteBack", // !write_wrap_out + // is(sWriteAck) + "sWriteAck" -> "sRefillReady", // io.nasti.b.fire + "sWriteAck" -> "sWriteAck", // !io.nasti.b.fire + // is(sRefillReady) + "sRefillReady" -> "sRefill", // io.nasti.b.fire + "sRefillReady" -> "sRefillReady", // !io.nasti.b.fire + // is(sRefill) + "sRefill" -> "sWriteCache", // read_wrap_out && cpu_mask.orR + "sRefill" -> "sIdle", // read_wrap_out && !cpu_mask.orR + "sRefill" -> "sRefill" // !read_wrap_out + ) + ) + + val arbiterInfo = infos.find(_.target.toString().contains("MemArbiter")).get + checkInfo( + arbiterInfo, + states = Seq(0 -> "sIdle", 1 -> "sICacheRead", 2 -> "sDCacheRead", 3 -> "sDCacheWrite", 4 -> "sDCacheAck"), + start = Some("sIdle"), + transitions = Seq( + // is(sIdle) + "sIdle" -> "sDCacheWrite", // io.dcache.aw.fire + "sIdle" -> "sDCacheRead", // !io.dcache.aw.fire && io.dcache.ar.fire + "sIdle" -> "sICacheRead", // !io.dcache.aw.fire && !io.dcache.ar.fire && io.icache.ar.fire + "sIdle" -> "sIdle", // !io.dcache.aw.fire && !io.dcache.ar.fire && !io.icache.ar.fire + // is(sICacheRead) + "sICacheRead" -> "sIdle", // (io.nasti.r.fire && io.nasti.r.bits.last) + "sICacheRead" -> "sICacheRead", // !(io.nasti.r.fire && io.nasti.r.bits.last) + // is(sDCacheRead) + "sDCacheRead" -> "sIdle", // (io.nasti.r.fire && io.nasti.r.bits.last) + "sDCacheRead" -> "sDCacheRead", // !(io.nasti.r.fire && io.nasti.r.bits.last) + // is(sDCacheWrite) + "sDCacheWrite" -> "sDCacheAck", // (io.dcache.w.fire && io.dcache.w.bits.last) + "sDCacheWrite" -> "sDCacheWrite", // !(io.dcache.w.fire && io.dcache.w.bits.last) + // is(sDCacheAck) + "sDCacheAck" -> "sIdle", // io.nasti.b.fire + "sDCacheAck" -> "sDCacheAck" // !io.nasti.b.fire + ) + ) + } + + private def checkInfo( + info: FsmInfoAnnotation, + states: Seq[(Int, String)], + start: Option[String], + transitions: Seq[(String, String)] + ): Unit = { + // ensure unique state names + val uniqueNames = states.map(_._2).distinct + assert(uniqueNames.length == states.length, "We assume unique state names!") + + // check for missing or misnamed states + val infoStateIndex = info.states.toMap + states.foreach { case (ii, name) => + assert(infoStateIndex.contains(ii), s"State $name ($ii) missing from info annotation!") + assert(infoStateIndex(ii) == name, s"State #$ii is named ${infoStateIndex(ii)} instead of $name") + } + + // check for states that were not expected + assert(states.length == info.states.length, s"More states than expected in info annotation: ${info.states}") + + // check for missing transitions: + val infoTransitionIndex = info.transitions.map { case (from, to) => + s"${infoStateIndex(from)} -> ${infoStateIndex(to)}" + }.toSet + transitions.foreach { case (from, to) => + val name = s"$from -> $to" + assert(infoTransitionIndex.contains(name), "missing transition") + } + + // check for unexpected transition + val expectedTransitionIndex = transitions.map { case (from, to) => s"$from -> $to" }.toSet + infoTransitionIndex.toSeq.sorted.foreach { name => + assert(expectedTransitionIndex.contains(name), "unexpected transition") + } + } +} diff --git a/src/test/scala/chiseltest/coverage/LineCoverageTest.scala b/src/test/scala/chiseltest/coverage/LineCoverageTest.scala new file mode 100644 index 000000000..b8ca6cb47 --- /dev/null +++ b/src/test/scala/chiseltest/coverage/LineCoverageTest.scala @@ -0,0 +1,147 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import chisel3._ +import chiseltest._ +import chiseltest.coverage.circuits.Test1Module +import firrtl2._ +import firrtl2.annotations.CircuitTarget +import firrtl2.options.Dependency +import firrtl2.stage.RunFirrtlTransformAnnotation +import org.scalatest.flatspec.AnyFlatSpec + +class LineCoverageTest extends AnyFlatSpec with ChiselScalatestTester { + it should "parse the results from the simulator" in { + val r = runTest() + + val data = LineCoverage.processCoverage(r) + assert(data.files.size == 1) + + val file = data.files.head + assert(file.name == "src/test/scala/chiseltest/coverage/circuits/Test1Module.scala") + + val offset = 12 + val expected = List( + // Test1Module + (5, 5), + (7, 5), + (8, 0), // apparently `a` is never four + (11, 5), + (12, 1), + (14, 4), + (17, 5), + (21, 5), + (26, 5), + (27, 5), + (30, 5), + (31, 5), + (32, 5), + (33, 5), + // SubModule1 (instantiated twice!) + (39, 10) + ) + + assert(file.lines == expected.map(e => (e._1 + offset, e._2))) + } + + it should "generate a textual report" in { + val data = LineCoverage.processCoverage(runTest()) + val code = new CodeBase() + val report = LineCoverage.textReport(code, data.files.head).toVector + val lines = report.map(_.trim) + + // check some lines + val offset = 12 + 2 // the 2 accounts for the table headers + assert(lines(0 + offset).startsWith(s"${1 + offset - 2} | | class Test1Module(")) + assert(lines(4 + offset).startsWith(s"${5 + offset - 2} | 5 | b := 0.U // line 5")) + assert(lines(7 + offset).startsWith(s"${8 + offset - 2} | 0 | b := 1.U")) + + // this is how you would print the whole report + // println(report.mkString("\n")) + } + + private def runTest(): AnnotationSeq = { + val rand = new scala.util.Random(0) + val r = test(new Test1Module(withSubmodules = true)).withAnnotations(LineCoverage.annotations) { dut => + (0 until 4).foreach { _ => + dut.a.poke(BigInt(3, rand).U) + dut.clock.step() + } + } + r.getAnnotationSeq + } +} + +class LineCoverageInstrumentationTest extends AnyFlatSpec with CompilerTest { + behavior.of("LineCoverage") + + override protected def annos = Seq(RunFirrtlTransformAnnotation(Dependency(LineCoveragePass))) + + it should "add cover statements" in { + val (result, rAnnos) = compile(new Test1Module(), "low-opt") + val l = result.split('\n').map(_.trim) + + // we expect four custom cover points + assert(l.exists(l => l.startsWith("cover(") && l.endsWith("l_0"))) + assert(l.exists(l => l.startsWith("cover(") && l.endsWith("l_1"))) + assert(l.exists(l => l.startsWith("cover(") && l.endsWith("l_2"))) + assert(l.exists(l => l.startsWith("cover(") && l.endsWith("l_3"))) + assert(!l.exists(l => l.startsWith("cover(") && l.endsWith("l_4"))) + + // we should have 4 coverage annotations as well + val a = rAnnos.collect { case a: LineCoverageAnnotation => a } + assert(a.size == 4) + + // lines for each coverage point (relative to the "class Test1Module " line) + val offset = 12 + val lines = Map( + "l_3" -> Seq(5, 7, 11, 17, 21, 26, 27), + "l_0" -> Seq(8), + "l_1" -> Seq(12), + "l_2" -> Seq(14) + ) + + // all annotations should only point to `LineCoverageTest.scala` + a.foreach { l => + assert(l.lines.size == 1) + assert(l.lines.head._1 == "src/test/scala/chiseltest/coverage/circuits/Test1Module.scala") + assert(l.lines.head._2 == lines(l.target.ref).map(_ + offset)) + } + } + + it should "work with deduplicated submodules" in { + val (result, rAnnos) = compile(new Test1Module(withSubmodules = true), "low") + // println(result) + val l = result.split('\n').map(_.trim) + + // should only have two modules + assert(l.count(_.startsWith("module")) == 2) + + // line coverage annotations are on a per module basis thus we expect 4 + 1 annotations + val a = rAnnos.collect { case a: LineCoverageAnnotation => a } + assert(a.length == 4 + 1) + + // check the annotation of the submodule + val subAs = a.filterNot(_.target.module == "Test1Module") + assert(subAs.size == 1) + assert(subAs.head.lines.size == 1) + assert(subAs.head.lines.head._1 == "src/test/scala/chiseltest/coverage/circuits/Test1Module.scala") + val offset = 12 + assert(subAs.head.lines.head._2 == Seq(39).map(_ + offset)) + } + + it should "ignore modules when they are appropriately annotated" in { + val ignore = Seq(DoNotCoverAnnotation(CircuitTarget("Test1Module").module("Test1Module"))) + val (result, rAnnos) = compile(new Test1Module(withSubmodules = true), "low", ignore) + // println(result) + // val l = result.split('\n').map(_.trim) + + // we only expect the submodule to have a line coverage annotation + val a = rAnnos.collect { case a: LineCoverageAnnotation => a } + assert(a.length == 1) + assert(a.head.target.module == "SubModule1") + } +} diff --git a/src/test/scala/chiseltest/coverage/SimulatorCoverageTest.scala b/src/test/scala/chiseltest/coverage/SimulatorCoverageTest.scala index 2319d6587..329ca4719 100644 --- a/src/test/scala/chiseltest/coverage/SimulatorCoverageTest.scala +++ b/src/test/scala/chiseltest/coverage/SimulatorCoverageTest.scala @@ -1,4 +1,6 @@ -// SPDX-License-Identifier: Apache-2.0 +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer package chiseltest.coverage @@ -6,6 +8,7 @@ import chiseltest._ import firrtl2.AnnotationSeq import org.scalatest.flatspec.AnyFlatSpec import chisel3._ +import chiseltest.coverage.circuits.Test1Module import chiseltest.simulator.{DefaultTag, SimulatorAnnotation} import org.scalatest.Tag diff --git a/src/test/scala/chiseltest/coverage/ToggleCoverageTest.scala b/src/test/scala/chiseltest/coverage/ToggleCoverageTest.scala new file mode 100644 index 000000000..e72970531 --- /dev/null +++ b/src/test/scala/chiseltest/coverage/ToggleCoverageTest.scala @@ -0,0 +1,192 @@ +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer + +package chiseltest.coverage + +import chisel3._ +import chisel3.experimental.ExtModule +import chiseltest._ +import chiseltest.coverage.circuits.Test1Module +import firrtl2.AnnotationSeq +import firrtl2.annotations.{CircuitTarget, ReferenceTarget} +import firrtl2.options.Dependency +import firrtl2.stage.RunFirrtlTransformAnnotation +import org.scalatest.flatspec.AnyFlatSpec + +class ToggleTestModule extends Module { + val in = IO(Input(UInt(8.W))) + val out0 = IO(Output(UInt(8.W))) + val out1 = IO(Output(UInt(8.W))) + + val c0 = Module(new ToggleTestChild) + c0.in := in + out0 := c0.out0 + out1 := c0.out1 + val w_test = WireInit(in) + dontTouch(w_test) +} + +class ToggleTestChild extends Module { + val in = IO(Input(UInt(8.W))) + val out0 = IO(Output(UInt(8.W))) + val out1 = IO(Output(UInt(8.W))) + out0 := in + out1 := RegNext(in) + val g0 = Module(new ToggleTestGrandChild) + dontTouch(g0.reset) +} + +class ToggleTestGrandChild extends Module { + // empty, just has a reset +} + +class ToggleTestWithBottomUpReset extends RawModule { + val clock = IO(Input(Clock())) + val resetGen = Module(new ResetBlackbox) + val reset = resetGen.reset + withClockAndReset(clock, reset) { + val in = IO(Input(UInt(8.W))) + val out0 = IO(Output(UInt(8.W))) + val out1 = IO(Output(UInt(8.W))) + + val c0 = Module(new ToggleTestChild) + c0.in := in + out0 := c0.out0 + out1 := c0.out1 + val w_test = WireInit(in) + dontTouch(w_test) + } +} + +class ResetBlackbox extends ExtModule { + val reset = IO(Output(Bool())) +} + +class ToggleCoverageTest extends AnyFlatSpec with ChiselScalatestTester { + behavior.of("ToggleCoverage") + + it should "parse the results from the simulator" ignore { + val r = runTest() + + val data = ToggleCoverage.processCoverage(r) + assert(data.inst.length == 1 + 1 + 1) + + // there are three instances that have been covered + assert(data.inst.map(_._1._1).sorted == List("", "c0", "c0.g0")) + + // there are three modules that have been covered + assert( + data.inst.map(_._1._2).distinct.sorted == + List("ToggleTestChild", "ToggleTestGrandChild", "ToggleTestModule") + ) + } + + private def runTest(): AnnotationSeq = { + val r = test(new ToggleTestModule()).withAnnotations(WriteVcdAnnotation +: ToggleCoverage.all) { dut => + // stepping without togelling should not change anything + (0 until 4).foreach { _ => dut.clock.step() } + + // we toggle some select bits + val bits = Seq(0, 3, 5, 7) + + bits.foreach { b => + dut.in.poke((BigInt(1) << b).U) + dut.clock.step() + } + } + r.getAnnotationSeq + } +} + +class ToggleCoverageInstrumentationTest extends AnyFlatSpec with CompilerTest { + behavior.of("ToggleCoverage Instrumentation") + + override protected def annos = Seq(RunFirrtlTransformAnnotation(Dependency(ToggleCoveragePass))) + + it should "add cover statements" in { + val (result, rAnnos) = compile(new Test1Module(), "sverilog") + // println(result) + val l = result.split('\n').map(_.trim) + } + + it should "only create one counter when there are obvious aliases" in { + val (result, rAnnos) = compile(new ToggleTestModule(), "low", a = ToggleCoverage.all) + // println(result) + val l = result.split('\n').map(_.trim) + + val annos = rAnnos.collect { case a: ToggleCoverageAnnotation => a } + + // we expect the covered signals to be the following + val expected = List( + // all signals in the ToggleTestChild module + "ToggleTestChild.g0.reset", + "ToggleTestChild.in", + "ToggleTestChild.out0", + "ToggleTestChild.out1", + "ToggleTestChild.out1_REG", + "ToggleTestChild.reset", + // all signals in the ToggleTestGrandChild module + "ToggleTestGrandChild.reset", + // all signals in the ToggleTestModule module + "ToggleTestModule.c0.in", + "ToggleTestModule.c0.out0", + "ToggleTestModule.c0.out1", + "ToggleTestModule.c0.reset", + "ToggleTestModule.in", + "ToggleTestModule.out0", + "ToggleTestModule.out1", + "ToggleTestModule.reset", + "ToggleTestModule.w_test" + ) + + val coverNames = annos.flatMap { a => a.signals.map(refToString) }.distinct.sorted + assert(coverNames == expected) + + // Check how many how many cover statements there are + val covers = l.filter(_.startsWith("cover(")) + val coverCount = covers.length + + // We expect there to be fewer actual cover statement than signals covered. + // The following signals alias: + // - ToggleTestChild.REG -> ToggleTestChild.out1 -> ToggleTestModule.out1 + // - ToggleTestModule.in -> ToggleTestChild.in -> ToggleTestChild.out0 -> ToggleTestModule.out0 + // - ToggleTestModule.reset -> ToggleTestChild.reset + // Thus we expect the following number of cover statements: + val expectedCoverBits = 8 + 8 + 1 + assert(coverCount == expectedCoverBits, "\n" + covers.mkString("\n")) + + // We expect there to be only a single `reg enToggle` because there should be + // no cover statements in the child module since all signals are exposed on the IOs. + val enToggleLines = l.filter(_.contains("reg enToggle")) + assert(enToggleLines.length == 1, enToggleLines.mkString("\n")) + } + + it should "work, even if the toplevel module is ignored" in { + val ignored = DoNotCoverAnnotation(CircuitTarget("ToggleTestModule").module("ToggleTestModule")) + val (result, _) = compile(new ToggleTestModule(), "low", a = ignored +: ToggleCoverage.all) + // println(result) + val l = result.split('\n').map(_.trim) + + // we still expect there to be exactly 17 cover statements since the toplevel is purely a pass-through module + val covers = l.filter(_.startsWith("cover(")) + val coverCount = covers.length + val expectedCoverBits = 8 + 8 + 1 + assert(coverCount == expectedCoverBits, "\n" + covers.mkString("\n")) + } + + it should "work, even with a reset that is generated by an ext module" in { + val (result, _) = compile(new ToggleTestWithBottomUpReset(), "low", a = ToggleCoverage.all) + // println(result) + val l = result.split('\n').map(_.trim) + + // we still expect there to be exactly 17 cover statements + val covers = l.filter(_.startsWith("cover(")) + val coverCount = covers.length + val expectedCoverBits = 8 + 8 + 1 + assert(coverCount == expectedCoverBits, "\n" + covers.mkString("\n")) + } + + private def refToString(r: ReferenceTarget): String = + r.toString().split('|').last.replace('>', '.') +} diff --git a/src/test/scala/chiseltest/coverage/circuits/FifoRegister.scala b/src/test/scala/chiseltest/coverage/circuits/FifoRegister.scala new file mode 100644 index 000000000..9845ef1ec --- /dev/null +++ b/src/test/scala/chiseltest/coverage/circuits/FifoRegister.scala @@ -0,0 +1,53 @@ +/* + * Copyright: 2014, Technical University of Denmark, DTU Compute + * Author: Martin Schoeberl (martin@jopdesign.com) + * License: Simplified BSD License + * + * Play with FIFO buffers. + * + * This code is a copy from the chisel-examples repo for easier + * inclusion in the Chisel book. + * + * Modified by Kevin Laeufer. + * + */ + +package chiseltest.coverage.circuits + +import chisel3._ +import chisel3.util._ + +object FifoState extends ChiselEnum { + val Empty, Full = Value +} + +/** A single register (=stage) to build the FIFO. + */ +//- start bubble_fifo_register +class FifoRegister(size: Int) extends Module { + val io = IO(new Bundle { + val enq = Flipped(Decoupled(UInt(size.W))) + val deq = Decoupled(UInt(size.W)) + }) + + val stateReg = RegInit(FifoState.Empty) + val dataReg = RegInit(0.U(size.W)) + + when(stateReg === FifoState.Empty) { + when(io.enq.fire) { + stateReg := FifoState.Full + dataReg := io.enq.bits + } + }.elsewhen(stateReg === FifoState.Full) { + when(io.deq.fire) { + stateReg := FifoState.Empty + dataReg := 0.U // just to better see empty slots in the waveform + } + }.otherwise { + // There should not be an otherwise state + } + + io.enq.ready := (stateReg === FifoState.Empty) + io.deq.valid := (stateReg === FifoState.Full) + io.deq.bits := dataReg +} diff --git a/src/test/scala/chiseltest/coverage/Test1Module.scala b/src/test/scala/chiseltest/coverage/circuits/Test1Module.scala similarity index 84% rename from src/test/scala/chiseltest/coverage/Test1Module.scala rename to src/test/scala/chiseltest/coverage/circuits/Test1Module.scala index f7e7509c2..8fee77910 100644 --- a/src/test/scala/chiseltest/coverage/Test1Module.scala +++ b/src/test/scala/chiseltest/coverage/circuits/Test1Module.scala @@ -1,6 +1,8 @@ -// SPDX-License-Identifier: Apache-2.0 +// Copyright 2021-2023 The Regents of the University of California +// released under BSD 3-Clause License +// author: Kevin Laeufer -package chiseltest.coverage +package chiseltest.coverage.circuits // NOTE: This module is contained in its own file in order to prevent any line numbers from changing. // It is used (among other things) for testing our automatic line coverage pass which