From d374d00d9f783926d7807750848f3be3375a9c59 Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Sat, 25 Nov 2023 09:08:03 +0100 Subject: [PATCH 1/7] add TryFrom for BranchOffset16 --- crates/wasmi/src/engine/regmach/bytecode/utils.rs | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/crates/wasmi/src/engine/regmach/bytecode/utils.rs b/crates/wasmi/src/engine/regmach/bytecode/utils.rs index 147a6e09bd..dcf12e401f 100644 --- a/crates/wasmi/src/engine/regmach/bytecode/utils.rs +++ b/crates/wasmi/src/engine/regmach/bytecode/utils.rs @@ -491,6 +491,17 @@ impl From for BranchOffset16 { } } +impl TryFrom for BranchOffset16 { + type Error = TranslationError; + + fn try_from(offset: BranchOffset) -> Result { + let Ok(offset16) = i16::try_from(offset.to_i32()) else { + return Err(TranslationError::new(TranslationErrorInner::BranchOffsetOutOfBounds)) + }; + Ok(Self(offset16)) + } +} + impl BranchOffset16 { /// Creates a 16-bit [`BranchOffset16`] from a 32-bit [`BranchOffset`] if possible. pub fn new(offset: BranchOffset) -> Option { From a5432b0a93f9e4a58671c018247eddc4ab6941f1 Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Sat, 25 Nov 2023 09:08:09 +0100 Subject: [PATCH 2/7] move From impl --- crates/wasmi/src/engine/regmach/bytecode/utils.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/crates/wasmi/src/engine/regmach/bytecode/utils.rs b/crates/wasmi/src/engine/regmach/bytecode/utils.rs index dcf12e401f..1dfd5095ad 100644 --- a/crates/wasmi/src/engine/regmach/bytecode/utils.rs +++ b/crates/wasmi/src/engine/regmach/bytecode/utils.rs @@ -502,6 +502,12 @@ impl TryFrom for BranchOffset16 { } } +impl From for BranchOffset { + fn from(offset: BranchOffset16) -> Self { + Self::from(i32::from(offset.to_i16())) + } +} + impl BranchOffset16 { /// Creates a 16-bit [`BranchOffset16`] from a 32-bit [`BranchOffset`] if possible. pub fn new(offset: BranchOffset) -> Option { @@ -538,12 +544,6 @@ impl BranchOffset16 { } } -impl From for BranchOffset { - fn from(offset: BranchOffset16) -> Self { - Self::from(i32::from(offset.to_i16())) - } -} - /// A generic fused comparison and conditional branch [`Instruction`]. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub struct BranchBinOpInstr { From 2b9ff82afbd6cbbf44284a2a674edb98baa51105 Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Sat, 25 Nov 2023 09:19:28 +0100 Subject: [PATCH 3/7] remove superseeded branch+cmp instructions --- .../src/engine/regmach/bytecode/construct.rs | 28 +++++------ .../wasmi/src/engine/regmach/bytecode/mod.rs | 45 ------------------ .../src/engine/regmach/bytecode/utils.rs | 4 +- .../src/engine/regmach/executor/instrs.rs | 12 ----- .../engine/regmach/executor/instrs/branch.rs | 36 --------------- .../src/engine/regmach/tests/op/block.rs | 6 +-- .../src/engine/regmach/tests/op/br_if.rs | 16 +++---- .../src/engine/regmach/tests/op/cmp_br.rs | 8 ++-- .../wasmi/src/engine/regmach/tests/op/if_.rs | 34 +++++++------- .../regmach/translator/instr_encoder.rs | 46 +++++++++---------- .../regmach/translator/relink_result.rs | 4 -- .../regmach/translator/visit_register.rs | 4 -- 12 files changed, 72 insertions(+), 171 deletions(-) diff --git a/crates/wasmi/src/engine/regmach/bytecode/construct.rs b/crates/wasmi/src/engine/regmach/bytecode/construct.rs index 03b0479e2c..230fefaa6c 100644 --- a/crates/wasmi/src/engine/regmach/bytecode/construct.rs +++ b/crates/wasmi/src/engine/regmach/bytecode/construct.rs @@ -224,8 +224,8 @@ macro_rules! constructor_for_branch_binop_imm { impl Instruction { $( #[doc = concat!("Creates a new [`Instruction::", stringify!($op_code), "`].")] - pub fn $name(lhs: Register, rhs: Const16<$ty>, offset: BranchOffset16) -> Self { - Self::$op_code(BranchBinOpInstrImm16::new(lhs, rhs, offset)) + pub fn $name(lhs: Register, rhs: impl Into>, offset: BranchOffset16) -> Self { + Self::$op_code(BranchBinOpInstrImm16::new(lhs, rhs.into(), offset)) } )* } @@ -412,24 +412,24 @@ impl Instruction { Self::Branch { offset } } - /// Creates a new [`Instruction::BranchI32Eqz`] for the given `condition` and `offset`. - pub fn branch_i32_eqz(condition: Register, offset: BranchOffset) -> Self { - Self::BranchI32Eqz { condition, offset } + /// Convenience constructor to create a new [`Instruction::BranchI32Eqz`] with a zero immediate value. + pub fn branch_i32_eqz(condition: Register, offset: BranchOffset16) -> Self { + Self::branch_i32_eq_imm(condition, 0_i16, offset) } - /// Creates a new [`Instruction::BranchI32Nez`] for the given `condition` and `offset`. - pub fn branch_i32_nez(condition: Register, offset: BranchOffset) -> Self { - Self::BranchI32Nez { condition, offset } + /// Convenience constructor to create a new [`Instruction::BranchI32Nez`] with a zero immediate value. + pub fn branch_i32_nez(condition: Register, offset: BranchOffset16) -> Self { + Self::branch_i32_ne_imm(condition, 0_i16, offset) } - /// Creates a new [`Instruction::BranchI64Eqz`] for the given `condition` and `offset`. - pub fn branch_i64_eqz(condition: Register, offset: BranchOffset) -> Self { - Self::BranchI64Eqz { condition, offset } + /// Convenience constructor to create a new [`Instruction::BranchI64Eqz`] with a zero immediate value. + pub fn branch_i64_eqz(condition: Register, offset: BranchOffset16) -> Self { + Self::branch_i64_eq_imm(condition, 0_i16, offset) } - /// Creates a new [`Instruction::BranchI64Nez`] for the given `condition` and `offset`. - pub fn branch_i64_nez(condition: Register, offset: BranchOffset) -> Self { - Self::BranchI64Nez { condition, offset } + /// Convenience constructor to create a new [`Instruction::BranchI64Nez`] with a zero immediate value. + pub fn branch_i64_nez(condition: Register, offset: BranchOffset16) -> Self { + Self::branch_i64_ne_imm(condition, 0_i16, offset) } /// Creates a new [`Instruction::BranchTable`] for the given `index` and `len_targets`. diff --git a/crates/wasmi/src/engine/regmach/bytecode/mod.rs b/crates/wasmi/src/engine/regmach/bytecode/mod.rs index 11f4fc7ec8..cf9a414760 100644 --- a/crates/wasmi/src/engine/regmach/bytecode/mod.rs +++ b/crates/wasmi/src/engine/regmach/bytecode/mod.rs @@ -367,51 +367,6 @@ pub enum Instruction { /// The branching offset for the instruction pointer. offset: BranchOffset, }, - /// A conditional branch instruction. - /// - /// # Note - /// - /// - The branch is taken if `condition` evaluates to zero. - /// - Partially translated from negated Wasm `br_if` instructions. - BranchI32Eqz { - /// The register holding the condition to evaluate against zero. - condition: Register, - /// The branching offset for the instruction pointer. - offset: BranchOffset, - }, - /// A Wasm `br_if` instruction. - /// - /// # Note - /// - /// The branch is taken if `condition` evaluates to zero. - BranchI32Nez { - /// The register holding the condition to evaluate against zero. - condition: Register, - /// The branching offset for the instruction pointer. - offset: BranchOffset, - }, - /// A fused Wasm `i64.eqz` + `if` instruction. - /// - /// # Note - /// - /// - The branch is taken if `condition` evaluates to zero. - BranchI64Eqz { - /// The register holding the condition to evaluate against zero. - condition: Register, - /// The branching offset for the instruction pointer. - offset: BranchOffset, - }, - /// A fused Wasm `i64.eqz` + `br_if` instruction. - /// - /// # Note - /// - /// The branch is taken if `condition` evaluates to zero. - BranchI64Nez { - /// The register holding the condition to evaluate against zero. - condition: Register, - /// The branching offset for the instruction pointer. - offset: BranchOffset, - }, /// A fused [`Instruction::I32And`] and [`Instruction::BranchI32Nez`] instruction. BranchI32And(BranchBinOpInstr), diff --git a/crates/wasmi/src/engine/regmach/bytecode/utils.rs b/crates/wasmi/src/engine/regmach/bytecode/utils.rs index 1dfd5095ad..faac2be3bf 100644 --- a/crates/wasmi/src/engine/regmach/bytecode/utils.rs +++ b/crates/wasmi/src/engine/regmach/bytecode/utils.rs @@ -496,7 +496,9 @@ impl TryFrom for BranchOffset16 { fn try_from(offset: BranchOffset) -> Result { let Ok(offset16) = i16::try_from(offset.to_i32()) else { - return Err(TranslationError::new(TranslationErrorInner::BranchOffsetOutOfBounds)) + return Err(TranslationError::new( + TranslationErrorInner::BranchOffsetOutOfBounds, + )); }; Ok(Self(offset16)) } diff --git a/crates/wasmi/src/engine/regmach/executor/instrs.rs b/crates/wasmi/src/engine/regmach/executor/instrs.rs index ec40a71e7a..b851abee36 100644 --- a/crates/wasmi/src/engine/regmach/executor/instrs.rs +++ b/crates/wasmi/src/engine/regmach/executor/instrs.rs @@ -245,18 +245,6 @@ impl<'ctx, 'engine> Executor<'ctx, 'engine> { forward_return!(self.execute_return_nez_many(condition, values)) } Instr::Branch { offset } => self.execute_branch(offset), - Instr::BranchI32Eqz { condition, offset } => { - self.execute_branch_i32_eqz(condition, offset) - } - Instr::BranchI32Nez { condition, offset } => { - self.execute_branch_i32_nez(condition, offset) - } - Instr::BranchI64Eqz { condition, offset } => { - self.execute_branch_i64_eqz(condition, offset) - } - Instr::BranchI64Nez { condition, offset } => { - self.execute_branch_i64_nez(condition, offset) - } Instr::BranchTable { index, len_targets } => { self.execute_branch_table(index, len_targets) } diff --git a/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs b/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs index 3b4721e269..a5b5e1a167 100644 --- a/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs +++ b/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs @@ -15,42 +15,6 @@ impl<'ctx, 'engine> Executor<'ctx, 'engine> { self.branch_to(offset) } - #[inline(always)] - pub fn execute_branch_i32_nez(&mut self, condition: Register, offset: BranchOffset) { - let value: i32 = self.get_register_as(condition); - if value != 0 { - return self.branch_to(offset); - } - self.next_instr(); - } - - #[inline(always)] - pub fn execute_branch_i32_eqz(&mut self, condition: Register, offset: BranchOffset) { - let value: i32 = self.get_register_as(condition); - if value == 0 { - return self.branch_to(offset); - } - self.next_instr(); - } - - #[inline(always)] - pub fn execute_branch_i64_nez(&mut self, condition: Register, offset: BranchOffset) { - let value: i64 = self.get_register_as(condition); - if value != 0 { - return self.branch_to(offset); - } - self.next_instr(); - } - - #[inline(always)] - pub fn execute_branch_i64_eqz(&mut self, condition: Register, offset: BranchOffset) { - let value: i64 = self.get_register_as(condition); - if value == 0 { - return self.branch_to(offset); - } - self.next_instr(); - } - #[inline(always)] pub fn execute_branch_table(&mut self, index: Register, len_targets: Const32) { let index: u32 = self.get_register_as(index); diff --git a/crates/wasmi/src/engine/regmach/tests/op/block.rs b/crates/wasmi/src/engine/regmach/tests/op/block.rs index 5b89a53d39..ad31e450ed 100644 --- a/crates/wasmi/src/engine/regmach/tests/op/block.rs +++ b/crates/wasmi/src/engine/regmach/tests/op/block.rs @@ -2,7 +2,7 @@ use super::*; use crate::engine::{ bytecode::BranchOffset, regmach::{ - bytecode::RegisterSpan, + bytecode::{BranchOffset16, RegisterSpan}, tests::{display_wasm::DisplayValueType, wasm_type::WasmType}, }, }; @@ -346,7 +346,7 @@ fn branch_if_block_0() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset::from(1)), + Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset16::from(1)), Instruction::Return, ]) .run() @@ -369,7 +369,7 @@ fn branch_if_block_1() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset::from(3)), + Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset16::from(3)), Instruction::copy(Register::from_i16(2), Register::from_i16(0)), Instruction::branch(BranchOffset::from(2)), Instruction::copy(Register::from_i16(2), Register::from_i16(0)), diff --git a/crates/wasmi/src/engine/regmach/tests/op/br_if.rs b/crates/wasmi/src/engine/regmach/tests/op/br_if.rs index e4259c8c08..87f2637889 100644 --- a/crates/wasmi/src/engine/regmach/tests/op/br_if.rs +++ b/crates/wasmi/src/engine/regmach/tests/op/br_if.rs @@ -2,7 +2,7 @@ use super::*; use crate::engine::{ bytecode::BranchOffset, regmach::{ - bytecode::RegisterSpan, + bytecode::{BranchOffset16, RegisterSpan}, tests::{display_wasm::DisplayValueType, driver::ExpectedFunc, wasm_type::WasmType}, }, }; @@ -844,7 +844,7 @@ fn branch_if_results_0() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset::from(1)), + Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset16::from(1)), Instruction::Return, ]) .run() @@ -867,7 +867,7 @@ fn branch_if_results_1() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset::from(3)), + Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset16::from(3)), Instruction::copy(Register::from_i16(2), Register::from_i16(0)), Instruction::branch(BranchOffset::from(2)), Instruction::copy(Register::from_i16(2), Register::from_i16(0)), @@ -902,7 +902,7 @@ fn branch_if_results_1_avoid_copy() { .expect_func_instrs([ Instruction::i32_clz(Register::from_i16(2), Register::from_i16(0)), Instruction::i32_ctz(Register::from_i16(3), Register::from_i16(1)), - Instruction::branch_i32_nez(Register::from_i16(3), BranchOffset::from(1)), + Instruction::branch_i32_nez(Register::from_i16(3), BranchOffset16::from(1)), Instruction::return_reg(Register::from_i16(2)), ]) .run() @@ -927,7 +927,7 @@ fn branch_if_results_2() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(2), BranchOffset::from(3)), + Instruction::branch_i32_eqz(Register::from_i16(2), BranchOffset16::from(3)), Instruction::copy2(RegisterSpan::new(Register::from_i16(3)), 0, 1), Instruction::branch(BranchOffset::from(2)), Instruction::copy2(RegisterSpan::new(Register::from_i16(3)), 0, 1), @@ -968,7 +968,7 @@ fn branch_if_results_2_avoid_copy() { .expect_func_instrs([ Instruction::i32_clz(Register::from_i16(3), Register::from_i16(0)), Instruction::i32_ctz(Register::from_i16(4), Register::from_i16(1)), - Instruction::branch_i32_nez(Register::from_i16(2), BranchOffset::from(1)), + Instruction::branch_i32_nez(Register::from_i16(2), BranchOffset16::from(1)), Instruction::i32_add( Register::from_i16(3), Register::from_i16(3), @@ -1002,7 +1002,7 @@ fn branch_if_results_4_mixed_1() { TranslationTest::new(wasm) .expect_func( ExpectedFunc::new([ - Instruction::branch_i32_eqz(Register::from_i16(2), BranchOffset::from(4)), + Instruction::branch_i32_eqz(Register::from_i16(2), BranchOffset16::from(4)), Instruction::copy_many_non_overlapping( RegisterSpan::new(Register::from_i16(3)), -1, @@ -1045,7 +1045,7 @@ fn branch_if_results_4_mixed_2() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(2), BranchOffset::from(4)), + Instruction::branch_i32_eqz(Register::from_i16(2), BranchOffset16::from(4)), Instruction::copy_many_non_overlapping(RegisterSpan::new(Register::from_i16(3)), 0, 0), Instruction::register2(1, 1), Instruction::branch(BranchOffset::from(3)), diff --git a/crates/wasmi/src/engine/regmach/tests/op/cmp_br.rs b/crates/wasmi/src/engine/regmach/tests/op/cmp_br.rs index 6a628bc9c7..c42ea2e25e 100644 --- a/crates/wasmi/src/engine/regmach/tests/op/cmp_br.rs +++ b/crates/wasmi/src/engine/regmach/tests/op/cmp_br.rs @@ -150,7 +150,7 @@ fn loop_backward_imm() { #[test] #[cfg_attr(miri, ignore)] fn loop_backward_imm_eqz() { - fn test_for(op: &str, expect_instr: fn(Register, BranchOffset) -> Instruction) { + fn test_for(op: &str, expect_instr: fn(Register, BranchOffset16) -> Instruction) { let wasm = wat2wasm(&format!( r" (module @@ -166,7 +166,7 @@ fn loop_backward_imm_eqz() { )); TranslationTest::new(wasm) .expect_func_instrs([ - expect_instr(Register::from_i16(0), BranchOffset::from(0_i32)), + expect_instr(Register::from_i16(0), BranchOffset16::from(0_i16)), Instruction::Return, ]) .run() @@ -539,7 +539,7 @@ fn block_i64_eqz_fuse() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i64_eqz(Register::from_i16(0), BranchOffset::from(1)), + Instruction::branch_i64_eqz(Register::from_i16(0), BranchOffset16::from(1)), Instruction::Return, ]) .run() @@ -561,7 +561,7 @@ fn if_i64_eqz_fuse() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i64_nez(Register::from_i16(0), BranchOffset::from(1)), + Instruction::branch_i64_nez(Register::from_i16(0), BranchOffset16::from(1)), Instruction::Return, ]) .run() diff --git a/crates/wasmi/src/engine/regmach/tests/op/if_.rs b/crates/wasmi/src/engine/regmach/tests/op/if_.rs index 3f496ad747..cfb79aca9d 100644 --- a/crates/wasmi/src/engine/regmach/tests/op/if_.rs +++ b/crates/wasmi/src/engine/regmach/tests/op/if_.rs @@ -1,7 +1,7 @@ use super::*; use crate::engine::{ bytecode::{BranchOffset, GlobalIdx}, - regmach::bytecode::RegisterSpan, + regmach::bytecode::{BranchOffset16, RegisterSpan}, CompiledFunc, }; use wasmi_core::{TrapCode, UntypedValue}; @@ -21,7 +21,7 @@ fn simple_if_then() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(1)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(1)), Instruction::Return, ]) .run() @@ -46,8 +46,8 @@ fn simple_if_then_nested() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(2)), - Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset::from(1)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset16::from(1)), Instruction::Return, ]) .run() @@ -72,7 +72,7 @@ fn if_then_global_set() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(2)), Instruction::global_set(GlobalIdx::from(0), Register::from_i16(1)), Instruction::return_imm32(AnyConst32::from(10_i32)), ]) @@ -102,7 +102,7 @@ fn if_then_return() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(3)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(3)), Instruction::i32_add( Register::from_i16(3), Register::from_i16(1), @@ -135,7 +135,7 @@ fn if_then_else_return() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(2)), Instruction::return_imm32(AnyConst32::from(10_i32)), Instruction::return_imm32(AnyConst32::from(20_i32)), ]) @@ -163,7 +163,7 @@ fn if_then_br_else() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(2)), Instruction::branch(BranchOffset::from(2)), Instruction::return_imm32(AnyConst32::from(10_i32)), Instruction::return_imm32(AnyConst32::from(20_i32)), @@ -192,7 +192,7 @@ fn if_then_else_br() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(2)), Instruction::return_imm32(AnyConst32::from(10_i32)), Instruction::branch(BranchOffset::from(1)), Instruction::return_imm32(AnyConst32::from(20_i32)), @@ -218,7 +218,7 @@ fn simple_if_then_else() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(2)), Instruction::branch(BranchOffset::from(1)), Instruction::Return, ]) @@ -251,11 +251,11 @@ fn simple_if_then_else_nested() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(4)), - Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(4)), + Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset16::from(2)), Instruction::branch(BranchOffset::from(1)), Instruction::branch(BranchOffset::from(3)), - Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset::from(2)), + Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset16::from(2)), Instruction::branch(BranchOffset::from(1)), Instruction::Return, ]) @@ -280,7 +280,7 @@ fn if_then_else_with_params() { ); TranslationTest::new(wasm) .expect_func_instrs([ - Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset::from(3)), + Instruction::branch_i32_eqz(Register::from_i16(0), BranchOffset16::from(3)), Instruction::i32_add( Register::from_i16(3), Register::from_i16(1), @@ -445,7 +445,7 @@ fn const_condition_br_if_then() { test_for( false, [ - Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset::from(2)), + Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset16::from(2)), Instruction::Trap(TrapCode::UnreachableCodeReached), Instruction::return_imm32(AnyConst32::from(1_i32)), ], @@ -484,7 +484,7 @@ fn const_condition_br_if_else() { test_for( true, [ - Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset::from(2)), + Instruction::branch_i32_nez(Register::from_i16(0), BranchOffset16::from(2)), Instruction::Trap(TrapCode::UnreachableCodeReached), Instruction::return_imm32(AnyConst32::from(1_i32)), ], @@ -569,7 +569,7 @@ fn test_if_without_else_has_result() { RegisterSpan::new(Register::from_i16(0)), CompiledFunc::from_u32(0), ), - Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset::from(3)), + Instruction::branch_i32_eqz(Register::from_i16(1), BranchOffset16::from(3)), Instruction::copy_i64imm32(Register::from_i16(0), -1), Instruction::branch(BranchOffset::from(1)), Instruction::return_reg(Register::from_i16(0)), diff --git a/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs b/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs index 7d07d5f319..fe04047fc6 100644 --- a/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs +++ b/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs @@ -842,7 +842,9 @@ impl InstrEncoder { condition: Register, label: LabelRef, ) -> Result<(), TranslationError> { - let offset = this.try_resolve_label(label)?; + let offset = this + .try_resolve_label(label) + .and_then(BranchOffset16::try_from)?; this.push_instr(Instruction::branch_i32_eqz(condition, offset))?; Ok(()) } @@ -904,8 +906,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i32_nez(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i32_nez(instr.reg_in, offset16)) } } } @@ -913,8 +915,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i64_nez(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i64_nez(instr.reg_in, offset16)) } } } @@ -922,8 +924,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i32_eqz(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i32_eqz(instr.reg_in, offset16)) } } } @@ -931,8 +933,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i64_eqz(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i64_eqz(instr.reg_in, offset16)) } } } @@ -1018,7 +1020,9 @@ impl InstrEncoder { condition: Register, label: LabelRef, ) -> Result<(), TranslationError> { - let offset = this.try_resolve_label(label)?; + let offset = this + .try_resolve_label(label) + .and_then(BranchOffset16::try_from)?; this.push_instr(Instruction::branch_i32_nez(condition, offset))?; Ok(()) } @@ -1080,8 +1084,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i32_eqz(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i32_eqz(instr.reg_in, offset16)) } } } @@ -1089,8 +1093,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i64_eqz(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i64_eqz(instr.reg_in, offset16)) } } } @@ -1098,8 +1102,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i32_nez(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i32_nez(instr.reg_in, offset16)) } } } @@ -1107,8 +1111,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset32 = self.try_resolve_label_for(label, last_instr)?; - Some(Instruction::branch_i64_nez(instr.reg_in, offset32)) + let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + Some(Instruction::branch_i64_nez(instr.reg_in, offset16)) } } } @@ -1197,11 +1201,7 @@ impl Instruction { new_offset: BranchOffset, ) -> Result<(), TranslationError> { match self { - Instruction::Branch { offset } - | Instruction::BranchI32Eqz { offset, .. } - | Instruction::BranchI32Nez { offset, .. } - | Instruction::BranchI64Eqz { offset, .. } - | Instruction::BranchI64Nez { offset, .. } => { + Instruction::Branch { offset } => { offset.init(new_offset); Ok(()) } diff --git a/crates/wasmi/src/engine/regmach/translator/relink_result.rs b/crates/wasmi/src/engine/regmach/translator/relink_result.rs index aad1686255..77fd8e7c3b 100644 --- a/crates/wasmi/src/engine/regmach/translator/relink_result.rs +++ b/crates/wasmi/src/engine/regmach/translator/relink_result.rs @@ -75,10 +75,6 @@ impl Instruction { | I::BranchI32OrEqzImm(_) | I::BranchI32XorEqz(_) | I::BranchI32XorEqzImm(_) - | I::BranchI32Eqz { .. } - | I::BranchI32Nez { .. } - | I::BranchI64Eqz { .. } - | I::BranchI64Nez { .. } | I::BranchTable { .. } | I::BranchI32Eq(_) | I::BranchI32EqImm(_) diff --git a/crates/wasmi/src/engine/regmach/translator/visit_register.rs b/crates/wasmi/src/engine/regmach/translator/visit_register.rs index eb4836bac7..fab832522b 100644 --- a/crates/wasmi/src/engine/regmach/translator/visit_register.rs +++ b/crates/wasmi/src/engine/regmach/translator/visit_register.rs @@ -78,10 +78,6 @@ impl VisitInputRegisters for Instruction { values.visit_input_registers(f); } Instruction::Branch { .. } => {}, - Instruction::BranchI32Eqz { condition, .. } | - Instruction::BranchI32Nez { condition, .. } | - Instruction::BranchI64Eqz { condition, .. } | - Instruction::BranchI64Nez { condition, .. } => f(condition), Instruction::BranchTable { index, .. } => f(index), Instruction::BranchI32And(instr) => instr.visit_input_registers(f), From 423e302f47b4ccea468b9975dacff7b1ce818c8b Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Sat, 25 Nov 2023 09:33:00 +0100 Subject: [PATCH 4/7] fix intra doc links --- .../src/engine/regmach/bytecode/construct.rs | 8 +- .../wasmi/src/engine/regmach/bytecode/mod.rs | 128 +++++++++--------- 2 files changed, 68 insertions(+), 68 deletions(-) diff --git a/crates/wasmi/src/engine/regmach/bytecode/construct.rs b/crates/wasmi/src/engine/regmach/bytecode/construct.rs index 230fefaa6c..308a94bd6d 100644 --- a/crates/wasmi/src/engine/regmach/bytecode/construct.rs +++ b/crates/wasmi/src/engine/regmach/bytecode/construct.rs @@ -412,22 +412,22 @@ impl Instruction { Self::Branch { offset } } - /// Convenience constructor to create a new [`Instruction::BranchI32Eqz`] with a zero immediate value. + /// Convenience constructor to create a new [`Instruction::BranchI32EqImm`] with a zero immediate value. pub fn branch_i32_eqz(condition: Register, offset: BranchOffset16) -> Self { Self::branch_i32_eq_imm(condition, 0_i16, offset) } - /// Convenience constructor to create a new [`Instruction::BranchI32Nez`] with a zero immediate value. + /// Convenience constructor to create a new [`Instruction::BranchI32NeImm`] with a zero immediate value. pub fn branch_i32_nez(condition: Register, offset: BranchOffset16) -> Self { Self::branch_i32_ne_imm(condition, 0_i16, offset) } - /// Convenience constructor to create a new [`Instruction::BranchI64Eqz`] with a zero immediate value. + /// Convenience constructor to create a new [`Instruction::BranchI64EqImm`] with a zero immediate value. pub fn branch_i64_eqz(condition: Register, offset: BranchOffset16) -> Self { Self::branch_i64_eq_imm(condition, 0_i16, offset) } - /// Convenience constructor to create a new [`Instruction::BranchI64Nez`] with a zero immediate value. + /// Convenience constructor to create a new [`Instruction::BranchI64NeImm`] with a zero immediate value. pub fn branch_i64_nez(condition: Register, offset: BranchOffset16) -> Self { Self::branch_i64_ne_imm(condition, 0_i16, offset) } diff --git a/crates/wasmi/src/engine/regmach/bytecode/mod.rs b/crates/wasmi/src/engine/regmach/bytecode/mod.rs index cf9a414760..d12ff66cba 100644 --- a/crates/wasmi/src/engine/regmach/bytecode/mod.rs +++ b/crates/wasmi/src/engine/regmach/bytecode/mod.rs @@ -368,246 +368,246 @@ pub enum Instruction { offset: BranchOffset, }, - /// A fused [`Instruction::I32And`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32And`] and Wasm branch instruction. BranchI32And(BranchBinOpInstr), - /// A fused [`Instruction::I32And`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32And`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32And`] with 16-bit encoded constant `rhs`. BranchI32AndImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32Or`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Or`] and Wasm branch instruction. BranchI32Or(BranchBinOpInstr), - /// A fused [`Instruction::I32Or`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Or`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32Or`] with 16-bit encoded constant `rhs`. BranchI32OrImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32Xor`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Xor`] and Wasm branch instruction. BranchI32Xor(BranchBinOpInstr), - /// A fused [`Instruction::I32Xor`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Xor`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32Xor`] with 16-bit encoded constant `rhs`. BranchI32XorImm(BranchBinOpInstrImm16), - /// A fused not-[`Instruction::I32And`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused not-[`Instruction::I32And`] and Wasm branch instruction. BranchI32AndEqz(BranchBinOpInstr), - /// A fused not-[`Instruction::I32And`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused not-[`Instruction::I32And`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32AndEqz`] with 16-bit encoded constant `rhs`. BranchI32AndEqzImm(BranchBinOpInstrImm16), - /// A fused not-[`Instruction::I32Or`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused not-[`Instruction::I32Or`] and Wasm branch instruction. BranchI32OrEqz(BranchBinOpInstr), - /// A fused not-[`Instruction::I32Or`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused not-[`Instruction::I32Or`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32OrEqz`] with 16-bit encoded constant `rhs`. BranchI32OrEqzImm(BranchBinOpInstrImm16), - /// A fused not-[`Instruction::I32Xor`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused not-[`Instruction::I32Xor`] and Wasm branch instruction. BranchI32XorEqz(BranchBinOpInstr), - /// A fused not-[`Instruction::I32Xor`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused not-[`Instruction::I32Xor`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32XorEqz`] with 16-bit encoded constant `rhs`. BranchI32XorEqzImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32Eq`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Eq`] and Wasm branch instruction. BranchI32Eq(BranchBinOpInstr), - /// A fused [`Instruction::I32Eq`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Eq`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32Eq`] with 16-bit encoded constant `rhs`. BranchI32EqImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32Ne`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Ne`] and Wasm branch instruction. BranchI32Ne(BranchBinOpInstr), - /// A fused [`Instruction::I32Ne`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32Ne`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32Ne`] with 16-bit encoded constant `rhs`. BranchI32NeImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32LtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LtS`] and Wasm branch instruction. BranchI32LtS(BranchBinOpInstr), - /// A fused [`Instruction::I32LtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LtS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32LtS`] with 16-bit encoded constant `rhs`. BranchI32LtSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32LtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LtU`] and Wasm branch instruction. BranchI32LtU(BranchBinOpInstr), - /// A fused [`Instruction::I32LtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LtU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32LtU`] with 16-bit encoded constant `rhs`. BranchI32LtUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32LeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LeS`] and Wasm branch instruction. BranchI32LeS(BranchBinOpInstr), - /// A fused [`Instruction::I32LeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LeS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32LeS`] with 16-bit encoded constant `rhs`. BranchI32LeSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32LeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LeU`] and Wasm branch instruction. BranchI32LeU(BranchBinOpInstr), - /// A fused [`Instruction::I32LeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32LeU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32LeU`] with 16-bit encoded constant `rhs`. BranchI32LeUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32GtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GtS`] and Wasm branch instruction. BranchI32GtS(BranchBinOpInstr), - /// A fused [`Instruction::I32GtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GtS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32GtS`] with 16-bit encoded constant `rhs`. BranchI32GtSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32GtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GtU`] and Wasm branch instruction. BranchI32GtU(BranchBinOpInstr), - /// A fused [`Instruction::I32GtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GtU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32GtU`] with 16-bit encoded constant `rhs`. BranchI32GtUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32GeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GeS`] and Wasm branch instruction. BranchI32GeS(BranchBinOpInstr), - /// A fused [`Instruction::I32GeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GeS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32GeS`] with 16-bit encoded constant `rhs`. BranchI32GeSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I32GeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GeU`] and Wasm branch instruction. BranchI32GeU(BranchBinOpInstr), - /// A fused [`Instruction::I32GeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I32GeU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI32GeU`] with 16-bit encoded constant `rhs`. BranchI32GeUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64Eq`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64Eq`] and Wasm branch instruction. BranchI64Eq(BranchBinOpInstr), - /// A fused [`Instruction::I64Eq`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64Eq`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64Eq`] with 16-bit encoded constant `rhs`. BranchI64EqImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64Ne`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64Ne`] and Wasm branch instruction. BranchI64Ne(BranchBinOpInstr), - /// A fused [`Instruction::I64Ne`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64Ne`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64Ne`] with 16-bit encoded constant `rhs`. BranchI64NeImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64LtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LtS`] and Wasm branch instruction. BranchI64LtS(BranchBinOpInstr), - /// A fused [`Instruction::I64LtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LtS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64LtS`] with 16-bit encoded constant `rhs`. BranchI64LtSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64LtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LtU`] and Wasm branch instruction. BranchI64LtU(BranchBinOpInstr), - /// A fused [`Instruction::I64LtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LtU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64LtU`] with 16-bit encoded constant `rhs`. BranchI64LtUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64LeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LeS`] and Wasm branch instruction. BranchI64LeS(BranchBinOpInstr), - /// A fused [`Instruction::I64LeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LeS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64LeS`] with 16-bit encoded constant `rhs`. BranchI64LeSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64LeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LeU`] and Wasm branch instruction. BranchI64LeU(BranchBinOpInstr), - /// A fused [`Instruction::I64LeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64LeU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64LeU`] with 16-bit encoded constant `rhs`. BranchI64LeUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64GtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GtS`] and Wasm branch instruction. BranchI64GtS(BranchBinOpInstr), - /// A fused [`Instruction::I64GtS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GtS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64GtS`] with 16-bit encoded constant `rhs`. BranchI64GtSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64GtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GtU`] and Wasm branch instruction. BranchI64GtU(BranchBinOpInstr), - /// A fused [`Instruction::I64GtU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GtU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64GtU`] with 16-bit encoded constant `rhs`. BranchI64GtUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64GeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GeS`] and Wasm branch instruction. BranchI64GeS(BranchBinOpInstr), - /// A fused [`Instruction::I64GeS`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GeS`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64GeS`] with 16-bit encoded constant `rhs`. BranchI64GeSImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::I64GeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GeU`] and Wasm branch instruction. BranchI64GeU(BranchBinOpInstr), - /// A fused [`Instruction::I64GeU`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::I64GeU`] and Wasm branch instruction. /// /// # Note /// /// Variant of [`Instruction::BranchI64GeU`] with 16-bit encoded constant `rhs`. BranchI64GeUImm(BranchBinOpInstrImm16), - /// A fused [`Instruction::F32Eq`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F32Eq`] and Wasm branch instruction. BranchF32Eq(BranchBinOpInstr), - /// A fused [`Instruction::F32Ne`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F32Ne`] and Wasm branch instruction. BranchF32Ne(BranchBinOpInstr), - /// A fused [`Instruction::F32Lt`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F32Lt`] and Wasm branch instruction. BranchF32Lt(BranchBinOpInstr), - /// A fused [`Instruction::F32Le`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F32Le`] and Wasm branch instruction. BranchF32Le(BranchBinOpInstr), - /// A fused [`Instruction::F32Gt`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F32Gt`] and Wasm branch instruction. BranchF32Gt(BranchBinOpInstr), - /// A fused [`Instruction::F32Ge`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F32Ge`] and Wasm branch instruction. BranchF32Ge(BranchBinOpInstr), - /// A fused [`Instruction::F64Eq`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F64Eq`] and Wasm branch instruction. BranchF64Eq(BranchBinOpInstr), - /// A fused [`Instruction::F64Ne`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F64Ne`] and Wasm branch instruction. BranchF64Ne(BranchBinOpInstr), - /// A fused [`Instruction::F64Lt`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F64Lt`] and Wasm branch instruction. BranchF64Lt(BranchBinOpInstr), - /// A fused [`Instruction::F64Le`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F64Le`] and Wasm branch instruction. BranchF64Le(BranchBinOpInstr), - /// A fused [`Instruction::F64Gt`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F64Gt`] and Wasm branch instruction. BranchF64Gt(BranchBinOpInstr), - /// A fused [`Instruction::F64Ge`] and [`Instruction::BranchI32Nez`] instruction. + /// A fused [`Instruction::F64Ge`] and Wasm branch instruction. BranchF64Ge(BranchBinOpInstr), /// A Wasm `br_table` instruction. From 313755e04d17d57b3fd5556f2166ebd47ae5b1dc Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Sat, 25 Nov 2023 10:20:37 +0100 Subject: [PATCH 5/7] refactor implementation of cmp+br instructions --- .../engine/regmach/executor/instrs/branch.rs | 174 +++++++++--------- 1 file changed, 87 insertions(+), 87 deletions(-) diff --git a/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs b/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs index a5b5e1a167..6a126d2c57 100644 --- a/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs +++ b/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs @@ -1,4 +1,4 @@ -use super::{Executor, UntypedValueExt}; +use super::Executor; use crate::engine::{ bytecode::BranchOffset, regmach::bytecode::{BranchBinOpInstr, BranchBinOpInstrImm16, Const16, Const32, Register}, @@ -27,135 +27,135 @@ impl<'ctx, 'engine> Executor<'ctx, 'engine> { } /// Executes a generic fused compare and branch instruction. - fn execute_branch_binop( + fn execute_branch_binop( &mut self, instr: BranchBinOpInstr, - f: fn(UntypedValue, UntypedValue) -> UntypedValue, - ) { - let lhs = self.get_register(instr.lhs); - let rhs = self.get_register(instr.rhs); - if bool::from(f(lhs, rhs)) { - self.branch_to(instr.offset.into()); - } else { - self.next_instr() + f: fn(T, T) -> bool, + ) + where + T: From, + { + let lhs: T = self.get_register_as(instr.lhs); + let rhs: T = self.get_register_as(instr.rhs); + if f(lhs, rhs) { + return self.branch_to(instr.offset.into()); } + self.next_instr() } /// Executes a generic fused compare and branch instruction with immediate `rhs` operand. fn execute_branch_binop_imm( &mut self, instr: BranchBinOpInstrImm16, - f: fn(UntypedValue, UntypedValue) -> UntypedValue, + f: fn(T, T) -> bool, ) where - T: From>, - UntypedValue: From, + T: From + From>, { - let lhs = self.get_register(instr.lhs); - let rhs = UntypedValue::from(T::from(instr.rhs)); - if bool::from(f(lhs, rhs)) { - self.branch_to(instr.offset.into()); - } else { - self.next_instr() + let lhs: T = self.get_register_as(instr.lhs); + let rhs = T::from(instr.rhs); + if f(lhs, rhs) { + return self.branch_to(instr.offset.into()); } + self.next_instr() } } macro_rules! impl_execute_branch_binop { - ( $( (Instruction::$op_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { + ( $( ($ty:ty, Instruction::$op_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { impl<'ctx, 'engine> Executor<'ctx, 'engine> { $( #[doc = concat!("Executes an [`Instruction::", stringify!($op_name), "`].")] #[inline(always)] pub fn $fn_name(&mut self, instr: BranchBinOpInstr) { - self.execute_branch_binop(instr, $op) + self.execute_branch_binop::<$ty>(instr, $op) } )* } } } impl_execute_branch_binop! { - (Instruction::BranchI32And, execute_branch_i32_and, UntypedValue::i32_and), - (Instruction::BranchI32Or, execute_branch_i32_or, UntypedValue::i32_or), - (Instruction::BranchI32Xor, execute_branch_i32_xor, UntypedValue::i32_xor), - (Instruction::BranchI32AndEqz, execute_branch_i32_and_eqz, UntypedValue::i32_and_eqz), - (Instruction::BranchI32OrEqz, execute_branch_i32_or_eqz, UntypedValue::i32_or_eqz), - (Instruction::BranchI32XorEqz, execute_branch_i32_xor_eqz, UntypedValue::i32_xor_eqz), - (Instruction::BranchI32Eq, execute_branch_i32_eq, UntypedValue::i32_eq), - (Instruction::BranchI32Ne, execute_branch_i32_ne, UntypedValue::i32_ne), - (Instruction::BranchI32LtS, execute_branch_i32_lt_s, UntypedValue::i32_lt_s), - (Instruction::BranchI32LtU, execute_branch_i32_lt_u, UntypedValue::i32_lt_u), - (Instruction::BranchI32LeS, execute_branch_i32_le_s, UntypedValue::i32_le_s), - (Instruction::BranchI32LeU, execute_branch_i32_le_u, UntypedValue::i32_le_u), - (Instruction::BranchI32GtS, execute_branch_i32_gt_s, UntypedValue::i32_gt_s), - (Instruction::BranchI32GtU, execute_branch_i32_gt_u, UntypedValue::i32_gt_u), - (Instruction::BranchI32GeS, execute_branch_i32_ge_s, UntypedValue::i32_ge_s), - (Instruction::BranchI32GeU, execute_branch_i32_ge_u, UntypedValue::i32_ge_u), + (i32, Instruction::BranchI32And, execute_branch_i32_and, |a, b| (a & b) != 0), + (i32, Instruction::BranchI32Or, execute_branch_i32_or, |a, b| (a | b) != 0), + (i32, Instruction::BranchI32Xor, execute_branch_i32_xor, |a, b| (a ^ b) != 0), + (i32, Instruction::BranchI32AndEqz, execute_branch_i32_and_eqz, |a, b| (a & b) == 0), + (i32, Instruction::BranchI32OrEqz, execute_branch_i32_or_eqz, |a, b| (a | b) == 0), + (i32, Instruction::BranchI32XorEqz, execute_branch_i32_xor_eqz, |a, b| (a ^ b) == 0), + (i32, Instruction::BranchI32Eq, execute_branch_i32_eq, |a, b| a == b), + (i32, Instruction::BranchI32Ne, execute_branch_i32_ne, |a, b| a != b), + (i32, Instruction::BranchI32LtS, execute_branch_i32_lt_s, |a, b| a < b), + (u32, Instruction::BranchI32LtU, execute_branch_i32_lt_u, |a, b| a < b), + (i32, Instruction::BranchI32LeS, execute_branch_i32_le_s, |a, b| a <= b), + (u32, Instruction::BranchI32LeU, execute_branch_i32_le_u, |a, b| a <= b), + (i32, Instruction::BranchI32GtS, execute_branch_i32_gt_s, |a, b| a > b), + (u32, Instruction::BranchI32GtU, execute_branch_i32_gt_u, |a, b| a > b), + (i32, Instruction::BranchI32GeS, execute_branch_i32_ge_s, |a, b| a >= b), + (u32, Instruction::BranchI32GeU, execute_branch_i32_ge_u, |a, b| a >= b), - (Instruction::BranchI64Eq, execute_branch_i64_eq, UntypedValue::i64_eq), - (Instruction::BranchI64Ne, execute_branch_i64_ne, UntypedValue::i64_ne), - (Instruction::BranchI64LtS, execute_branch_i64_lt_s, UntypedValue::i64_lt_s), - (Instruction::BranchI64LtU, execute_branch_i64_lt_u, UntypedValue::i64_lt_u), - (Instruction::BranchI64LeS, execute_branch_i64_le_s, UntypedValue::i64_le_s), - (Instruction::BranchI64LeU, execute_branch_i64_le_u, UntypedValue::i64_le_u), - (Instruction::BranchI64GtS, execute_branch_i64_gt_s, UntypedValue::i64_gt_s), - (Instruction::BranchI64GtU, execute_branch_i64_gt_u, UntypedValue::i64_gt_u), - (Instruction::BranchI64GeS, execute_branch_i64_ge_s, UntypedValue::i64_ge_s), - (Instruction::BranchI64GeU, execute_branch_i64_ge_u, UntypedValue::i64_ge_u), + (i64, Instruction::BranchI64Eq, execute_branch_i64_eq, |a, b| a == b), + (i64, Instruction::BranchI64Ne, execute_branch_i64_ne, |a, b| a != b), + (i64, Instruction::BranchI64LtS, execute_branch_i64_lt_s, |a, b| a < b), + (u64, Instruction::BranchI64LtU, execute_branch_i64_lt_u, |a, b| a < b), + (i64, Instruction::BranchI64LeS, execute_branch_i64_le_s, |a, b| a <= b), + (u64, Instruction::BranchI64LeU, execute_branch_i64_le_u, |a, b| a <= b), + (i64, Instruction::BranchI64GtS, execute_branch_i64_gt_s, |a, b| a > b), + (u64, Instruction::BranchI64GtU, execute_branch_i64_gt_u, |a, b| a > b), + (i64, Instruction::BranchI64GeS, execute_branch_i64_ge_s, |a, b| a >= b), + (u64, Instruction::BranchI64GeU, execute_branch_i64_ge_u, |a, b| a >= b), - (Instruction::BranchF32Eq, execute_branch_f32_eq, UntypedValue::f32_eq), - (Instruction::BranchF32Ne, execute_branch_f32_ne, UntypedValue::f32_ne), - (Instruction::BranchF32Lt, execute_branch_f32_lt, UntypedValue::f32_lt), - (Instruction::BranchF32Le, execute_branch_f32_le, UntypedValue::f32_le), - (Instruction::BranchF32Gt, execute_branch_f32_gt, UntypedValue::f32_gt), - (Instruction::BranchF32Ge, execute_branch_f32_ge, UntypedValue::f32_ge), + (f32, Instruction::BranchF32Eq, execute_branch_f32_eq, |a, b| a == b), + (f32, Instruction::BranchF32Ne, execute_branch_f32_ne, |a, b| a != b), + (f32, Instruction::BranchF32Lt, execute_branch_f32_lt, |a, b| a < b), + (f32, Instruction::BranchF32Le, execute_branch_f32_le, |a, b| a <= b), + (f32, Instruction::BranchF32Gt, execute_branch_f32_gt, |a, b| a > b), + (f32, Instruction::BranchF32Ge, execute_branch_f32_ge, |a, b| a >= b), - (Instruction::BranchF64Eq, execute_branch_f64_eq, UntypedValue::f64_eq), - (Instruction::BranchF64Ne, execute_branch_f64_ne, UntypedValue::f64_ne), - (Instruction::BranchF64Lt, execute_branch_f64_lt, UntypedValue::f64_lt), - (Instruction::BranchF64Le, execute_branch_f64_le, UntypedValue::f64_le), - (Instruction::BranchF64Gt, execute_branch_f64_gt, UntypedValue::f64_gt), - (Instruction::BranchF64Ge, execute_branch_f64_ge, UntypedValue::f64_ge), + (f64, Instruction::BranchF64Eq, execute_branch_f64_eq, |a, b| a == b), + (f64, Instruction::BranchF64Ne, execute_branch_f64_ne, |a, b| a != b), + (f64, Instruction::BranchF64Lt, execute_branch_f64_lt, |a, b| a < b), + (f64, Instruction::BranchF64Le, execute_branch_f64_le, |a, b| a <= b), + (f64, Instruction::BranchF64Gt, execute_branch_f64_gt, |a, b| a > b), + (f64, Instruction::BranchF64Ge, execute_branch_f64_ge, |a, b| a >= b), } macro_rules! impl_execute_branch_binop_imm { - ( $( (Instruction::$op_name:ident, $fn_name:ident, $op:expr, $ty:ty) ),* $(,)? ) => { + ( $( ($ty:ty, Instruction::$op_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { impl<'ctx, 'engine> Executor<'ctx, 'engine> { $( #[doc = concat!("Executes an [`Instruction::", stringify!($op_name), "`].")] #[inline(always)] pub fn $fn_name(&mut self, instr: BranchBinOpInstrImm16<$ty>) { - self.execute_branch_binop_imm(instr, $op) + self.execute_branch_binop_imm::<$ty>(instr, $op) } )* } } } impl_execute_branch_binop_imm! { - (Instruction::BranchI32AndImm, execute_branch_i32_and_imm, UntypedValue::i32_and, i32), - (Instruction::BranchI32OrImm, execute_branch_i32_or_imm, UntypedValue::i32_or, i32), - (Instruction::BranchI32XorImm, execute_branch_i32_xor_imm, UntypedValue::i32_xor, i32), - (Instruction::BranchI32AndEqzImm, execute_branch_i32_and_eqz_imm, UntypedValue::i32_and_eqz, i32), - (Instruction::BranchI32OrEqzImm, execute_branch_i32_or_eqz_imm, UntypedValue::i32_or_eqz, i32), - (Instruction::BranchI32XorEqzImm, execute_branch_i32_xor_eqz_imm, UntypedValue::i32_xor_eqz, i32), - (Instruction::BranchI32EqImm, execute_branch_i32_eq_imm, UntypedValue::i32_eq, i32), - (Instruction::BranchI32NeImm, execute_branch_i32_ne_imm, UntypedValue::i32_ne, i32), - (Instruction::BranchI32LtSImm, execute_branch_i32_lt_s_imm, UntypedValue::i32_lt_s, i32), - (Instruction::BranchI32LtUImm, execute_branch_i32_lt_u_imm, UntypedValue::i32_lt_u, u32), - (Instruction::BranchI32LeSImm, execute_branch_i32_le_s_imm, UntypedValue::i32_le_s, i32), - (Instruction::BranchI32LeUImm, execute_branch_i32_le_u_imm, UntypedValue::i32_le_u, u32), - (Instruction::BranchI32GtSImm, execute_branch_i32_gt_s_imm, UntypedValue::i32_gt_s, i32), - (Instruction::BranchI32GtUImm, execute_branch_i32_gt_u_imm, UntypedValue::i32_gt_u, u32), - (Instruction::BranchI32GeSImm, execute_branch_i32_ge_s_imm, UntypedValue::i32_ge_s, i32), - (Instruction::BranchI32GeUImm, execute_branch_i32_ge_u_imm, UntypedValue::i32_ge_u, u32), + (i32, Instruction::BranchI32AndImm, execute_branch_i32_and_imm, |a, b| (a & b) != 0), + (i32, Instruction::BranchI32OrImm, execute_branch_i32_or_imm, |a, b| (a | b) != 0), + (i32, Instruction::BranchI32XorImm, execute_branch_i32_xor_imm, |a, b| (a ^ b) != 0), + (i32, Instruction::BranchI32AndEqzImm, execute_branch_i32_and_eqz_imm, |a, b| (a & b) == 0), + (i32, Instruction::BranchI32OrEqzImm, execute_branch_i32_or_eqz_imm, |a, b| (a | b) == 0), + (i32, Instruction::BranchI32XorEqzImm, execute_branch_i32_xor_eqz_imm, |a, b| (a ^ b) == 0), + (i32, Instruction::BranchI32EqImm, execute_branch_i32_eq_imm, |a, b| a == b), + (i32, Instruction::BranchI32NeImm, execute_branch_i32_ne_imm, |a, b| a != b), + (i32, Instruction::BranchI32LtSImm, execute_branch_i32_lt_s_imm, |a, b| a < b), + (u32, Instruction::BranchI32LtUImm, execute_branch_i32_lt_u_imm, |a, b| a < b), + (i32, Instruction::BranchI32LeSImm, execute_branch_i32_le_s_imm, |a, b| a <= b), + (u32, Instruction::BranchI32LeUImm, execute_branch_i32_le_u_imm, |a, b| a <= b), + (i32, Instruction::BranchI32GtSImm, execute_branch_i32_gt_s_imm, |a, b| a > b), + (u32, Instruction::BranchI32GtUImm, execute_branch_i32_gt_u_imm, |a, b| a > b), + (i32, Instruction::BranchI32GeSImm, execute_branch_i32_ge_s_imm, |a, b| a >= b), + (u32, Instruction::BranchI32GeUImm, execute_branch_i32_ge_u_imm, |a, b| a >= b), - (Instruction::BranchI64EqImm, execute_branch_i64_eq_imm, UntypedValue::i64_eq, i64), - (Instruction::BranchI64NeImm, execute_branch_i64_ne_imm, UntypedValue::i64_ne, i64), - (Instruction::BranchI64LtSImm, execute_branch_i64_lt_s_imm, UntypedValue::i64_lt_s, i64), - (Instruction::BranchI64LtUImm, execute_branch_i64_lt_u_imm, UntypedValue::i64_lt_u, u64), - (Instruction::BranchI64LeSImm, execute_branch_i64_le_s_imm, UntypedValue::i64_le_s, i64), - (Instruction::BranchI64LeUImm, execute_branch_i64_le_u_imm, UntypedValue::i64_le_u, u64), - (Instruction::BranchI64GtSImm, execute_branch_i64_gt_s_imm, UntypedValue::i64_gt_s, i64), - (Instruction::BranchI64GtUImm, execute_branch_i64_gt_u_imm, UntypedValue::i64_gt_u, u64), - (Instruction::BranchI64GeSImm, execute_branch_i64_ge_s_imm, UntypedValue::i64_ge_s, i64), - (Instruction::BranchI64GeUImm, execute_branch_i64_ge_u_imm, UntypedValue::i64_ge_u, u64), + (i64, Instruction::BranchI64EqImm, execute_branch_i64_eq_imm, |a, b| a == b), + (i64, Instruction::BranchI64NeImm, execute_branch_i64_ne_imm, |a, b| a != b), + (i64, Instruction::BranchI64LtSImm, execute_branch_i64_lt_s_imm, |a, b| a < b), + (u64, Instruction::BranchI64LtUImm, execute_branch_i64_lt_u_imm, |a, b| a < b), + (i64, Instruction::BranchI64LeSImm, execute_branch_i64_le_s_imm, |a, b| a <= b), + (u64, Instruction::BranchI64LeUImm, execute_branch_i64_le_u_imm, |a, b| a <= b), + (i64, Instruction::BranchI64GtSImm, execute_branch_i64_gt_s_imm, |a, b| a > b), + (u64, Instruction::BranchI64GtUImm, execute_branch_i64_gt_u_imm, |a, b| a > b), + (i64, Instruction::BranchI64GeSImm, execute_branch_i64_ge_s_imm, |a, b| a >= b), + (u64, Instruction::BranchI64GeUImm, execute_branch_i64_ge_u_imm, |a, b| a >= b), } From 61250bcc4b090965f8273d9b76f4cf6d2283908b Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Sat, 25 Nov 2023 10:24:03 +0100 Subject: [PATCH 6/7] apply rustfmt --- .../src/engine/regmach/executor/instrs/branch.rs | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs b/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs index 6a126d2c57..55644ffe2f 100644 --- a/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs +++ b/crates/wasmi/src/engine/regmach/executor/instrs/branch.rs @@ -27,11 +27,7 @@ impl<'ctx, 'engine> Executor<'ctx, 'engine> { } /// Executes a generic fused compare and branch instruction. - fn execute_branch_binop( - &mut self, - instr: BranchBinOpInstr, - f: fn(T, T) -> bool, - ) + fn execute_branch_binop(&mut self, instr: BranchBinOpInstr, f: fn(T, T) -> bool) where T: From, { @@ -44,11 +40,8 @@ impl<'ctx, 'engine> Executor<'ctx, 'engine> { } /// Executes a generic fused compare and branch instruction with immediate `rhs` operand. - fn execute_branch_binop_imm( - &mut self, - instr: BranchBinOpInstrImm16, - f: fn(T, T) -> bool, - ) where + fn execute_branch_binop_imm(&mut self, instr: BranchBinOpInstrImm16, f: fn(T, T) -> bool) + where T: From + From>, { let lhs: T = self.get_register_as(instr.lhs); From 80c466deba9151ffd48323ec19f0b26f7946baa1 Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Sat, 25 Nov 2023 10:33:04 +0100 Subject: [PATCH 7/7] reduce column noise --- .../regmach/translator/instr_encoder.rs | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs b/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs index fe04047fc6..df0e02f6b2 100644 --- a/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs +++ b/crates/wasmi/src/engine/regmach/translator/instr_encoder.rs @@ -906,7 +906,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i32_nez(instr.reg_in, offset16)) } } @@ -915,7 +916,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i64_nez(instr.reg_in, offset16)) } } @@ -924,7 +926,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i32_eqz(instr.reg_in, offset16)) } } @@ -933,7 +936,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i64_eqz(instr.reg_in, offset16)) } } @@ -1084,7 +1088,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i32_eqz(instr.reg_in, offset16)) } } @@ -1093,7 +1098,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i64_eqz(instr.reg_in, offset16)) } } @@ -1102,7 +1108,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i32_nez(instr.reg_in, offset16)) } } @@ -1111,7 +1118,8 @@ impl InstrEncoder { match stack.get_register_space(instr.result) { RegisterSpace::Local => None, _ => { - let offset16 = self.try_resolve_label_for(label, last_instr).and_then(BranchOffset16::try_from)?; + let offset16 = self.try_resolve_label_for(label, last_instr) + .and_then(BranchOffset16::try_from)?; Some(Instruction::branch_i64_nez(instr.reg_in, offset16)) } }