diff --git a/Makefile b/Makefile index 266d613..5c683c5 100644 --- a/Makefile +++ b/Makefile @@ -8,8 +8,8 @@ FILES = lectures/l00_diode \ lectures/l00_refresher \ lectures/lp_project_report \ lectures/l01_intro \ -# lectures/l02_esd \ - lectures/l03_refbias \ + lectures/l02_esd \ +# lectures/l03_refbias \ lectures/l04_afe \ lectures/l05_sc \ lectures/l06_adc \ diff --git a/docs/plan.md b/docs/plan.md index fc6f071..fb13e7b 100644 --- a/docs/plan.md +++ b/docs/plan.md @@ -5,22 +5,23 @@ permalink: /plan/ --- -| Week | Book | Thursday | Topics | -|------|----------------------|---------------------------|-------------------------------------------------------------| -| 2 | CJM 1-6 | Introduction | Info, Refresh | -| 3 | | ICs and their components | Refresh, IC components, ESD, GGNMOS, Latchup | -| 4 | CJM 7,8 | Reference and bias | Diode voltage, bandgaps, low voltage bandgaps, bias sources | -| 5 | CJM 12 | Filters and DACs | Filter synthesis, Gm-C, Active-RC, DACs | -| 6 | CJM 11-14 | Switched capacitor | Discrete-Time, Z-domain, Switched capacitor | -| 7 | CJM 18 | Oversampling converters | FOM, Quantization, Oversampling, Noise shaping, Sigma-Delta | -| 8 | | Winter holiday | | -| 9 | CJM 7.4, CFAS,+DC/DC | Voltage regulation | LDO, ULP, BUCK, BOOST, PWM, PFM | -| 10 | CJM 19, CFAS | PLLs | Calculation, VCO, PFD, Loop-filter, dividers | -| 11 | Paper | Oscillators | RC-Oscillators, Crystal oscillators | -| 12 | Slides | Low-power radio receivers | GFSK, QPSK, PSK, QAM, radio blocks | -| 13 | | Easter | | -| 14 | | Easter | | -| 15 | | Analog SystemVerilog | analog system verilog behavioral models and energy sources | -| 16 | | Q & A | | -| 17 | | Q & A | | +| Week | Book | Project | Lecture | Topics | +|------|----------------------|---------|---------------------------|-------------------------------------------------------------| +| 2 | CJM 1-6 | | Introduction | Info, Refresh | +| 3 | | | ICs and their components | Refresh, IC components, ESD, GGNMOS, Latchup | +| 4 | CJM 7,8 | | Reference and bias | Diode voltage, bandgaps, low voltage bandgaps, bias sources | +| 5 | CJM 12 | | Filters and DACs | Filter synthesis, Gm-C, Active-RC, DACs | +| 6 | CJM 11-14 | M1 | Switched capacitor | Discrete-Time, Z-domain, Switched capacitor | +| 7 | CJM 18 | | Oversampling converters | FOM, Quantization, Oversampling, Noise shaping, Sigma-Delta | +| 8 | | | Winter holiday | | +| 9 | CJM 7.4, CFAS,+DC/DC | M2 | Voltage regulation | LDO, ULP, BUCK, BOOST, PWM, PFM | +| 10 | CJM 19, CFAS | | PLLs | Calculation, VCO, PFD, Loop-filter, dividers | +| 11 | Paper | | Oscillators | RC-Oscillators, Crystal oscillators | +| 12 | Slides | M3 | Low-power radio receivers | GFSK, QPSK, PSK, QAM, radio blocks | +| 13 | | | Easter | | +| 14 | | | Easter | | +| 15 | | M4 | Analog SystemVerilog | analog system verilog behavioral models and energy sources | +| 16 | | | Q & A | | +| 17 | | | Q & A | | +| 18 | | M5 | Q & A | | diff --git a/dot/Makefile b/dot/Makefile index 48796ac..c17fd28 100644 --- a/dot/Makefile +++ b/dot/Makefile @@ -2,3 +2,4 @@ figs: cat dig_des.dot | dot -Tsvg > ../media/dig_des.svg + cat dig_des_lr.dot | dot -Tsvg > ../media/dig_des_lr.svg diff --git a/lectures/l01_intro.md b/lectures/l01_intro.md index 437ca5f..90f079b 100644 --- a/lectures/l01_intro.md +++ b/lectures/l01_intro.md @@ -117,11 +117,15 @@ If you like the world to be ordered, with definite answers, then it's likely tha If you're comfortable with not knowing, and an insatiable desire to understand how the world *really* works at a fundamental level, then it's likely that you'll find analog flow interesting. +![inline](../media/dig_des.svg) + --> --- -![inline](../media/dig_des.svg) + + +![inline](../media/dig_des_lr.svg) --- @@ -274,13 +278,14 @@ my understanding is wrong, then I'll happily discuss. **Lectures:** Friday at 08:15 - 10:00 -The "lectures" will be Q & A's on the topic. If no questions, then I'll ramble on +Read the introduction before the lectures at [aic2024](https://analogicus.com/aic2024) -**Exercise Hours:** -Friday at 10:15 - 12:00 +The "lectures" will be Q & A's on the topic. If no questions, then I'll ramble on. -The TA will be in the "exercise hours", and I also will hopefully join most days. +**Project Hours:** +Friday at 10:15 - 12:00 +The TA will be in the "project hours", and I will join most days. --- @@ -290,7 +295,7 @@ The TA will be in the "exercise hours", and I also will hopefully join most days - [Description](https://www.ntnu.no/studier/emner/TFE4188#tab=omEmnet) -- [Time schedule](https://tp.uio.no/ntnu/timeplan/?id=TFE4188&sem=24v&sort=form&type=course) +- [Time schedule](https://www.ntnu.no/studier/emner/TFE4188#tab=timeplan) - [Lecture plan](https://wulffern.github.io/aic2024/plan/) @@ -314,7 +319,7 @@ Buy a hard-copy of the book if you don't have that. Don't expect to understand t --> -![inline](../media/cjm.png) ![inline](../media/cfas.png) +![inline](../media/cjm.png) --- @@ -323,9 +328,10 @@ Buy a hard-copy of the book if you don't have that. Don't expect to understand t ## Exam -- May/June 2022? +- June 2022 - 4 hours - A - F grade (F = Fail) +- Counts for 55 % of the grade --- @@ -344,7 +350,7 @@ Buy a hard-copy of the book if you don't have that. Don't expect to understand t - For the rest, two options: - Don't do the exercises, don't get feedback - Do the exercises, hand them in within deadline, get feedback -- The TA's will only support the exercises in the marked weeks +- The TA will only support the exercises in the marked weeks --- @@ -411,7 +417,6 @@ The fourth milestone is the report, while the fifth milestone is the layout. --- - ![fit](../media/project_plan.pdf) @@ -437,18 +442,28 @@ During the first group session of a milestone, you will **Check-in (10 minutes)** -Each member of the group says how they feel. Some examples could be: +Some example questions could be + +- Share one thing that is going on in your life (personal or professional.) +- What is one thing that you are grateful for right now? +- What is something funny that happened? + +Some examples answers could be: - My dog died yesterday, so I'm not feeling great today. -- I woke up early, had an omelette, and went running, so I feel motivated and fantastic. +- I woke up early, had an omelet, and went running, so I feel motivated and fantastic. - I feel *blaaah* today, motivation is lacking. +- I went running yesterday and did not discover before I got home that I'd forgotten to put my pants on, even though it was + -10 C. -The point of this excersize is to get to know eachother a bit, and attempt to create pshycological safety in the group. +The point of this exercise is to get to know each other a bit, and attempt to create psychological safety in the group. -**Ideas (30 minutes)** +**Ideas (35 minutes)** Come up with ideas for how the milestone could be implemented. What circuit ideas could work? -**Plan (10 minutes)** +**Break (15 minutes)** + +**Plan (20 minutes)** Sketch out who does what the next week. What's the goal for the week. @@ -467,11 +482,11 @@ Each group member talks about their one word. You shall always Check-in, Reflect and Discuss. Although some may consider it a waste of time, it's important to improve the group dynamics. -**Review (30 minutes)** +**Review (35 minutes)** Go through the plan from last week, what worked, what did not work, what should be done differently. Discuss. -**Plan (10 minutes)** +**Plan (20 minutes)** Sketch out who does what the next week. What's the goal for the week. @@ -500,7 +515,7 @@ I've made a rather detailed (at least I think so myself) tutorial on how to make I strongly recommend you start with that first. --> - [rply\_ex0\_sky130nm](https://wulffern.github.io/rply_ex0_sky130nm) + [Skywater 130 nm Tutorial](https://analogicus.com/aic2024/2023/11/16/Tools.html) @@ -16,7 +16,7 @@ header: Helvetica -## [TFE4188 - Introduction to Lecture 2](https://wulffern.github.io/aic2023/2023/01/19/Lecture-2-IC-and-ESD.html) +## TFE4188 - Introduction to Lecture 2 # ICs and ESD --- @@ -31,13 +31,6 @@ Understand why you must **always handle ESD** on an IC --- - - -#[fit] RPLY - -The project for 2023 is to design an integrated temperature sensor. The hope is that some will tapeout on the Google/Efabless Open MPW shuttle - ---- @@ -50,7 +43,7 @@ The project for 2023 is to design an integrated temperature sensor. The hope is @@ -141,12 +134,14 @@ If you make an IC, you must consider Electrostatic Discharge (ESD) Protection ci **Charged device model (CDM)** @@ -333,7 +329,7 @@ We want a circuit that most of the time sleeps, and does not affect our normal I a huge current comes in on VDD, and the VDD voltage shoots up fast, the circuit must wake up and bring the voltage down. If the circuit triggers under normal operating condition, when your watching a video on your phone, your battery will -drain very fast, and it might even catch fire. +drain very fast, and your phone might even catch fire. As such, ESD design engineers have a "ESD design window". Never let the ESD circuit trigger when VDD < normal, but always trigger the ESD circuit before VDD $>$ breakdown of circuit. @@ -381,7 +377,7 @@ when they scatter off an atom. If you break too many bonds between atoms, your m Assume a transistor like the one below. The gate, source and bulk is connected to ground. The drain is connected to a high voltage. -![](../media/physics/ggnmos.pdf) +![](../media/ggnmos.pdf) ### Avalanche @@ -472,7 +468,7 @@ Assume we have the circuit below. We can draw a cross section of the inverter. -![](../media/physics/scr_eh.pdf) +![](../media/scr_eh.pdf) ### Electron injection diff --git a/media/dig_des_lr.svg b/media/dig_des_lr.svg new file mode 100644 index 0000000..27f2602 --- /dev/null +++ b/media/dig_des_lr.svg @@ -0,0 +1,202 @@ + + + + + + +G + + + +I + +Idea + + + +D + +Digital Design + SystemVerilog + + + +I->D + + + + + +AD + +Analog Design +Xschem + + + +I->AD + + + + + +S + +Digital Simulation + iverilog/vpp/verilator/gtkwave + + + +D->S + + + + + +S->D + + + + + +PNR + +RTL to GDSII +OpenRoad + + + +S->PNR + + + + + +PNR->S + + + + + +TO + +Tapeout + + + +PNR->TO + + + + + +ASV + +Analog Model +SystemVerilog + + + +AD->ASV + + + + + +AS + +Analog Simulation +ngspice + + + +AD->AS + + + + + +ASV->D + + + + + +AS->AD + + + + + +AL + +Analog Layout +Magic + + + +AS->AL + + + + + +AL->AS + + + + + +AV + +LVS +netgen + + + +AL->AV + + + + + +LPE + +Parasitics +Magic + + + +AV->LPE + + + + + +AGDS + +GDSII + + + +AV->AGDS + + + + + +LPE->AS + + + + + +AGDS->PNR + + + + + diff --git a/media/esd_hbm_finger.pdf b/media/esd_hbm_finger.pdf new file mode 100644 index 0000000..522fa4a Binary files /dev/null and b/media/esd_hbm_finger.pdf differ diff --git a/media/esd_hbm_finger.svg b/media/esd_hbm_finger.svg new file mode 100644 index 0000000..7aa02e3 --- /dev/null +++ b/media/esd_hbm_finger.svg @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media/esd_hbm_model.pdf b/media/esd_hbm_model.pdf new file mode 100644 index 0000000..4b1e822 Binary files /dev/null and b/media/esd_hbm_model.pdf differ diff --git a/media/esd_hbm_model.svg b/media/esd_hbm_model.svg new file mode 100644 index 0000000..df9a7cf --- /dev/null +++ b/media/esd_hbm_model.svg @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media/l02_02.pdf b/media/l02_02.pdf new file mode 100644 index 0000000..8e15c3c Binary files /dev/null and b/media/l02_02.pdf differ diff --git a/media/l02_02.svg b/media/l02_02.svg new file mode 100644 index 0000000..eaafc7d --- /dev/null +++ b/media/l02_02.svg @@ -0,0 +1,71 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media/l02_all.pdf b/media/l02_all.pdf new file mode 100644 index 0000000..4151e3b Binary files /dev/null and b/media/l02_all.pdf differ diff --git a/media/l02_all.svg b/media/l02_all.svg new file mode 100644 index 0000000..fb333e2 --- /dev/null +++ b/media/l02_all.svg @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media/l02_ggnmos.pdf b/media/l02_ggnmos.pdf new file mode 100644 index 0000000..67c1734 Binary files /dev/null and b/media/l02_ggnmos.pdf differ diff --git a/media/l02_ggnmos.svg b/media/l02_ggnmos.svg new file mode 100644 index 0000000..6f929b8 --- /dev/null +++ b/media/l02_ggnmos.svg @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media/l02_hbm_overview.pdf b/media/l02_hbm_overview.pdf new file mode 100644 index 0000000..bc4b053 Binary files /dev/null and b/media/l02_hbm_overview.pdf differ diff --git a/media/l02_hbm_overview.svg b/media/l02_hbm_overview.svg new file mode 100644 index 0000000..f1863ea --- /dev/null +++ b/media/l02_hbm_overview.svg @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media/l02_latchup.pdf b/media/l02_latchup.pdf new file mode 100644 index 0000000..7d6ca73 Binary files /dev/null and b/media/l02_latchup.pdf differ diff --git a/media/l02_latchup.svg b/media/l02_latchup.svg new file mode 100644 index 0000000..121cdf5 --- /dev/null +++ b/media/l02_latchup.svg @@ -0,0 +1,84 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media/scr_eh.pdf b/media/scr_eh.pdf new file mode 100644 index 0000000..3d14bdf Binary files /dev/null and b/media/scr_eh.pdf differ diff --git a/media/scr_eh.svg b/media/scr_eh.svg new file mode 100644 index 0000000..530c1ab --- /dev/null +++ b/media/scr_eh.svg @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/plan.md b/plan.md index fc6f071..fb13e7b 100644 --- a/plan.md +++ b/plan.md @@ -5,22 +5,23 @@ permalink: /plan/ --- -| Week | Book | Thursday | Topics | -|------|----------------------|---------------------------|-------------------------------------------------------------| -| 2 | CJM 1-6 | Introduction | Info, Refresh | -| 3 | | ICs and their components | Refresh, IC components, ESD, GGNMOS, Latchup | -| 4 | CJM 7,8 | Reference and bias | Diode voltage, bandgaps, low voltage bandgaps, bias sources | -| 5 | CJM 12 | Filters and DACs | Filter synthesis, Gm-C, Active-RC, DACs | -| 6 | CJM 11-14 | Switched capacitor | Discrete-Time, Z-domain, Switched capacitor | -| 7 | CJM 18 | Oversampling converters | FOM, Quantization, Oversampling, Noise shaping, Sigma-Delta | -| 8 | | Winter holiday | | -| 9 | CJM 7.4, CFAS,+DC/DC | Voltage regulation | LDO, ULP, BUCK, BOOST, PWM, PFM | -| 10 | CJM 19, CFAS | PLLs | Calculation, VCO, PFD, Loop-filter, dividers | -| 11 | Paper | Oscillators | RC-Oscillators, Crystal oscillators | -| 12 | Slides | Low-power radio receivers | GFSK, QPSK, PSK, QAM, radio blocks | -| 13 | | Easter | | -| 14 | | Easter | | -| 15 | | Analog SystemVerilog | analog system verilog behavioral models and energy sources | -| 16 | | Q & A | | -| 17 | | Q & A | | +| Week | Book | Project | Lecture | Topics | +|------|----------------------|---------|---------------------------|-------------------------------------------------------------| +| 2 | CJM 1-6 | | Introduction | Info, Refresh | +| 3 | | | ICs and their components | Refresh, IC components, ESD, GGNMOS, Latchup | +| 4 | CJM 7,8 | | Reference and bias | Diode voltage, bandgaps, low voltage bandgaps, bias sources | +| 5 | CJM 12 | | Filters and DACs | Filter synthesis, Gm-C, Active-RC, DACs | +| 6 | CJM 11-14 | M1 | Switched capacitor | Discrete-Time, Z-domain, Switched capacitor | +| 7 | CJM 18 | | Oversampling converters | FOM, Quantization, Oversampling, Noise shaping, Sigma-Delta | +| 8 | | | Winter holiday | | +| 9 | CJM 7.4, CFAS,+DC/DC | M2 | Voltage regulation | LDO, ULP, BUCK, BOOST, PWM, PFM | +| 10 | CJM 19, CFAS | | PLLs | Calculation, VCO, PFD, Loop-filter, dividers | +| 11 | Paper | | Oscillators | RC-Oscillators, Crystal oscillators | +| 12 | Slides | M3 | Low-power radio receivers | GFSK, QPSK, PSK, QAM, radio blocks | +| 13 | | | Easter | | +| 14 | | | Easter | | +| 15 | | M4 | Analog SystemVerilog | analog system verilog behavioral models and energy sources | +| 16 | | | Q & A | | +| 17 | | | Q & A | | +| 18 | | M5 | Q & A | |