diff --git a/dot/dig_des.dot b/dot/dig_des.dot index 4db8be6..d6d1790 100644 --- a/dot/dig_des.dot +++ b/dot/dig_des.dot @@ -1,6 +1,6 @@ digraph G{ -rankdir="LR"; +#rankdir="LR"; node [margin=0.5 color=blue fontcolor=black fontsize=20 width=0.5 shape=box fontname="Helvetica"] I [label="Idea",shape=egg] diff --git a/lectures/l01_intro.md b/lectures/l01_intro.md index 7a81b95..1b03646 100644 --- a/lectures/l01_intro.md +++ b/lectures/l01_intro.md @@ -139,6 +139,9 @@ have fueled a renaissance of open source software tools. Together with [Efabless](https://https://efabless.com) there are cheap alternatives, like [tinytapeout](https://tinytapeout.com), which makes it possible for a private citizen to tape-out their own integrated circuit. +Google just sponsored a [GlobalFoundries 180 nm tapeout](https://efabless.com/gf-180-open-mpw-shuttle-program) where you could tape out +your circuit for free. + --> @@ -247,7 +250,7 @@ I want to: - Enable you to read the books on integrated circuits - Enable you to read papers (latest research) -- Correct misunderstandings of the topic +- Correct misunderstandings on the topic - Answer any questions you have on the chapters - - @@ -361,14 +365,116 @@ Strict deadline 29 of April. If you hand in 30 of April at 00:00:01, then you fa *"In an insane world, it was the sanest choice."* - Sarah Connor, Terminator 2: Judgment Day + + **Design a integrated temperature sensor with digital read-out** + + + --- ![fit](../media/project_plan.pdf) + + + --- diff --git a/media/dig_des.svg b/media/dig_des.svg index 3332076..c77a5ff 100644 --- a/media/dig_des.svg +++ b/media/dig_des.svg @@ -1,202 +1,202 @@ - - - + + G - + I - -Idea + +Idea D - -Digital Design - SystemVerilog + +Digital Design + SystemVerilog I->D - - + + AD - -Analog Design -Xschem + +Analog Design +Xschem I->AD - - + + S - -Digital Simulation - iverilog/vpp/verilator/gtkwave + +Digital Simulation + iverilog/vpp/verilator/gtkwave D->S - - + + S->D - - + + PNR - -RTL to GDSII -OpenRoad + +RTL to GDSII +OpenRoad S->PNR - - + + PNR->S - - + + TO - -Tapeout + +Tapeout PNR->TO - - + + ASV - -Analog Model -SystemVerilog + +Analog Model +SystemVerilog AD->ASV - - + + AS - -Analog Simulation -ngspice + +Analog Simulation +ngspice AD->AS - - + + ASV->D - - + + AS->AD - - + + AL - -Analog Layout -Magic + +Analog Layout +Magic AS->AL - - + + AL->AS - - + + AV - -LVS -netgen + +LVS +netgen AL->AV - - + + LPE - -Parasitics -Magic + +Parasitics +Magic AV->LPE - - + + AGDS - -GDSII + +GDSII AV->AGDS - - + + LPE->AS - - + + AGDS->PNR - - + +