Consider multiple clock domains

[yupferris]

I've always liked the idea of lifting some kind of clock domain identifier(s) into the type system, so most logic is constrained to only interact with other logic in the same domain, but with some types able to bridge the gap by implementing CDC (eg. special FIFOs), which ensure robust/safe behavior between domains.

I'm not entirely sure how to handle this in sim, though. Perhaps exposing multiple posedge_clk fn's (one per enumerated domain?) or having that function take the domain to transition on as a parameter or something is sufficient? This ends up putting yet more sim scheduling burden on the user, but might make sense. This also puts more pressure on sim efficiency, since more prop calls are likely required per simulated unit of time in order to correctly propagate signals between domains.

Definitely needs more thought/experimentation!