+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_ll_crs.h"
+#include "stm32c0xx_ll_bus.h"
+
+/** @addtogroup STM32C0xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRS_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes CRS peripheral registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRS registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_CRS_DeInit(void)
+{
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRS) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_dma.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_dma.c
index 3f0cf6f24..80d655a16 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_dma.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_dma.c
@@ -74,10 +74,19 @@
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+#if defined(LL_DMA_CHANNEL_5)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#else
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
((CHANNEL) == LL_DMA_CHANNEL_2) || \
((CHANNEL) == LL_DMA_CHANNEL_3))))
+#endif /* LL_DMA_CHANNEL_5 */
/**
* @}
@@ -101,7 +110,10 @@
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4 (*)
+ * @arg @ref LL_DMA_CHANNEL_5 (*)
* @arg @ref LL_DMA_CHANNEL_ALL
+ * @note (*) Availability depends on devices
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are de-initialized
* - ERROR: DMA registers are not de-initialized
@@ -167,6 +179,18 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
/* Reset interrupt pending bits for DMAx Channel3 */
LL_DMA_ClearFlag_GI3(DMAx);
}
+#if defined(DMA1_Channel4)
+ else if (Channel == LL_DMA_CHANNEL_4)
+ {
+ /* Reset interrupt pending bits for DMAx Channel4 */
+ LL_DMA_ClearFlag_GI4(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_5)
+ {
+ /* Reset interrupt pending bits for DMAx Channel5 */
+ LL_DMA_ClearFlag_GI5(DMAx);
+ }
+#endif /* DMA1_Channel4 */
else
{
status = ERROR;
@@ -186,6 +210,9 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4 (*)
+ * @arg @ref LL_DMA_CHANNEL_5 (*)
+ * @note (*) Availability depends on devices
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are initialized
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_exti.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_exti.c
index 50af5587c..4cbfabf4d 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_exti.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_exti.c
@@ -44,7 +44,9 @@
*/
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-
+#if defined(EXTI_IMR2_IM36)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+#endif /* EXTI_IMR2_IM36 */
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
@@ -91,6 +93,22 @@ ErrorStatus LL_EXTI_DeInit(void)
/* Pending register set to default reset values */
LL_EXTI_WriteReg(RPR1, 0x0007FFFFU);
LL_EXTI_WriteReg(FPR1, 0x0007FFFFU);
+#if defined(EXTI_IMR2_IM36)
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR2, 0x00000010U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR2, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR2, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR2, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+ /* Pending register set to default reset values */
+ LL_EXTI_WriteReg(RPR2, 0x00000004U);
+ LL_EXTI_WriteReg(FPR2, 0x00000004U);
+#endif /* EXTI_IMR2_IM36*/
+
return SUCCESS;
}
@@ -106,6 +124,9 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+#if defined(EXTI_IMR2_IM36)
+ assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+#endif /* EXTI_IMR2_IM36 */
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
@@ -140,6 +161,7 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
status = ERROR;
break;
}
+
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
switch (EXTI_InitStruct->Trigger)
@@ -166,7 +188,60 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
}
}
}
-
+#if defined(EXTI_IMR2_IM36)
+ /* Configure EXTI Lines in range from 32 to 63 */
+ if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+#endif /* EXTI_IMR2_IM36 */
}
/* DISABLE LineCommand */
else
@@ -174,9 +249,15 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
/* De-configure EXTI Lines in range from 0 to 31 */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+#if defined(EXTI_IMR2_IM36)
+ /* De-configure EXTI Lines in range from 32 to 63 */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+#endif /* EXTI_IMR2_IM36 */
}
return status;
}
+
/**
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
@@ -185,7 +266,9 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
-
+#if defined(EXTI_IMR2_IM36)
+ EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE;
+#endif /* EXTI_IMR2_IM36 */
EXTI_InitStruct->LineCommand = DISABLE;
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_gpio.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_gpio.c
index acd124ae1..9eb83e4b5 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_gpio.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_gpio.c
@@ -100,7 +100,7 @@
* - SUCCESS: GPIO registers are de-initialized
* - ERROR: Wrong GPIO Port
*/
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx)
{
ErrorStatus status = SUCCESS;
@@ -165,19 +165,16 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
- pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+ pinpos = 0;
/* Configure the port pins */
- while (((GPIO_InitStruct->Pin) >> pinpos) != 0U)
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
{
/* Get current io position */
- currentpin = (GPIO_InitStruct->Pin) & (1UL << pinpos);
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
- if (currentpin != 0U)
+ if (currentpin != 0x00u)
{
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
@@ -185,6 +182,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
}
/* Pull-up Pull down resistor configuration*/
@@ -196,7 +199,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
/* Speed mode configuration */
- if (POSITION_VAL(currentpin) < 8U)
+ if (currentpin < LL_GPIO_PIN_8)
{
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
@@ -205,19 +208,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
return (SUCCESS);
}
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_i2c.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_i2c.c
index 50a2c7b62..1529b7ecd 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_i2c.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_i2c.c
@@ -30,7 +30,7 @@
* @{
*/
-#if defined (I2C1)
+#if defined (I2C1) || defined(I2C2)
/** @defgroup I2C_LL I2C
* @{
@@ -98,6 +98,17 @@ ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
}
+#if defined(I2C2)
+ else if (I2Cx == I2C2)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ }
+#endif /* I2C2 */
else
{
status = ERROR;
@@ -206,7 +217,7 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
* @}
*/
-#endif /* I2C1 */
+#endif /* I2C1 || I2C2 */
/**
* @}
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rcc.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rcc.c
index c1ef0f7ca..af292db99 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rcc.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rcc.c
@@ -23,7 +23,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32C0xx_LL_Driver
* @{
*/
@@ -43,9 +43,12 @@
*/
#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ADC_CLKSOURCE)
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)
+#if defined (USB_DRD_FS)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USB_CLKSOURCE)
+#endif /* USB_DRD_FS */
/**
* @}
@@ -58,9 +61,6 @@
uint32_t RCC_GetSystemClockFreq(void);
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-uint32_t RCC_PLL_GetFreqDomain_ADC(void);
-uint32_t RCC_PLL_GetFreqDomain_I2S1(void);
/**
* @}
*/
@@ -214,8 +214,10 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
* @brief Return I2Cx clock frequency
* @param I2CxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
* @retval I2C clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+ * @note (*) peripheral not available on all devices
*/
uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
{
@@ -246,9 +248,30 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
break;
}
}
- else
+#if defined(I2C2)
+ else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
{
+ /* I2C2 CLK clock frequency */
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_HSIKER: /* I2C2 Clock is HSI Kernel */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2c_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
+ default:
+ i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
}
+#endif /* I2C2 */
return i2c_frequency;
}
@@ -273,7 +296,10 @@ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
switch (LL_RCC_GetI2SClockSource(I2SxSource))
{
case LL_RCC_I2S1_CLKSOURCE_HSIKER: /* I2S1 Clock is HSI Kernel */
- i2s_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2s_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
break;
case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
@@ -312,7 +338,10 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
adc_frequency = RCC_GetSystemClockFreq();
break;
case LL_RCC_ADC_CLKSOURCE_HSIKER : /* HSI clock Kernel used as ADC clock source */
- adc_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ adc_frequency = (HSI_VALUE / ((LL_RCC_HSIKER_GetDivider() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ }
break;
default:
adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
@@ -362,6 +391,50 @@ uint32_t LL_RCC_GetRTCClockFreq(void)
return rtc_frequency;
}
+#if defined(USB_DRD_FS)
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) is not ready
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+#if defined(RCC_HSI48_SUPPORT)
+ case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
+ if (LL_RCC_HSI48_IsReady() != 0U)
+ {
+ usb_frequency = HSI48_VALUE;
+ }
+ break;
+#endif /* RCC_HSI48_SUPPORT */
+
+ case LL_RCC_USB_CLKSOURCE_HSE: /* HSE used as USB clock source */
+ if (LL_RCC_HSE_IsReady() != 0U)
+ {
+ usb_frequency = HSE_VALUE;
+ }
+ break;
+
+ default:
+ usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return usb_frequency;
+}
+#endif /* USB_DRD_FS */
+
/**
* @}
*/
@@ -382,6 +455,9 @@ uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency;
uint32_t hsidiv;
+#if defined(RCC_CR_SYSDIV)
+ uint32_t sysdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
+#endif /* RCC_CR_SYSDIV */
/* Get SYSCLK source -------------------------------------------------------*/
switch (LL_RCC_GetSysClkSource())
@@ -389,12 +465,34 @@ uint32_t RCC_GetSystemClockFreq(void)
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
frequency = HSE_VALUE;
break;
+
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
+ frequency = (HSI_VALUE / hsidiv);
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_LSE: /* LSE used as system clock source */
+ frequency = LSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_LSI: /* LSI used as system clock source */
+ frequency = LSI_VALUE;
+ break;
+
+#if defined(RCC_HSI48_SUPPORT)
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSIUSB48: /* HSIUSB48 used as system clock source */
+ frequency = HSI48_VALUE;
+ break;
+#endif /* RCC_HSI48_SUPPORT */
+
default:
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
frequency = (HSI_VALUE / hsidiv);
break;
}
+#if defined(RCC_CR_SYSDIV)
+ frequency = frequency / sysdiv;
+#endif /* RCC_CR_SYSDIV */
return frequency;
}
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rtc.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rtc.c
index 804a96d20..0b2a5e63f 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rtc.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_rtc.c
@@ -24,7 +24,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32C0xx_LL_Driver
* @{
@@ -376,12 +376,14 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date
/* Check the input parameters format */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
- LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month,
+ RTC_DateStruct->Year);
}
else
{
LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
- __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
}
/* Exit Initialization mode */
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_spi.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_spi.c
index cbfaa2580..065572255 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_spi.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_spi.c
@@ -130,7 +130,7 @@
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
@@ -149,6 +149,18 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
status = SUCCESS;
}
#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
return status;
}
@@ -343,7 +355,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
{
return LL_SPI_DeInit(SPIx);
}
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_tim.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_tim.c
index c71b14d64..8f5ded0c4 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_tim.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_tim.c
@@ -66,8 +66,8 @@
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
@@ -706,6 +706,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -718,8 +720,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
@@ -773,8 +773,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -802,8 +800,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -852,8 +852,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -881,8 +879,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -931,8 +931,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -960,8 +958,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1010,8 +1010,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1039,7 +1037,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
/* Set the Output Idle state */
@@ -1306,7 +1303,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
- /* Select the Polarity and set the CC2E Bit */
+ /* Select the Polarity and set the CC4E Bit */
MODIFY_REG(TIMx->CCER,
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_usart.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_usart.c
index c43ba5f2d..dc9124848 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_usart.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_usart.c
@@ -238,7 +238,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USA
}
else if (USARTx == USART2)
{
- /* USART2 clock is PCLK */
+ /* USART2 clock is PCLK1 */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
}
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_usb.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_usb.c
new file mode 100644
index 000000000..c53d95a15
--- /dev/null
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_usb.c
@@ -0,0 +1,1485 @@
+/**
+ ******************************************************************************
+ * @file stm32c0xx_ll_usb.c
+ * @author MCD Application Team
+ * @brief USB Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
+
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+ @endverbatim
+
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_LL_USB_DRIVER
+ * @{
+ */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB_DRD_FS)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx);
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx,
+ USB_DRD_HCTypeDef *hc,
+ uint32_t ch_reg,
+ uint32_t *len);
+
+static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx,
+ USB_DRD_HCTypeDef *hc,
+ uint32_t len);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+/**
+ * @brief Reset the USB Core (needed after USB clock settings change)
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx)
+{
+ /* Disable Host Mode */
+ USBx->CNTR &= ~USB_CNTR_HOST;
+
+ /* Force Reset IP */
+ USBx->CNTR |= USB_CNTR_USBRST;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the USB Core
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg)
+{
+ HAL_StatusTypeDef ret;
+ UNUSED(cfg);
+
+ if (USBx == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Reset after a PHY select */
+ ret = USB_CoreReset(USBx);
+
+ /* Clear pending interrupts */
+ USBx->ISTR = 0U;
+
+ return ret;
+}
+
+/**
+ * @brief USB_EnableGlobalInt
+ * Enables the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx)
+{
+ uint32_t winterruptmask;
+
+ /* Clear pending interrupts */
+ USBx->ISTR = 0U;
+
+ /* Set winterruptmask variable */
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
+ USB_CNTR_SUSPM | USB_CNTR_ERRM |
+ USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+ /* Set interrupt mask */
+ USBx->CNTR = winterruptmask;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DisableGlobalInt
+ * Disable the controller's Global Int in the AHB Config reg
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx)
+{
+ uint32_t winterruptmask;
+
+ /* Set winterruptmask variable */
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
+ USB_CNTR_SUSPM | USB_CNTR_ERRM |
+ USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+ /* Clear interrupt mask */
+ USBx->CNTR &= ~winterruptmask;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetCurrentMode Set functional mode
+ * @param USBx Selected device
+ * @param mode current core mode
+ * This parameter can be one of the these values:
+ * @arg USB_DEVICE_MODE Peripheral mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode)
+{
+ if (mode == USB_DEVICE_MODE)
+ {
+ USBx->CNTR &= ~USB_CNTR_HOST;
+ }
+ else if (mode == USB_HOST_MODE)
+ {
+ USBx->CNTR |= USB_CNTR_HOST;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevInit Initializes the USB controller registers
+ * for device mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg)
+{
+ HAL_StatusTypeDef ret;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(cfg);
+
+ /* Force Reset */
+ USBx->CNTR = USB_CNTR_USBRST;
+
+ /* Release Reset */
+ USBx->CNTR &= ~USB_CNTR_USBRST;
+
+ /* Set the Device Mode */
+ ret = USB_SetCurrentMode(USBx, USB_DEVICE_MODE);
+
+ /* Clear pending interrupts */
+ USBx->ISTR = 0U;
+
+ return ret;
+}
+
+/**
+ * @brief USB_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx : Selected device
+ * @param num : FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(num);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+
+#if defined (HAL_PCD_MODULE_ENABLED)
+/**
+ * @brief Activate and configure an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t wEpRegVal;
+
+ wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
+
+ /* initialize Endpoint */
+ switch (ep->type)
+ {
+ case EP_TYPE_CTRL:
+ wEpRegVal |= USB_EP_CONTROL;
+ break;
+
+ case EP_TYPE_BULK:
+ wEpRegVal |= USB_EP_BULK;
+ break;
+
+ case EP_TYPE_INTR:
+ wEpRegVal |= USB_EP_INTERRUPT;
+ break;
+
+ case EP_TYPE_ISOC:
+ wEpRegVal |= USB_EP_ISOCHRONOUS;
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_VTRX | USB_EP_VTTX));
+
+ PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
+
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in != 0U)
+ {
+ /*Set the endpoint Transmit buffer address */
+ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ }
+ else
+ {
+ /* Set the endpoint Receive buffer address */
+ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+
+ /* Set the endpoint Receive buffer counter */
+ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ if (ep->num == 0U)
+ {
+ /* Configure VALID status for EP0 */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+ else
+ {
+ /* Configure NAK status for OUT Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
+ else
+ {
+ if (ep->type == EP_TYPE_BULK)
+ {
+ /* Set bulk endpoint as double buffered */
+ PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+ }
+ else
+ {
+ /* Set the ISOC endpoint in double buffer mode */
+ PCD_CLEAR_EP_KIND(USBx, ep->num);
+ }
+
+ /* Set buffer address for double buffered mode */
+ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
+
+ if (ep->is_in == 0U)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT */
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT */
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ return ret;
+}
+
+/**
+ * @brief De-activate and de-initialize an endpoint
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
+{
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in != 0U)
+ {
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ /* Configure DISABLE status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+
+ else
+ {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ /* Configure DISABLE status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
+ else
+ {
+ if (ep->is_in == 0U)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(USBx, ep->num);
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ PCD_RX_DTOG(USBx, ep->num);
+
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPStartXfer setup and starts a transfer over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
+{
+ uint32_t len;
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ uint16_t pmabuffer;
+ uint16_t wEPVal;
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /*Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ }
+ else
+ {
+ len = ep->xfer_len;
+ }
+
+ /* configure and validate Tx endpoint */
+ if (ep->doublebuffer == 0U)
+ {
+ USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
+ PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else
+ {
+ /* double buffer bulk management */
+ if (ep->type == EP_TYPE_BULK)
+ {
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ /* enable double buffer */
+ PCD_SET_BULK_EP_DBUF(USBx, ep->num);
+
+ /* each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the two first buffer in the Buffer0 & Buffer1 */
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ else
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }
+ /* auto Switch to single buffer mode when transfer xfer_len_db;
+
+ /* disable double buffer mode for Bulk endpoint */
+ PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
+
+ /* Set Tx count with nbre of byte to be transmitted */
+ PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }
+ else /* manage isochronous double buffer IN mode */
+ {
+ /* each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the data buffer */
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ else
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
+ }
+ else /* OUT endpoint */
+ {
+ if (ep->doublebuffer == 0U)
+ {
+ /* Multi packet transfer */
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len -= len;
+ }
+ else
+ {
+ len = ep->xfer_len;
+ ep->xfer_len = 0U;
+ }
+ /* configure and validate Rx endpoint */
+ PCD_SET_EP_RX_CNT(USBx, ep->num, len);
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else
+ {
+ /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
+ /* Set the Double buffer counter */
+ if (ep->type == EP_TYPE_BULK)
+ {
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
+
+ /* Coming from ISR */
+ if (ep->xfer_count != 0U)
+ {
+ /* update last value to check if there is blocking state */
+ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num);
+
+ /*Blocking State */
+ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
+ (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
+ {
+ PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
+ }
+ }
+ }
+ /* iso out double */
+ else if (ep->type == EP_TYPE_ISOC)
+ {
+ /* Multi packet transfer */
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len -= len;
+ }
+ else
+ {
+ len = ep->xfer_len;
+ ep->xfer_len = 0U;
+ }
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief USB_EPSetStall set a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
+{
+ if (ep->is_in != 0U)
+ {
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
+ }
+ else
+ {
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPClearStall Clear a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
+{
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in != 0U)
+ {
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ /* Configure VALID status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPStoptXfer Stop transfer on an EP
+ * @param USBx usb device instance
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
+{
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ }
+ }
+ else /* OUT endpoint */
+ {
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
+ else
+ {
+ /* Configure RX Endpoint to disabled state */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+#endif /* defined (HAL_PCD_MODULE_ENABLED) */
+
+/**
+ * @brief USB_StopDevice Stop the usb device mode
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx)
+{
+ /* disable all interrupts and force USB reset */
+ USBx->CNTR = USB_CNTR_USBRST;
+
+ /* clear interrupt status register */
+ USBx->ISTR = 0U;
+
+ /* switch-off device */
+ USBx->CNTR = (USB_CNTR_USBRST | USB_CNTR_PDWN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetDevAddress Stop the usb device mode
+ * @param USBx Selected device
+ * @param address new device address to be assigned
+ * This parameter can be a value from 0 to 255
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address)
+{
+ if (address == 0U)
+ {
+ /* set device address and enable function */
+ USBx->DADDR = USB_DADDR_EF;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx)
+{
+ /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
+ USBx->BCDR |= USB_BCDR_DPPU;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx)
+{
+ /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
+ USBx->BCDR &= ~(USB_BCDR_DPPU);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadInterrupts return the global USB interrupt status
+ * @param USBx Selected device
+ * @retval USB Global Interrupt status
+ */
+uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx)
+{
+ uint32_t tmpreg;
+
+ tmpreg = USBx->ISTR;
+ return tmpreg;
+}
+
+/**
+ * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx)
+{
+ USBx->CNTR |= USB_CNTR_L2RES;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx)
+{
+ USBx->CNTR &= ~USB_CNTR_L2RES;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx USB peripheral instance register address.
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ * @retval None
+ */
+void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ UNUSED(USBx);
+ uint32_t WrVal;
+ uint32_t count;
+ __IO uint32_t *pdwVal;
+ uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U;
+ /* Due to the PMA access 32bit only so the last non word data should be processed alone */
+ uint16_t remaining_bytes = wNBytes % 4U;
+ uint8_t *pBuf = pbUsrBuf;
+
+ /* Check if there is a remaining byte */
+ if (remaining_bytes != 0U)
+ {
+ NbWords--;
+ }
+
+ /* Get the PMA Buffer pointer */
+ pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr);
+
+ /* Write the Calculated Word into the PMA related Buffer */
+ for (count = NbWords; count != 0U; count--)
+ {
+ *pdwVal = __UNALIGNED_UINT32_READ(pBuf);
+ pdwVal++;
+ /* Increment pBuf 4 Time as Word Increment */
+ pBuf++;
+ pBuf++;
+ pBuf++;
+ pBuf++;
+ }
+
+ /* When Number of data is not word aligned, write the remaining Byte */
+ if (remaining_bytes != 0U)
+ {
+ WrVal = 0U;
+
+ do
+ {
+ WrVal |= (uint32_t)(*(uint8_t *)pBuf) << (8U * count);
+ count++;
+ pBuf++;
+ remaining_bytes--;
+ } while (remaining_bytes != 0U);
+
+ *pdwVal = WrVal;
+ }
+}
+
+/**
+ * @brief Copy data from packet memory area (PMA) to user memory buffer
+ * @param USBx USB peripheral instance register address.
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ * @retval None
+ */
+void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ UNUSED(USBx);
+ uint32_t count;
+ uint32_t RdVal;
+ __IO uint32_t *pdwVal;
+ uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U;
+ /*Due to the PMA access 32bit only so the last non word data should be processed alone */
+ uint16_t remaining_bytes = wNBytes % 4U;
+ uint8_t *pBuf = pbUsrBuf;
+
+ /* Get the PMA Buffer pointer */
+ pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr);
+
+ /* if nbre of byte is not word aligned decrement the nbre of word*/
+ if (remaining_bytes != 0U)
+ {
+ NbWords--;
+ }
+
+ /*Read the Calculated Word From the PMA related Buffer*/
+ for (count = NbWords; count != 0U; count--)
+ {
+ __UNALIGNED_UINT32_WRITE(pBuf, *pdwVal);
+
+ pdwVal++;
+ pBuf++;
+ pBuf++;
+ pBuf++;
+ pBuf++;
+ }
+
+ /*When Number of data is not word aligned, read the remaining byte*/
+ if (remaining_bytes != 0U)
+ {
+ RdVal = *(__IO uint32_t *)pdwVal;
+
+ do
+ {
+ *(uint8_t *)pBuf = (uint8_t)(RdVal >> (8U * (uint8_t)(count)));
+ count++;
+ pBuf++;
+ remaining_bytes--;
+ } while (remaining_bytes != 0U);
+ }
+}
+
+
+/*------------------------------------------------------------------------*/
+/* HOST API */
+/*------------------------------------------------------------------------*/
+
+/**
+ * @brief USB_HostInit Initializes the USB DRD controller registers
+ * for Host mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg)
+{
+ UNUSED(cfg);
+
+ /* Clear All Pending Interrupt */
+ USBx->ISTR = 0U;
+
+ /* Disable all interrupts */
+ USBx->CNTR &= ~(USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM |
+ USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON |
+ USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM);
+
+ /* Clear All Pending Interrupt */
+ USBx->ISTR = 0U;
+
+ /* Set the PullDown on the PHY */
+ USBx->BCDR |= USB_BCDR_DPPD;
+
+ /* Enable Global interrupt */
+ USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM |
+ USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON |
+ USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief USB_DRD_ResetPort : Reset Host Port
+ * @param USBx Selected device
+ * @retval HAL status
+ * @note (1)The application must wait at least 10 ms
+ * before clearing the reset bit.
+ */
+HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx)
+{
+ /* Force USB Reset */
+ USBx->CNTR |= USB_CNTR_USBRST;
+ HAL_Delay(100);
+ /* Release USB Reset */
+ USBx->CNTR &= ~USB_CNTR_USBRST;
+ HAL_Delay(30);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Return Host Core speed
+ * @param USBx Selected device
+ * @retval speed Host speed
+ * This parameter can be one of these values
+ * @arg USB_DRD_SPEED_FS Full speed mode
+ * @arg USB_DRD_SPEED_LS Low speed mode
+ */
+uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx)
+{
+ if ((USBx->ISTR & USB_ISTR_LS_DCONN) != 0U)
+ {
+ return USB_DRD_SPEED_LS;
+ }
+ else
+ {
+ return USB_DRD_SPEED_FS;
+ }
+}
+
+/**
+ * @brief Return Host Current Frame number
+ * @param USBx Selected device
+ * @retval current frame number
+ */
+uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx)
+{
+ return USBx->FNR & 0x7FFU;
+}
+
+/**
+ * @brief Set the channel Kind (Single/double buffer mode)
+ * @param USBx Selected device
+ * @param phy_ch_num Selected device
+ * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx,
+ uint8_t phy_ch_num, uint8_t db_state)
+{
+ uint32_t tmp;
+
+ if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE))
+ {
+ tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK;
+ }
+ else
+ {
+ tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK;
+ }
+
+ /* Set the device speed in case using HUB FS with device LS */
+ USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize a host channel
+ * @param USBx Selected device
+ * @param phy_ch_num Channel number
+ * This parameter can be a value from 1 to 15
+ * @param epnum Endpoint number
+ * This parameter can be a value from 1 to 15
+ * @param dev_address Current device address
+ * This parameter can be a value from 0 to 255
+ * @param speed Current device speed
+ * This parameter can be one of these values:
+ * @arg USB_DRD_SPEED_FULL Full speed mode
+ * @arg USB_DRD_SPEED_LOW Low speed mode
+ * @param ep_type Endpoint Type
+ * This parameter can be one of these values:
+ * @arg EP_TYPE_CTRL Control type
+ * @arg EP_TYPE_ISOC Isochronous type
+ * @arg EP_TYPE_BULK Bulk type
+ * @arg EP_TYPE_INTR Interrupt type
+ * @param mps Max Packet Size
+ * This parameter can be a value from 0 to 32K
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t wChRegVal;
+ uint32_t HostCoreSpeed;
+
+ UNUSED(mps);
+
+ wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK;
+
+ /* Initialize host Channel */
+ switch (ep_type)
+ {
+ case EP_TYPE_CTRL:
+ wChRegVal |= USB_EP_CONTROL;
+ break;
+
+ case EP_TYPE_BULK:
+ wChRegVal |= USB_EP_BULK;
+ break;
+
+ case EP_TYPE_INTR:
+ wChRegVal |= USB_EP_INTERRUPT;
+ break;
+
+ case EP_TYPE_ISOC:
+ wChRegVal |= USB_EP_ISOCHRONOUS;
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* Clear device address, Endpoint number and Low Speed Endpoint fields */
+ wChRegVal &= ~(USB_CHEP_DEVADDR |
+ USB_CHEP_ADDR |
+ USB_CHEP_LSEP |
+ USB_CHEP_NAK |
+ USB_CHEP_KIND |
+ USB_CHEP_ERRTX |
+ USB_CHEP_ERRRX |
+ (0xFU << 27));
+
+ /* Set device address and Endpoint number associated to the channel */
+ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) |
+ ((uint32_t)epnum & 0x0FU));
+
+ /* Get Host core Speed */
+ HostCoreSpeed = USB_GetHostSpeed(USBx);
+
+ /* Set the device speed in case using HUB FS with device LS */
+ if ((speed == USB_DRD_SPEED_LS) && (HostCoreSpeed == USB_DRD_SPEED_FS))
+ {
+ wChRegVal |= USB_CHEP_LSEP;
+ }
+
+ /* Update the channel register value */
+ USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX));
+
+ return ret;
+}
+
+/**
+ * @brief Start a transfer over a host channel
+ * @param USBx Selected device
+ * @param hc pointer to host channel structure
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc)
+{
+ uint32_t len;
+ uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num;
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ uint32_t ch_reg = USB_DRD_GET_CHEP(USBx, phy_ch_num);
+#endif /* USE_USB_DOUBLE_BUFFER */
+
+ if (hc->ch_dir == CH_IN_DIR) /* In Channel */
+ {
+ /* Multi packet transfer */
+ if (hc->xfer_len > hc->max_packet)
+ {
+ len = hc->max_packet;
+ }
+ else
+ {
+ len = hc->xfer_len;
+ }
+
+ if (hc->doublebuffer == 0U)
+ {
+ if ((hc->ep_type == EP_TYPE_BULK) ||
+ (hc->ep_type == EP_TYPE_INTR))
+ {
+ USB_DRD_CLEAR_RX_DTOG(USBx, phy_ch_num);
+
+ /* Set Data PID */
+ if (hc->data_pid == HC_PID_DATA1)
+ {
+ USB_DRD_RX_DTOG(USBx, phy_ch_num);
+ }
+ }
+
+ /* Set RX buffer count */
+ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len);
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else if (hc->ep_type == EP_TYPE_BULK)
+ {
+ /* Double buffer activated */
+ if ((hc->xfer_len > hc->max_packet))
+ {
+ (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE);
+
+ /* Set the Double buffer counter */
+ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len);
+ USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len);
+ }
+ else /* Switch to single buffer mode */
+ {
+ (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE);
+
+ /* Set RX buffer count */
+ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len);
+ }
+ }
+ else /* Isochronous */
+ {
+ /* Set the Double buffer counter */
+ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len);
+ USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len);
+ }
+#endif /* USE_USB_DOUBLE_BUFFER */
+
+ /* Enable host channel */
+ USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID);
+ }
+ else /* Out Channel */
+ {
+ /* Multi packet transfer */
+ if (hc->xfer_len > hc->max_packet)
+ {
+ len = hc->max_packet;
+ }
+ else
+ {
+ len = hc->xfer_len;
+ }
+
+ /* Configure and validate Tx endpoint */
+ if (hc->doublebuffer == 0U)
+ {
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len);
+ USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len);
+
+ /* SET PID SETUP */
+ if ((hc->data_pid) == HC_PID_SETUP)
+ {
+ USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num);
+ }
+
+ if ((hc->ep_type == EP_TYPE_BULK) ||
+ (hc->ep_type == EP_TYPE_INTR))
+ {
+ USB_DRD_CLEAR_TX_DTOG(USBx, phy_ch_num);
+
+ /* Set Data PID */
+ if (hc->data_pid == HC_PID_DATA1)
+ {
+ USB_DRD_TX_DTOG(USBx, phy_ch_num);
+ }
+ }
+ }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ else if (hc->ep_type == EP_TYPE_BULK)
+ {
+ (void)USB_HC_BULK_DB_StartXfer(USBx, hc, ch_reg, &len);
+ }
+ else
+ {
+ (void)USB_HC_ISO_DB_StartXfer(USBx, hc, len);
+ }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+ /* Enable host channel */
+ USB_DRD_SET_CHEP_TX_STATUS(USBx, hc->phy_ch_num, USB_CH_TX_VALID);
+ }
+
+ return HAL_OK;
+}
+
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+/**
+ * @brief Start Transfer of Channel isochronous out double buffer
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @param len Transfer Length
+ * @retval HAL state
+ */
+static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx,
+ USB_DRD_HCTypeDef *hc,
+ uint32_t len)
+{
+ uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num;
+
+ /* check the DTOG_TX to determine in which buffer we should write */
+ if ((USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_DTOG_TX) != 0U)
+ {
+ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, len);
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)len);
+ }
+ else
+ {
+ /* DTOGTX=0 */
+ /* Set the Double buffer counter for pmabuffer0 */
+ USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, len);
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)len);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Transfer of Channel bulk out double buffer
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @param ch_reg snapshot of the CHEPR register
+ * @param len Transfer Length
+ * @retval HAL state
+ */
+static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx,
+ USB_DRD_HCTypeDef *hc,
+ uint32_t ch_reg,
+ uint32_t *len)
+{
+ uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num;
+
+ /* -Double Buffer Mangement- */
+ if (hc->xfer_len_db > hc->max_packet)
+ {
+ /* enable double buffer mode */
+ (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE);
+ *len = hc->max_packet;
+ hc->xfer_len_db -= *len;
+
+ /* Prepare two buffer before enabling host */
+ if ((ch_reg & USB_CH_DTOG_TX) == 0U)
+ {
+ /* Write Buffer0 */
+ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len);
+ }
+ else
+ {
+ /* Write Buffer1 */
+ USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len);
+ }
+
+ hc->xfer_buff += *len;
+
+ /* Multi packet transfer */
+ if (hc->xfer_len_db > hc->max_packet)
+ {
+ hc->xfer_len_db -= *len;
+ }
+ else
+ {
+ *len = hc->xfer_len_db;
+ hc->xfer_len_db = 0U;
+ }
+
+ if ((ch_reg & USB_CH_DTOG_TX) == 0U)
+ {
+ /* Write Buffer1 */
+ USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len);
+ }
+ else
+ {
+ /* Write Buffer0 */
+ USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len);
+ }
+ }
+ else
+ {
+ /* Disable bulk double buffer mode */
+ (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE);
+ USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len);
+ USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)*len);
+ }
+
+ return HAL_OK;
+}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+
+/**
+ * @brief Halt a host channel in
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
+{
+ /* Set disable to Channel */
+ USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Halt a host channel out
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
+ * This parameter can be a value from 1 to 15
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
+{
+ /* Set disable to Channel */
+ USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop Host Core
+ * @param USBx Selected device
+ * @retval HAL state
+ */
+HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx)
+{
+ USBx->ISTR &= ~(USB_ISTR_DIR | USB_ISTR_L1REQ |
+ USB_ISTR_ESOF | USB_ISTR_SOF |
+ USB_ISTR_RESET | USB_ISTR_DCON |
+ USB_ISTR_SUSP | USB_ISTR_WKUP |
+ USB_ISTR_ERR | USB_ISTR_PMAOVR |
+ USB_ISTR_CTR);
+
+ /* Set PowerDown */
+ USBx->CNTR |= USB_CNTR_PDWN;
+
+ /* Force a Reset */
+ USBx->CNTR |= USB_CNTR_USBRST;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_DRD_FS) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
diff --git a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_utils.c b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_utils.c
index cb3e3c54f..0a94d18e7 100644
--- a/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_utils.c
+++ b/stm32cube/stm32c0xx/drivers/src/stm32c0xx_ll_utils.c
@@ -42,10 +42,6 @@
*/
#define UTILS_MAX_FREQUENCY 48000000U /*!< Maximum frequency for system clock, in Hz */
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
-#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
-
/* Defines used for FLASH latency according to HCLK Frequency */
#define UTILS_SCALE1_LATENCY1_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
#define UTILS_SCALE1_LATENCY2_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
@@ -54,51 +50,6 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
- * @{
- */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_HCLK_DIV_1) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_2) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_4) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_8) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_16) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_64) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_128) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_256) \
- || ((__VALUE__) == LL_RCC_HCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_HSI_DIV(__VALUE__) (((__VALUE__) == LL_RCC_HSI_DIV_1) \
- || ((__VALUE__) == LL_RCC_HSI_DIV_2) \
- || ((__VALUE__) == LL_RCC_HSI_DIV_4) \
- || ((__VALUE__) == LL_RCC_HSI_DIV_8) \
- || ((__VALUE__) == LL_RCC_HSI_DIV_16) \
- || ((__VALUE__) == LL_RCC_HSI_DIV_32) \
- || ((__VALUE__) == LL_RCC_HSI_DIV_64) \
- || ((__VALUE__) == LL_RCC_HSI_DIV_128))
-
-#define IS_LL_UTILS_HSIKER_DIV(__VALUE__) (((__VALUE__) == LL_RCC_HSIKER_DIV_1) \
- || ((__VALUE__) == LL_RCC_HSIKER_DIV_2) \
- || ((__VALUE__) == LL_RCC_HSIKER_DIV_3) \
- || ((__VALUE__) == LL_RCC_HSIKER_DIV_4) \
- || ((__VALUE__) == LL_RCC_HSIKER_DIV_5) \
- || ((__VALUE__) == LL_RCC_HSIKER_DIV_6) \
- || ((__VALUE__) == LL_RCC_HSIKER_DIV_7) \
- || ((__VALUE__) == LL_RCC_HSIKER_DIV_8))
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
- || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN)\
- && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
- * @}
- */
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UTILS_LL_Exported_Functions
@@ -205,8 +156,6 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
SystemCoreClock = HCLKFrequency;
}
-
-
/**
* @}
*/
@@ -263,7 +212,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
timeout--;
} while ((getlatency != latency) && (timeout > 0U));
- if(getlatency != latency)
+ if (getlatency != latency)
{
status = ERROR;
}
@@ -275,7 +224,6 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
return status;
}
-
/**
* @}
*/
diff --git a/stm32cube/stm32c0xx/release_note.html b/stm32cube/stm32c0xx/release_note.html
index ecd828274..2cc9d0cb6 100644
--- a/stm32cube/stm32c0xx/release_note.html
+++ b/stm32cube/stm32c0xx/release_note.html
@@ -11,8 +11,11 @@
div.columns{display: flex; gap: min(4vw, 1.5em);}
div.column{flex: auto; overflow-x: auto;}
div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
- ul.task-list{list-style: none;}
+ /* The extra [class] is a hack that increases specificity enough to
+ override a similar rule in reveal.js */
+ ul.task-list[class]{list-style: none;}
ul.task-list li input[type="checkbox"] {
+ font-size: inherit;
width: 0.8em;
margin: 0 0.8em 0.2em -1.6em;
vertical-align: middle;
@@ -62,22 +65,315 @@
Purpose
CodeSonar® static analysis tool, and developed in compliance with MISRA
C® guidelines. Reports are available on demand.
The drivers provided within this package
-support the STM32C031/STM32C011
+support the STM32C031/STM32C011/C071
lines.
Update History
-
-
+
+
Main Changes
+
First official release of STM32CubeC0 Firmware
+Package to support STM32CubeC071xx
+devices
+
+
Contents
+
Features
+
STM32CubeC0 gathers in one single package all the generic embedded
+software components required to develop an application on STM32C0
+microcontrollers.
+
+
Production–ready HAL and LL API drivers, checked with Coverity®
+static analysis tool, and developed in compliance with MISRA C®
+guidelines.
+
CMSIS CORE, DSP and RTOS software components.
+
Consistent set of middleware components (Azure® RTOS USBX,
+FileX/LevelX, ThreadX, mcuboot, mbed-crypto, and OpenBootloader).
+
Up to 187 examples and applications for easy
+understanding, compatible with STM32CubeMX to facilitate the
+configuration through a graphical tool.
+
New Templates_Board project for NUCLEO-C071RB demonstrating the
+STM32CubeMX “Start my project from ST Board” providing an easy access to
+ST boards’ features.
+
+
CMSIS Device Updates
+
+
Support of STM32C071xx devices
+
Update CMSIS devices to include latest corrections
+
+
HAL/LL Drivers Updates
+
+
HAL and LL drivers Official Release for STM32C071xx
+
Add USB HAL and LL drivers for STM32C071xx devices
+
General updates to fix known defects and implementation
+enhancements
+
+
BSP Drivers Updates
+
+
Update STM32C0xx_Nucleo BSP Driver to support NUCLEO-C071RB board
+for STM32UC071xx devices
+
General updates to fix known defects and implementation
+enhancements
+
+
Midlware Updates
+
+
Major update in AzureRTOS Middlewares (new version V6.4.0)
+
Add the AzureRTOS USBX middleware component
+
Add mbed-crypto and mcuboot Middleware
+
+
Projects
+
+
Add 75 new projects on NUCLEO-C071RB board:
+
+
14 Applications
+
58 examples
+
1 HAL Templates
+
1 LL Templates
+
1 Board Templates
+
+
+
The STM32CubeC0 Firmware package comes with template
+running on STMicroelectronics boards, organized by board and provided
+with preconfigured projects for the main supported toolchains. The
+exhaustive list of projects is provided in this table STM32CubeProjectsList.html
Maintenance Release of STM32CubeC0 Firmware Package
@@ -166,8 +462,8 @@
Main Changes
Update of AzureRtos Middleware to new version V6.2.0
Update of OpenBootloader to new version V6.1.0
-
Contents
-
Projects
+
Contents
+
Projects
The STM32CubeC0 Firmware package comes with template
running on STMicroelectronics boards, organized by board and provided
with preconfigured projects for the main supported toolchains. The
@@ -192,7 +488,7 @@
Projects
-
Components
+
Components
The Project categories flagged by “” have changed since the previous release.
“” are new.
@@ -305,8 +601,8 @@
Components
-
Development Toolchains and
-Compilers
+
Development Toolchains
+and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9 + ST-LINK,
patch available here:
@@ -325,14 +621,15 @@
Development Toolchains and
STM32CubeIDE v1.12.0 using GCC10
-
Supported Devices and boards
+
Supported Devices and
+boards
STM32C031 and STM32C011 devices Rev A
NUCLEO-C031C6 board rev.B
STM32C0116-DK board rev.B
STM32C0316-DK board rev.B
-
Dependencies
+
Dependencies
STM32CubeMX V6.9.0
@@ -340,11 +637,11 @@
Dependencies
version V6.9.0.
-
Known Limitations
+
Known Limitations
Not applicable
-
Backward Compatibility
+
Backward Compatibility
HAL_SYSCFG_GetPinBinding() and LL_SYSCFG_GetConfigPinMux() are
updated.
@@ -356,7 +653,7 @@
Backward Compatibility
-
Main Changes
+
Main Changes
Patch Release of STM32CubeC0 Firmware Package
@@ -369,8 +666,8 @@
Main Changes
Update RCC LL driver by adding missing AHB Prescaler.
-
Contents
-
Projects
+
Contents
+
Projects
The STM32CubeC0 Firmware package comes with template
running on STMicroelectronics boards, organized by board and provided
with preconfigured projects for the main supported toolchains. The
@@ -396,7 +693,7 @@
Projects
-
Components
+
Components
The Project categories flagged by “” have changed since the previous release.
“” are new.
@@ -507,13 +804,13 @@
Components
-
Main Changes
+
Main Changes
First Official Release of STM32CubeC0 Firmware Package
-
Contents
-
Projects
+
Contents
+
Projects
The STM32CubeC0 Firmware package comes with template
running on STMicroelectronics boards, organized by board and provided
with preconfigured projects for the main supported toolchains. The
@@ -538,7 +835,7 @@
Projects
-
Components
+
Components
Drivers
@@ -639,7 +936,7 @@
Components
-
Development Toolchains
+
Development Toolchains
and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9 + ST-LINK,
@@ -659,7 +956,7 @@
Development Toolchains
STM32CubeIDE v1.9.0 using GCC10
-
Supported Devices and
+
Supported Devices and
boards
STM32C031 and STM32C011 devices Rev A
@@ -667,7 +964,7 @@
Supported Devices and
STM32C0116-DK board rev.B
STM32C0316-DK board rev.B
-
Dependencies
+
Dependencies
STM32CubeMX V6.5.0
@@ -675,11 +972,11 @@
Dependencies
version V6.5.0.
-
Known Limitations
+
Known Limitations
None
-
Backward Compatibility
+
Backward Compatibility
Not applicable
diff --git a/stm32cube/stm32c0xx/soc/stm32c011xx.h b/stm32cube/stm32c0xx/soc/stm32c011xx.h
index 0b4813bf6..7ce9b55ca 100644
--- a/stm32cube/stm32c0xx/soc/stm32c011xx.h
+++ b/stm32cube/stm32c0xx/soc/stm32c011xx.h
@@ -225,7 +225,7 @@ typedef struct
__IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */
- uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */
+ uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */
__IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
__IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
@@ -421,7 +421,7 @@ typedef struct
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */
__IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */
- uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */
+ uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */
__IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
} SYSCFG_TypeDef;
@@ -498,7 +498,14 @@ typedef struct
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
-#define SRAM_SIZE_MAX (0x00001500UL) /*!< maximum SRAM size (up to 6 KBytes) */
+#define SRAM_SIZE_MAX (0x00001800UL) /*!< maximum SRAM size (up to 6 KBytes) */
+
+#define FLASH_SIZE_DEFAULT 0x8000U /*!< Flash memory default size */
+
+#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \
+ ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \
+ (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
+
/*!< Peripheral memory map */
#define APBPERIPH_BASE (PERIPH_BASE)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
@@ -546,6 +553,7 @@ typedef struct
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
@@ -606,10 +614,10 @@ typedef struct
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
@@ -1283,6 +1291,10 @@ typedef struct
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
+#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */
+#define ADC_AWD2CR_AWD2CH_21 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */
+#define ADC_AWD2CR_AWD2CH_22 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
@@ -1307,6 +1319,10 @@ typedef struct
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
+#define ADC_AWD3CR_AWD3CH_20 (0x100000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00100000 */
+#define ADC_AWD3CR_AWD3CH_21 (0x200000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00200000 */
+#define ADC_AWD3CR_AWD3CH_22 (0x400000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00400000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_Pos (0U)
@@ -1523,18 +1539,6 @@ typedef struct
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos (12U)
-#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos (13U)
-#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos (14U)
-#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos (15U)
-#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
@@ -1953,7 +1957,6 @@ typedef struct
#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
-
/******************* Bit definition for EXTI_FPR1 register ******************/
#define EXTI_FPR1_FPIF0_Pos (0U)
#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
@@ -2093,8 +2096,8 @@ typedef struct
#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
-#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
-#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR4_EXTI14_Pos (16U)
#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
@@ -2157,57 +2160,21 @@ typedef struct
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR1_IM16_Pos (16U)
-#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
-#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR1_IM17_Pos (17U)
-#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
-#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR1_IM18_Pos (18U)
-#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR1_IM20_Pos (20U)
-#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
-#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR1_IM21_Pos (21U)
-#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
-#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR1_IM22_Pos (22U)
-#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
-#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR1_IM24_Pos (24U)
-#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
-#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR1_IM26_Pos (26U)
-#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
-#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR1_IM27_Pos (27U)
-#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
-#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR1_IM28_Pos (28U)
-#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
-#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR1_IM29_Pos (29U)
-#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
-#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
-#define EXTI_IMR1_IM30_Pos (30U)
-#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
-#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
-#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
+#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
#define EXTI_IMR1_IM_Pos (0U)
-#define EXTI_IMR1_IM_Msk (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFEAFFFFF */
+#define EXTI_IMR1_IM_Msk (0x0288FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x288FFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
@@ -2272,34 +2239,17 @@ typedef struct
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
-#define EXTI_EMR1_EM21_Pos (21U)
-#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
-#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
-#define EXTI_EMR1_EM26_Pos (26U)
-#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
-#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
-#define EXTI_EMR1_EM27_Pos (27U)
-#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
-#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
-#define EXTI_EMR1_EM28_Pos (28U)
-#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
-#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
-#define EXTI_EMR1_EM29_Pos (29U)
-#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
-#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
-#define EXTI_EMR1_EM30_Pos (30U)
-#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
-#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
+
/******************************************************************************/
/* */
/* FLASH */
@@ -2384,7 +2334,7 @@ typedef struct
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
+#define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x00000078 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -2417,23 +2367,6 @@ typedef struct
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
-/******************* Bits definition for FLASH_ECCR register ****************/
-#define FLASH_ECCR_ADDR_ECC_Pos (0U)
-#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
-#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
-#define FLASH_ECCR_SYSF_ECC_Pos (20U)
-#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
-#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
-#define FLASH_ECCR_ECCCIE_Pos (24U)
-#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
-#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
-#define FLASH_ECCR_ECCC_Pos (30U)
-#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
-#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
-#define FLASH_ECCR_ECCD_Pos (31U)
-#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
-#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
-
/******************* Bits definition for FLASH_OPTR register ****************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
@@ -2441,16 +2374,16 @@ typedef struct
#define FLASH_OPTR_BOR_EN_Pos (8U)
#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk
-#define FLASH_OPTR_BORF_LEV_Pos (9U)
-#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000600 */
-#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk
-#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000200 */
-#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000400 */
-#define FLASH_OPTR_BORR_LEV_Pos (11U)
-#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001800 */
+#define FLASH_OPTR_BORR_LEV_Pos (9U)
+#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */
#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk
-#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000800 */
-#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001000 */
+#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */
+#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */
+#define FLASH_OPTR_BORF_LEV_Pos (11U)
+#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */
+#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk
+#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */
+#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP_Pos (13U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
@@ -2475,6 +2408,9 @@ typedef struct
#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
+#define FLASH_OPTR_SECURE_MUXING_EN_Pos (23U)
+#define FLASH_OPTR_SECURE_MUXING_EN_Msk (0x1UL << FLASH_OPTR_SECURE_MUXING_EN_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_SECURE_MUXING_EN FLASH_OPTR_SECURE_MUXING_EN_Msk
#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
@@ -2495,12 +2431,12 @@ typedef struct
/****************** Bits definition for FLASH_PCROP1ASR register ************/
#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U)
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */
+#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x3FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000003F */
#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk
/****************** Bits definition for FLASH_PCROP1AER register ************/
#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U)
-#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */
+#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x3FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000003F */
#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk
#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
@@ -2508,34 +2444,34 @@ typedef struct
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
-#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */
+#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000000F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
-#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */
+#define FLASH_WRP1AR_WRP1A_END_Msk (0xFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x000F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRP1BR register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
-#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */
+#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000000F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
-#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */
+#define FLASH_WRP1BR_WRP1B_END_Msk (0xFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x000F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_PCROP1BSR register ************/
#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U)
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */
+#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x3FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000003F */
#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk
/****************** Bits definition for FLASH_PCROP1BER register ************/
#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U)
-#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */
+#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x3FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000003F */
#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk
/****************** Bits definition for FLASH_SECR register *****************/
#define FLASH_SECR_SEC_SIZE_Pos (0U)
-#define FLASH_SECR_SEC_SIZE_Msk (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */
+#define FLASH_SECR_SEC_SIZE_Msk (0x1FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000001F */
#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk
#define FLASH_SECR_BOOT_LOCK_Pos (16U)
#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */
@@ -3617,7 +3553,7 @@ typedef struct
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable external WKUP pin 3 */
#define PWR_CR3_EWUP4_Pos (3U)
-#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000004 */
+#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable external WKUP pin 4 */
#define PWR_CR3_EWUP6_Pos (5U)
#define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */
@@ -3679,9 +3615,6 @@ typedef struct
#define PWR_SR2_FLASH_RDY_Pos (7U)
#define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */
#define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */
-#define PWR_SR2_REGLPF_Pos (9U)
-#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
-#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CWUF_Pos (0U)
@@ -3970,40 +3903,36 @@ typedef struct
#define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */
/*!< MCO2SEL configuration */
-#define RCC_CFGR_MCO2SEL_Pos (16U)
-#define RCC_CFGR_MCO2SEL_Msk (0xFUL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x000F0000 */
-#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [3:0] bits (Clock output selection) */
-#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00010000 */
-#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00020000 */
-#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00040000 */
-#define RCC_CFGR_MCO2SEL_3 (0x8UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_MCO2SEL_Pos (16U)
+#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00070000 */
+#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (Clock output selection) */
+#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00040000 */
/*!< MCO2 Prescaler configuration */
-#define RCC_CFGR_MCO2PRE_Pos (20U)
-#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00F00000 */
-#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO prescaler [3:0] */
-#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00100000 */
-#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00400000 */
-#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_MCO2PRE_Pos (20U)
+#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00700000 */
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO prescaler [2:0] */
+#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00400000 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
-#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
/*!< MCO Prescaler configuration */
#define RCC_CFGR_MCOPRE_Pos (28U)
-#define RCC_CFGR_MCOPRE_Msk (0xFUL << RCC_CFGR_MCOPRE_Pos) /*!< 0xF0000000 */
-#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [3:0] */
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
-#define RCC_CFGR_MCOPRE_3 (0x8UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
@@ -4089,7 +4018,7 @@ typedef struct
#define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk
#define RCC_APBRSTR1_USART2RST_Pos (17U)
-#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00010000 */
#define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk
#define RCC_APBRSTR1_I2C1RST_Pos (21U)
#define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */
@@ -4163,7 +4092,7 @@ typedef struct
#define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */
#define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk
#define RCC_APBENR1_USART2EN_Pos (17U)
-#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00010000 */
#define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk
#define RCC_APBENR1_I2C1EN_Pos (21U)
#define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */
@@ -4240,7 +4169,7 @@ typedef struct
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
-#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00010000 */
#define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk
#define RCC_APBSMENR1_I2C1SMEN_Pos (21U)
#define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
@@ -5013,9 +4942,6 @@ typedef struct
#define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */
#define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
#define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
-#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
-#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
@@ -5048,49 +4974,49 @@ typedef struct
/****************** Bit definition for SYSCFG_CFGR3 register ****************/
#define SYSCFG_CFGR3_PINMUX0_Pos (0U)
-#define SYSCFG_CFGR3_PINMUX0_Msk (0x2UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR3_PINMUX0_Msk (0x3UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000003 */
#define SYSCFG_CFGR3_PINMUX0 SYSCFG_CFGR3_PINMUX0_Msk /*!< Pin GPIO multiplexer 0 */
#define SYSCFG_CFGR3_PINMUX0_0 (0x1UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR3_PINMUX0_1 (0x2UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR3_PINMUX1_Pos (2U)
-#define SYSCFG_CFGR3_PINMUX1_Msk (0x2UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x0000000C */
+#define SYSCFG_CFGR3_PINMUX1_Msk (0x3UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x0000000C */
#define SYSCFG_CFGR3_PINMUX1 SYSCFG_CFGR3_PINMUX1_Msk /*!< Pin GPIO multiplexer 1 */
#define SYSCFG_CFGR3_PINMUX1_0 (0x1UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR3_PINMUX1_1 (0x2UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR3_PINMUX2_Pos (4U)
-#define SYSCFG_CFGR3_PINMUX2_Msk (0x2UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_PINMUX2_Msk (0x3UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000030 */
#define SYSCFG_CFGR3_PINMUX2 SYSCFG_CFGR3_PINMUX2_Msk /*!< Pin GPIO multiplexer 2 */
#define SYSCFG_CFGR3_PINMUX2_0 (0x1UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000010 */
#define SYSCFG_CFGR3_PINMUX2_1 (0x2UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000020 */
#define SYSCFG_CFGR3_PINMUX3_Pos (6U)
-#define SYSCFG_CFGR3_PINMUX3_Msk (0x2UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x000000C0 */
+#define SYSCFG_CFGR3_PINMUX3_Msk (0x3UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x000000C0 */
#define SYSCFG_CFGR3_PINMUX3 SYSCFG_CFGR3_PINMUX3_Msk /*!< Pin GPIO multiplexer 3 */
#define SYSCFG_CFGR3_PINMUX3_0 (0x1UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x00000040 */
#define SYSCFG_CFGR3_PINMUX3_1 (0x2UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x00000080 */
#define SYSCFG_CFGR3_PINMUX4_Pos (8U)
-#define SYSCFG_CFGR3_PINMUX4_Msk (0x2UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR3_PINMUX4_Msk (0x3UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000300 */
#define SYSCFG_CFGR3_PINMUX4 SYSCFG_CFGR3_PINMUX4_Msk /*!< Pin GPIO multiplexer 4 */
#define SYSCFG_CFGR3_PINMUX4_0 (0x1UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR3_PINMUX4_1 (0x2UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR3_PINMUX5_Pos (10U)
-#define SYSCFG_CFGR3_PINMUX5_Msk (0x2UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000C00 */
+#define SYSCFG_CFGR3_PINMUX5_Msk (0x3UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000C00 */
#define SYSCFG_CFGR3_PINMUX5 SYSCFG_CFGR3_PINMUX5_Msk /*!< Pin GPIO multiplexer 5 */
#define SYSCFG_CFGR3_PINMUX5_0 (0x1UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000400 */
#define SYSCFG_CFGR3_PINMUX5_1 (0x2UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000800 */
/***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/
-#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U)
-#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
-#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */
+#define SYSCFG_ITLINE0_SR_WWDG_Pos (0U)
+#define SYSCFG_ITLINE0_SR_WWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_WWDG_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE0_SR_WWDG SYSCFG_ITLINE0_SR_WWDG_Msk /*!< EWDG interrupt */
#define SYSCFG_ITLINE2_SR_RTC_Pos (1U)
#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */
#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC interrupt */
#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)
#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */
-#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)
-#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
-#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */
+#define SYSCFG_ITLINE4_SR_RCC_Pos (0U)
+#define SYSCFG_ITLINE4_SR_RCC_Msk (0x1UL << SYSCFG_ITLINE4_SR_RCC_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE4_SR_RCC SYSCFG_ITLINE4_SR_RCC_Msk /*!< RCC interrupt */
#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)
#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */
@@ -5148,9 +5074,9 @@ typedef struct
#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA1 Channel 3 Interrupt */
-#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
-#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
-#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
+#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
+#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
#define SYSCFG_ITLINE12_SR_ADC_Pos (0U)
#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */
@@ -5751,27 +5677,27 @@ typedef struct
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
-#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
+ __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
+ __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
+ uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
+ uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
+ uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/* Legacy registers naming */
+#define TR1 AWD1TR
+#define TR2 AWD2TR
+#define TR3 AWD3TR
+
+/**
+ * @brief CRC calculation unit
+ */
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED1; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRS control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
+ __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
+ __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
+} DBG_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA Multiplexer
+ */
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
+ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+ * @brief Asynch Interrupt/Event Controller (EXTI)
+ */
+typedef struct
+{
+ __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
+ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
+ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
+ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
+ uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
+ __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x30 */
+ __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x34 */
+ __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x38 */
+ uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */
+ __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
+ uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
+ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
+ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
+ uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */
+ __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
+ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
+ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
+ uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
+ __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */
+ __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */
+ __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */
+ __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */
+ __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */
+ __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */
+ uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */
+ __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
+} GPIO_TypeDef;
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
+ __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
+ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
+ __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
+ __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
+ __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
+ __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
+ __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
+ __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
+ __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
+ __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
+ __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */
+ __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */
+ uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */
+ __IO uint32_t BKP0R; /*!< Backup register 0, Address offset: 0x70 */
+ __IO uint32_t BKP1R; /*!< Backup register 1, Address offset: 0x74 */
+ __IO uint32_t BKP2R; /*!< Backup register 2, Address offset: 0x78 */
+ __IO uint32_t BKP3R; /*!< Backup register 3, Address offset: 0x7C */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
+ uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x0C -- 0x10 */
+ __IO uint32_t CRRCR; /*!< RCC Clock Configuration Register, Address offset: 0x14 */
+ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
+ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
+ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
+ __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
+ __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
+ __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
+ __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
+ __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */
+ __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */
+ __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
+ __IO uint32_t CCIPR2; /*!< RCC Peripherals Independent Clocks Configuration Register2, Address offset: 0x58 */
+ __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */
+ __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */
+ uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */
+ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
+ __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
+ uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */
+ __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
+} RTC_TypeDef;
+
+ /**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */
+ uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */
+ __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
+ __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */
+ __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */
+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
+
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Dual Role Device
+ */
+
+typedef struct
+{
+ __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */
+ __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */
+ __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */
+ __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */
+ __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */
+ __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */
+ __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */
+ __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */
+ __IO uint32_t RESERVED0[8]; /*!< Reserved, */
+ __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint32_t RESERVED1; /*!< Reserved */
+ __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+} USB_DRD_TypeDef;
+
+/**
+ * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table
+ */
+typedef struct
+{
+ __IO uint32_t TXBD; /*! */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_SR register *******************/
+#define RTC_SR_TSOVF_Pos (4U)
+#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
+#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */
+#define RTC_SR_TSF_Pos (3U)
+#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
+#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */
+#define RTC_SR_ALRAF_Pos (0U)
+#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
+#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
+
+/******************** Bits definition for RTC_MISR register *****************/
+#define RTC_MISR_TSOVMF_Pos (4U)
+#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */
+#define RTC_MISR_TSMF_Pos (3U)
+#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
+#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */
+#define RTC_MISR_ALRAMF_Pos (0U)
+#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
+
+/******************** Bits definition for RTC_SCR register ******************/
+#define RTC_SCR_CTSOVF_Pos (4U)
+#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */
+#define RTC_SCR_CTSF_Pos (3U)
+#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
+#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */
+#define RTC_SCR_CALRAF_Pos (0U)
+#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
+#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[22]*/
+#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)
+#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */
+#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)
+#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */
+#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)
+#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt */
+#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)
+#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
+#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
+#else
+ sysdiv = 1U;
+#endif /* RCC_CR_SYSDIV */
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_0: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
+ SystemCoreClock = (HSE_VALUE / sysdiv);
+ break;
+
+#if defined(RCC_HSI48_SUPPORT)
+ case RCC_CFGR_SW_1: /* HSI48 used as system clock */
+ SystemCoreClock = (HSI48_VALUE / sysdiv);
break;
+#endif /* RCC_HSI48_SUPPORT */
case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
- SystemCoreClock = LSI_VALUE;
+ SystemCoreClock = (LSI_VALUE / sysdiv);
break;
case RCC_CFGR_SWS_2: /* LSE used as system clock */
- SystemCoreClock = LSE_VALUE;
+ SystemCoreClock = (LSE_VALUE / sysdiv);
break;
case 0x00000000U: /* HSI used as system clock */
default: /* HSI used as system clock */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
- SystemCoreClock = (HSI_VALUE/hsidiv);
+ SystemCoreClock = ((HSI_VALUE / sysdiv) / hsidiv);
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
From 726f23b09c0dd31cdd78f5b25fb3cd6cb3dd10fa Mon Sep 17 00:00:00 2001
From: Guillaume Gautier
Date: Tue, 24 Sep 2024 14:51:48 +0200
Subject: [PATCH 02/11] stm32cube: update stm32f1 to cube version V1.8.6
Update Cube version for STM32F1xx series
on https://github.com/STMicroelectronics
from version v1.8.5
to version v1.8.6
Signed-off-by: Guillaume Gautier
---
stm32cube/stm32f1xx/README | 13 +-
.../drivers/include/Legacy/stm32_hal_legacy.h | 91 ++--
.../drivers/include/stm32f1xx_hal_can.h | 4 +
.../drivers/include/stm32f1xx_hal_cortex.h | 3 +-
.../drivers/include/stm32f1xx_hal_nand.h | 2 +-
.../drivers/include/stm32f1xx_hal_pccard.h | 13 +-
.../drivers/include/stm32f1xx_hal_spi.h | 44 +-
.../drivers/include/stm32f1xx_hal_tim.h | 35 +-
.../drivers/include/stm32f1xx_hal_usart.h | 2 +-
.../drivers/include/stm32f1xx_hal_wwdg.h | 2 +-
.../drivers/include/stm32f1xx_ll_adc.h | 4 +-
.../drivers/include/stm32f1xx_ll_cortex.h | 2 +-
.../drivers/include/stm32f1xx_ll_dac.h | 3 +-
.../drivers/include/stm32f1xx_ll_fsmc.h | 167 ++++----
.../drivers/include/stm32f1xx_ll_iwdg.h | 10 +-
.../drivers/include/stm32f1xx_ll_sdmmc.h | 8 +-
.../drivers/include/stm32f1xx_ll_spi.h | 137 +++---
.../drivers/include/stm32f1xx_ll_tim.h | 25 +-
.../drivers/include/stm32f1xx_ll_usart.h | 114 ++---
.../drivers/include/stm32f1xx_ll_usb.h | 101 +++--
.../drivers/include/stm32f1xx_ll_utils.h | 2 +-
.../drivers/include/stm32f1xx_ll_wwdg.h | 12 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal.c | 2 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_can.c | 41 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_cec.c | 2 +-
.../drivers/src/stm32f1xx_hal_cortex.c | 82 ++--
.../stm32f1xx/drivers/src/stm32f1xx_hal_dac.c | 5 +-
.../drivers/src/stm32f1xx_hal_dac_ex.c | 1 -
.../drivers/src/stm32f1xx_hal_flash.c | 5 -
.../drivers/src/stm32f1xx_hal_flash_ex.c | 3 -
.../drivers/src/stm32f1xx_hal_gpio.c | 2 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c | 37 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c | 51 ++-
.../stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c | 78 ++--
.../drivers/src/stm32f1xx_hal_iwdg.c | 3 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c | 2 +-
.../drivers/src/stm32f1xx_hal_nand.c | 4 +-
.../drivers/src/stm32f1xx_hal_pccard.c | 40 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c | 30 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_sd.c | 21 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_spi.c | 400 +++++++++---------
.../drivers/src/stm32f1xx_hal_sram.c | 5 +-
.../stm32f1xx/drivers/src/stm32f1xx_hal_tim.c | 62 +--
.../drivers/src/stm32f1xx_hal_tim_ex.c | 34 +-
...tm32f1xx_hal_timebase_rtc_alarm_template.c | 110 +++--
.../src/stm32f1xx_hal_timebase_tim_template.c | 23 +-
.../drivers/src/stm32f1xx_hal_uart.c | 61 ++-
.../drivers/src/stm32f1xx_hal_usart.c | 9 +-
.../drivers/src/stm32f1xx_hal_wwdg.c | 130 +++---
.../stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c | 45 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_spi.c | 9 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_tim.c | 22 +-
.../stm32f1xx/drivers/src/stm32f1xx_ll_usb.c | 88 ++--
stm32cube/stm32f1xx/release_note.html | 356 ++++++++++++----
stm32cube/stm32f1xx/soc/stm32f100xb.h | 2 -
stm32cube/stm32f1xx/soc/stm32f100xe.h | 2 -
stm32cube/stm32f1xx/soc/stm32f101x6.h | 2 -
stm32cube/stm32f1xx/soc/stm32f101xb.h | 2 -
stm32cube/stm32f1xx/soc/stm32f101xe.h | 2 -
stm32cube/stm32f1xx/soc/stm32f101xg.h | 2 -
stm32cube/stm32f1xx/soc/stm32f102x6.h | 2 -
stm32cube/stm32f1xx/soc/stm32f102xb.h | 2 -
stm32cube/stm32f1xx/soc/stm32f103x6.h | 2 -
stm32cube/stm32f1xx/soc/stm32f103xb.h | 2 -
stm32cube/stm32f1xx/soc/stm32f103xe.h | 2 -
stm32cube/stm32f1xx/soc/stm32f103xg.h | 2 -
stm32cube/stm32f1xx/soc/stm32f105xc.h | 2 -
stm32cube/stm32f1xx/soc/stm32f107xc.h | 2 -
stm32cube/stm32f1xx/soc/stm32f1xx.h | 3 +-
stm32cube/stm32f1xx/soc/system_stm32f1xx.c | 2 +-
70 files changed, 1487 insertions(+), 1103 deletions(-)
diff --git a/stm32cube/stm32f1xx/README b/stm32cube/stm32f1xx/README
index 547e8e2e9..110e712ce 100644
--- a/stm32cube/stm32f1xx/README
+++ b/stm32cube/stm32f1xx/README
@@ -6,7 +6,7 @@ Origin:
http://www.st.com/en/embedded-software/stm32cubef1.html
Status:
- version v1.8.5
+ version v1.8.6
Purpose:
ST Microelectronics official MCU package for STM32F1 series.
@@ -23,7 +23,7 @@ URL:
https://github.com/STMicroelectronics/STM32CubeF1
Commit:
- 5326afcfb2ecfb27b7e473fd43e1adec9e3595ec
+ 42472d601caa457b02d849c7de5f9792629ee324
Maintained-by:
External
@@ -52,11 +52,8 @@ Patch List:
-Added stm32cube/stm32f1xx/drivers/include/stm32_assert.h
-Removed unused stm32cube/stm32f1xx/drivers/include/stm32_assert_template.h
- *Wrap define UNUSED with an ifndef
- This will prevent a compiler warning for the case the UNUSED macro
- is already defined elsewhere in the project
- Impacted files:
- drivers/include/stm32f1xx_hal_def.h
- ST Internal Reference: 136825
+ *Fix to remove PAGESIZE definition which conflicts with POSIX
+ Impacted files:
+ drivers/include/Legacy/stm32_hal_legacy.h
See release_note.html from STM32Cube
diff --git a/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h
index a1fc260ec..6bacae34d 100644
--- a/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h
+++ b/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h
@@ -37,16 +37,12 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
+#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
-#if defined(STM32U5)
-#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-#endif /* STM32U5 || STM32H7 || STM32MP1 */
+#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -279,7 +275,7 @@ extern "C" {
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
@@ -476,7 +472,9 @@ extern "C" {
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7)
/* #define PAGESIZE FLASH_PAGE_SIZE */
+#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@@ -552,6 +550,16 @@ extern "C" {
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_USER_nBOOT1 OB_USER_NBOOT1
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U0 */
/**
* @}
@@ -800,6 +808,21 @@ extern "C" {
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
+
+#if defined(STM32WBA)
+#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
+#endif /* STM32WBA */
/**
* @}
*/
@@ -1243,10 +1266,10 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-#if defined(STM32H5)
+#if defined(STM32H5) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
-#endif /* STM32H5 */
+#endif /* STM32H5 || STM32H7RS */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1258,10 +1281,10 @@ extern "C" {
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
-#if defined(STM32H5) || defined(STM32WBA)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
-#endif /* STM32H5 || STM32WBA */
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1599,6 +1622,8 @@ extern "C" {
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
+
/**
* @}
*/
@@ -1809,7 +1834,7 @@ extern "C" {
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
@@ -1991,12 +2016,12 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
-#if defined(STM32H5) || defined(STM32WBA)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
-#endif /* STM32H5 || STM32WBA */
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
/**
* @}
@@ -2311,8 +2336,8 @@ extern "C" {
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2345,8 +2370,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2403,8 +2428,8 @@ extern "C" {
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2421,7 +2446,7 @@ extern "C" {
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
+#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2723,6 +2748,12 @@ extern "C" {
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#if defined(STM32C0)
+#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
+#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
+#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
+#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
+#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3646,8 +3677,12 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
- defined(STM32WL) || defined(STM32C0)
+ defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3749,8 +3784,10 @@ extern "C" {
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3896,7 +3933,8 @@ extern "C" {
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
+ defined (STM32WBA) || defined (STM32H5) || \
+ defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3932,7 +3970,9 @@ extern "C" {
#endif /* STM32F1 */
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
- defined (STM32L0) || defined (STM32L1)
+ defined (STM32H7) || \
+ defined (STM32L0) || defined (STM32L1) || \
+ defined (STM32WB)
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
#endif
@@ -4217,6 +4257,9 @@ extern "C" {
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
* @}
*/
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h
index 287c9919e..db8cc92fb 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h
@@ -209,7 +209,11 @@ typedef struct
/**
* @brief CAN handle Structure definition
*/
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
typedef struct __CAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
{
CAN_TypeDef *Instance; /*!< Register base address */
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h
index cea3dc759..5d03cd3cc 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h
@@ -285,6 +285,8 @@ void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
@@ -405,4 +407,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __STM32F1xx_HAL_CORTEX_H */
-
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h
index 38093c3e7..81562cee7 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h
@@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_Timing
FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h
index 58ec0eaff..dc726caa0 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h
@@ -68,7 +68,7 @@ typedef enum
typedef struct __PCCARD_HandleTypeDef
#else
typedef struct
-#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
{
FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
@@ -82,7 +82,7 @@ typedef struct
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
} PCCARD_HandleTypeDef;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
@@ -100,7 +100,7 @@ typedef enum
* @brief HAL PCCARD Callback pointer definition
*/
typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -122,7 +122,7 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
} while(0)
#else
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -137,7 +137,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
- FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+ FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
+ FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
@@ -165,7 +166,7 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HA
pPCCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
HAL_PCCARD_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h
index 73073fc8f..309eb5bd2 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h
@@ -107,7 +107,7 @@ typedef struct __SPI_HandleTypeDef
SPI_InitTypeDef Init; /*!< SPI communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
@@ -336,11 +336,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval None
*/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
@@ -482,8 +483,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
+#define SPI_RESET_CRC(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
+ } while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR register.
@@ -498,7 +502,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
- ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
+ ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 register.
@@ -510,7 +514,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
- (__INTERRUPT__)) ? SET : RESET)
+ (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
@@ -619,7 +623,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
- (((__POLYNOMIAL__)&0x1U) != 0U))
+ (((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
@@ -668,17 +672,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @{
*/
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
@@ -704,8 +708,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
* @{
*/
/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
/**
* @}
*/
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h
index 53951f77c..ac7207586 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h
@@ -385,29 +385,28 @@ typedef struct
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@@ -1707,7 +1706,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
@@ -2045,7 +2043,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h
index 551171cb5..cb0f638b9 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h
@@ -624,7 +624,7 @@ uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup USART_Private_Functions USART Private Functions
+/** @addtogroup USART_Private_Functions
* @{
*/
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h
index 6179e20b7..081a918ac 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h
@@ -183,7 +183,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h
index fb65098bb..e341933e3 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h
@@ -3686,7 +3686,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
- return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
+ return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
}
/**
@@ -3717,7 +3717,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{
- return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+ return (READ_BIT(ADCxy_COMMON->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
}
/**
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h
index c8b503c99..c1fb2c774 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h
@@ -587,7 +587,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
- WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
}
/**
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h
index 3e17bbf6e..6e885f036 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h
@@ -87,7 +87,6 @@ extern "C" {
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-
#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
@@ -473,7 +472,7 @@ typedef struct
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval DAC conversion data (unit: digital value)
*/
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
/ (__VREFANALOG_VOLTAGE__) \
)
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h
index abd47886c..118137b52 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h
@@ -41,47 +41,47 @@ extern "C" {
#if defined(FSMC_BANK1)
#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
- ((__BANK__) == FSMC_NORSRAM_BANK2) || \
- ((__BANK__) == FSMC_NORSRAM_BANK3) || \
- ((__BANK__) == FSMC_NORSRAM_BANK4))
+ ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK4))
#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+ ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
- ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
- ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
- ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
- ((__SIZE__) == FSMC_PAGE_SIZE_1024))
+ ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
+ ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
+ ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
+ ((__SIZE__) == FSMC_PAGE_SIZE_1024))
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
- ((__MODE__) == FSMC_ACCESS_MODE_B) || \
- ((__MODE__) == FSMC_ACCESS_MODE_C) || \
- ((__MODE__) == FSMC_ACCESS_MODE_D))
+ ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_D))
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+ ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+ ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+ ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+ ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+ ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+ ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+ ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+ ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+ ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
@@ -96,18 +96,18 @@ extern "C" {
#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+ ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+ ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FSMC_NAND_ECC_ENABLE))
+ ((__STATE__) == FSMC_NAND_ECC_ENABLE))
#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
@@ -161,56 +161,57 @@ extern "C" {
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing*/
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
- This parameter can be a value of @ref FSMC_Memory_Type */
+ This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
+ This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
+ This parameter can be a value of @ref FSMC_Wait_Timing */
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device
+ by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
+ This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
+ This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
+ This parameter can be a value of @ref FSMC_Write_Burst */
uint32_t PageSize; /*!< Specifies the memory page size.
- This parameter can be a value of @ref FSMC_Page_Size */
+ This parameter can be a value of @ref FSMC_Page_Size */
} FSMC_NORSRAM_InitTypeDef;
/**
@@ -254,7 +255,7 @@ typedef struct
in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
+ This parameter can be a value of @ref FSMC_Access_Mode */
} FSMC_NORSRAM_TimingTypeDef;
#endif /* FSMC_BANK1 */
@@ -338,7 +339,7 @@ typedef struct
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FSMC_PCCARD_InitTypeDef;
+} FSMC_PCCARD_InitTypeDef;
#endif /* FSMC_BANK4 */
/**
@@ -643,7 +644,7 @@ typedef struct
* @retval None
*/
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- |= FSMC_BCRx_MBKEN)
+ |= FSMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
@@ -652,7 +653,7 @@ typedef struct
* @retval None
*/
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- &= ~FSMC_BCRx_MBKEN)
+ &= ~FSMC_BCRx_MBKEN)
/**
* @}
@@ -671,8 +672,9 @@ typedef struct
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
-#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \
- ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN) : \
+ ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
/**
* @brief Disable the NAND device access.
@@ -680,8 +682,9 @@ typedef struct
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
-#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
- CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN) : \
+ CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
/**
* @}
@@ -710,7 +713,7 @@ typedef struct
* @}
*/
-#endif
+#endif /* FSMC_BANK4 */
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
* @brief macros to handle NAND interrupts
@@ -728,8 +731,9 @@ typedef struct
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
-#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
@@ -742,8 +746,9 @@ typedef struct
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
-#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
/**
* @brief Get flag status of the NAND device.
@@ -757,8 +762,9 @@ typedef struct
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
-#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
@@ -772,8 +778,9 @@ typedef struct
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
-#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
/**
* @}
@@ -839,7 +846,7 @@ typedef struct
/**
* @}
*/
-#endif
+#endif /* FSMC_BANK4 */
/**
* @}
@@ -862,14 +869,14 @@ typedef struct
* @{
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_InitTypeDef *Init);
+ const FSMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
- uint32_t ExtendedMode);
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode);
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+ FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
@@ -894,11 +901,11 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev
/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
* @{
*/
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
@@ -909,8 +916,8 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
- uint32_t Timeout);
+HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout);
/**
* @}
*/
@@ -926,13 +933,13 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
* @{
*/
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
/**
* @}
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h
index ea718ecd9..5dce390ff 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h
@@ -207,7 +207,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
@@ -230,7 +230,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
@@ -249,7 +249,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
@@ -260,7 +260,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
@@ -272,7 +272,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
}
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h
index 0234caeed..704a7f02d 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h
@@ -300,10 +300,14 @@ typedef struct
#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
#define SDMMC_CARD_LOCKED 0x02000000U
-#ifndef SDMMC_DATATIMEOUT
-#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */
+#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
#endif /* SDMMC_DATATIMEOUT */
+#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
+#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT
+#endif /* SDMMC_SWDATATIMEOUT */
+
#define SDMMC_0TO7BITS 0x000000FFU
#define SDMMC_8TO15BITS 0x0000FF00U
#define SDMMC_16TO23BITS 0x00FF0000U
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h
index 37e00b125..15bfc9af6 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h
@@ -55,53 +55,66 @@ typedef struct
uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetTransferDirection().*/
uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_LL_EC_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetMode().*/
uint32_t DataWidth; /*!< Specifies the SPI data width.
This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetDataWidth().*/
uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_LL_EC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetClockPolarity().*/
uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_LL_EC_PHASE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetClockPhase().*/
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
+ or by software using the SSI bit.
This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetNSSMode().*/
- uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
+ to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+ @note The communication clock is derived from the master clock.
+ The slave clock does not need to be set.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetBaudRatePrescaler().*/
uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetTransferBitOrder().*/
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
- This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+ This feature can be modified afterwards using unitary
+ functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetCRCPolynomial().*/
} LL_SPI_InitTypeDef;
@@ -309,7 +322,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
@@ -339,7 +352,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
}
@@ -369,7 +382,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
}
@@ -398,7 +411,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
}
@@ -438,7 +451,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
*/
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
}
@@ -466,7 +479,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
}
@@ -503,7 +516,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
}
@@ -530,7 +543,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
*/
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
}
@@ -574,7 +587,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
}
@@ -609,7 +622,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->CRCPR));
}
@@ -620,7 +633,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->RXCRCR));
}
@@ -631,7 +644,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->TXCRCR));
}
@@ -672,7 +685,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
*/
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
{
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
@@ -693,7 +706,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
}
@@ -704,7 +717,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
}
@@ -715,7 +728,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
}
@@ -726,7 +739,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
@@ -737,7 +750,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
@@ -755,7 +768,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
}
@@ -829,7 +842,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
/**
* @brief Enable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @note This bit controls the generation of an interrupt when an error condition
+ * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
* @param SPIx SPI Instance
* @retval None
@@ -863,7 +877,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
/**
* @brief Disable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @note This bit controls the generation of an interrupt when an error condition
+ * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
* @param SPIx SPI Instance
* @retval None
@@ -901,7 +916,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
}
@@ -912,7 +927,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
}
@@ -923,7 +938,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
}
@@ -964,7 +979,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
}
@@ -997,7 +1012,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
}
@@ -1008,7 +1023,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
{
return (uint32_t) &(SPIx->DR);
}
@@ -1085,7 +1100,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
* @{
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
@@ -1353,7 +1368,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
}
@@ -1386,7 +1401,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat
* @arg @ref LL_I2S_DATAFORMAT_24B
* @arg @ref LL_I2S_DATAFORMAT_32B
*/
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
}
@@ -1413,7 +1428,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
* @arg @ref LL_I2S_POLARITY_LOW
* @arg @ref LL_I2S_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
}
@@ -1448,7 +1463,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
* @arg @ref LL_I2S_STANDARD_PCM_LONG
*/
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
}
@@ -1479,7 +1494,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
* @arg @ref LL_I2S_MODE_MASTER_TX
* @arg @ref LL_I2S_MODE_MASTER_RX
*/
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
}
@@ -1502,7 +1517,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca
* @param SPIx SPI Instance
* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
}
@@ -1529,7 +1544,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
*/
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
}
@@ -1562,7 +1577,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
}
@@ -1581,7 +1596,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_RXNE(SPIx);
}
@@ -1592,7 +1607,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_TXE(SPIx);
}
@@ -1603,7 +1618,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_BSY(SPIx);
}
@@ -1614,7 +1629,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_OVR(SPIx);
}
@@ -1625,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
@@ -1640,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
}
@@ -1762,7 +1777,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_ERR(SPIx);
}
@@ -1773,7 +1788,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_RXNE(SPIx);
}
@@ -1784,7 +1799,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_TXE(SPIx);
}
@@ -1825,7 +1840,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_RX(SPIx);
}
@@ -1858,7 +1873,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_TX(SPIx);
}
@@ -1903,7 +1918,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
* @{
*/
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h
index f1bceb797..d54a00ead 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h
@@ -556,10 +556,10 @@ typedef struct
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC);
}
+/**
+ * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+ * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h
index ffe41927e..6d370619a 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h
@@ -347,7 +347,7 @@ typedef struct
* @}
*/
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper
* @{
*/
@@ -636,7 +636,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
#endif /* USART_OverSampling_Feature */
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
@@ -653,7 +653,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
@@ -668,7 +668,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USA
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
@@ -684,7 +684,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
@@ -699,7 +699,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
@@ -715,7 +715,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
@@ -730,7 +730,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
@@ -758,7 +758,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
/**
* @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
@@ -771,7 +771,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
/**
* @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
@@ -784,7 +784,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
/**
* @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
@@ -886,7 +886,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
/**
* @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -899,7 +899,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -912,7 +912,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -925,7 +925,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -938,7 +938,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
@@ -957,7 +957,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
@@ -1125,7 +1125,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint3
/**
* @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
@@ -1138,7 +1138,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
/**
* @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
@@ -1151,7 +1151,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
/**
* @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
@@ -1164,7 +1164,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
@@ -1180,7 +1180,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
@@ -1196,7 +1196,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
@@ -1211,7 +1211,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
@@ -1232,7 +1232,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
/**
* @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
@@ -1245,7 +1245,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
/**
* @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
@@ -1258,7 +1258,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
/**
* @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
@@ -1271,7 +1271,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *US
/**
* @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
@@ -1284,7 +1284,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
/**
* @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
@@ -1297,7 +1297,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
/**
* @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
@@ -1311,7 +1311,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
@@ -1326,7 +1326,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
@@ -1340,7 +1340,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USA
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
@@ -1355,7 +1355,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
@@ -1376,7 +1376,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USA
/**
* @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
@@ -1389,7 +1389,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
/**
* @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
@@ -1402,7 +1402,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
@@ -1423,7 +1423,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USART
/**
* @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -1439,7 +1439,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3
/**
* @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -1454,7 +1454,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USA
/**
* @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
@@ -1467,7 +1467,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
/**
* @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
@@ -1480,7 +1480,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
/**
* @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
@@ -1541,7 +1541,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1579,7 +1579,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
@@ -1619,7 +1619,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1658,7 +1658,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1700,7 +1700,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1866,7 +1866,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll SR LBD LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
@@ -1879,7 +1879,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
@@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
/**
* @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll SR LBD LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
@@ -2044,7 +2044,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
/**
* @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll SR CTS LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
@@ -2120,7 +2120,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
/**
* @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
@@ -2148,7 +2148,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
/**
* @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
@@ -2216,7 +2216,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
/**
* @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
@@ -2244,7 +2244,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
/**
* @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
@@ -2312,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
@@ -2336,7 +2336,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h
index c3a548eef..f0e13e80c 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h
@@ -37,6 +37,13 @@ extern "C" {
*/
/* Exported types ------------------------------------------------------------*/
+#ifndef HAL_USB_TIMEOUT
+#define HAL_USB_TIMEOUT 0xF000000U
+#endif /* define HAL_USB_TIMEOUT */
+
+#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
+#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
+#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
/**
* @brief USB Mode definition
@@ -85,42 +92,42 @@ typedef enum
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
+ uint8_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
#if defined (USB_OTG_FS)
- uint32_t Host_channels; /*!< Host Channels number.
+ uint8_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+#endif /* defined (USB_OTG_FS) */
- uint32_t dma_enable; /*!< USB DMA state.
+ uint8_t dma_enable; /*!< USB DMA state.
If DMA is not supported this parameter shall be set by default to zero */
-#endif /* defined (USB_OTG_FS) */
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Speed/HCD_Speed
- (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+ uint8_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+ uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
+ uint8_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
+ uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
#if defined (USB_OTG_FS)
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+ uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
- uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+ uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+ uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
#endif /* defined (USB_OTG_FS) */
} USB_CfgTypeDef;
@@ -513,41 +520,41 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup);
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
-uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
@@ -556,12 +563,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc);
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h
index d938fa364..69483bda0 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h
@@ -212,7 +212,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
+ * @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
diff --git a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h
index 6f9e1b703..565d18c5a 100644
--- a/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h
+++ b/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h
@@ -131,7 +131,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
@@ -158,7 +158,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
@@ -191,7 +191,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
@@ -223,7 +223,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
@@ -244,7 +244,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
@@ -286,7 +286,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c
index 6756fb445..688e2becb 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c
@@ -57,7 +57,7 @@
*/
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
-#define __STM32F1xx_HAL_VERSION_SUB2 (0x09U) /*!< [15:8] sub2 version */
+#define __STM32F1xx_HAL_VERSION_SUB2 (0x0AU) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c
index b143ac869..207d19646 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c
@@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
- (+++) Configure CAN pins as alternate function open-drain
+ (+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
+#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
- * @brief Configuration functions.
- *
+ * @brief Configuration functions.
+ *
@verbatim
==============================================================================
##### Configuration functions #####
@@ -868,7 +869,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
-#endif
+#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
@@ -878,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
-#endif
+#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
@@ -970,8 +971,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### Control functions #####
@@ -1143,7 +1144,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
- uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@@ -1159,15 +1159,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
- if (count > timeout)
+ if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
- }
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+ } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@@ -1608,8 +1607,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
- * @brief Interrupts management
- *
+ * @brief Interrupts management
+ *
@verbatim
==============================================================================
##### Interrupts management #####
@@ -2074,8 +2073,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
- * @brief CAN Callback functions
- *
+ * @brief CAN Callback functions
+ *
@verbatim
==============================================================================
##### Callback functions #####
@@ -2324,8 +2323,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
+ * @brief CAN Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c
index c0a173dfb..e2c9ffdfe 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c
@@ -924,7 +924,7 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
hcec->TxXferCount--;
/* Write data to TX buffer*/
- hcec->Instance->TXD = (uint8_t)*hcec->pTxBuffPtr++;
+ hcec->Instance->TXD = (uint8_t) * hcec->pTxBuffPtr++;
/* If this is the last byte of the ongoing transmission */
if (hcec->TxXferCount == 0U)
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c
index d5ee73b8f..35cd222f9 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c
@@ -290,6 +290,38 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
__ISB();
}
+/**
+ * @brief Enable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
@@ -301,38 +333,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c
index c890cade2..2e86c4abd 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c
@@ -959,10 +959,7 @@ uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
uint32_t result;
/* Check the DAC peripheral handle */
- if (hdac == NULL)
- {
- return HAL_ERROR;
- }
+ assert_param(hdac != NULL);
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c
index 3c4fbb8fc..87a718471 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c
@@ -387,7 +387,6 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
}
-
/**
* @}
*/
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c
index 1801cae74..f71d2a765 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c
@@ -266,9 +266,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
@@ -587,8 +584,6 @@ void HAL_FLASH_IRQHandler(void)
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
#endif /* FLASH_BANK2_END */
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
}
}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c
index 6c818a4c5..a836cfe4c 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c
@@ -318,9 +318,6 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
/* If procedure already ongoing, reject the next one */
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
{
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c
index d994cf02d..ec5e3791d 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c
@@ -505,7 +505,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
* the next reset.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: specifies the port bit to be locked.
-* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c
index 67c86af92..5e9d53161 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c
@@ -106,8 +106,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx;
-
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
@@ -117,8 +115,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
- USBx = hhcd->Instance;
-
if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -148,22 +144,31 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
hhcd->State = HAL_HCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
- if ((USBx->CID & (0x1U << 8)) == 0U)
- {
- hhcd->Init.dma_enable = 0U;
- }
+ hhcd->Init.dma_enable = 0U;
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
- (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+ if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
- /* Force Host Mode*/
- (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+ /* Force Host Mode */
+ if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init Host */
- (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+ if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
hhcd->State = HAL_HCD_STATE_READY;
@@ -1212,7 +1217,7 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1428,7 +1433,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
uint32_t num_packets;
@@ -1569,7 +1574,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
@@ -1635,7 +1640,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c
index 0651e867a..00287cb8a 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c
@@ -89,7 +89,7 @@
add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
@@ -139,7 +139,7 @@
or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
@@ -193,7 +193,7 @@
add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
@@ -2937,6 +2937,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
+ if (hi2c->XferSize == 3U)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
@@ -4810,7 +4815,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -4826,7 +4831,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
UNUSED(DevAddress);
/* Abort Master transfer during Receive or Transmit process */
- if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) ||
+ (CurrentMode == HAL_I2C_MODE_MEM)))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -5621,7 +5627,9 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
uint32_t tmp;
+ uint32_t CurrentXferOptions;
+ CurrentXferOptions = hi2c->XferOptions;
tmp = hi2c->XferCount;
if (tmp > 3U)
{
@@ -5677,7 +5685,14 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
@@ -5780,15 +5795,11 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
- else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
+ else
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
- else
- {
- /* Do nothing */
- }
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
@@ -5825,7 +5836,14 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
#else
@@ -7136,7 +7154,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c
index 0ae903eec..9aaa18acb 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c
@@ -777,15 +777,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -896,15 +895,14 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -994,15 +992,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1021,6 +1018,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
hi2s->TxXferCount = Size;
}
+ __HAL_UNLOCK(hi2s);
+
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -1031,7 +1030,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
__HAL_I2S_ENABLE(hi2s);
}
- __HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1060,15 +1058,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1087,6 +1084,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
hi2s->RxXferCount = Size;
}
+ __HAL_UNLOCK(hi2s);
+
/* Enable RXNE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -1097,7 +1096,6 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
__HAL_I2S_ENABLE(hi2s);
}
- __HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1124,15 +1122,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1174,12 +1171,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ __HAL_UNLOCK(hi2s);
/* Check if the I2S Tx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
@@ -1188,7 +1180,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- __HAL_UNLOCK(hi2s);
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
return HAL_OK;
}
@@ -1215,15 +1213,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1271,12 +1268,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ __HAL_UNLOCK(hi2s);
/* Check if the I2S Rx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
@@ -1285,7 +1277,13 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
- __HAL_UNLOCK(hi2s);
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
return HAL_OK;
}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c
index c65b792c9..1d61feb9b 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c
@@ -120,7 +120,8 @@
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
+ ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c
index 68cf226a2..4dd65562e 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c
@@ -2328,7 +2328,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c
index 88930cad3..c536e2118 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c
@@ -507,7 +507,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig)
{
hnand->Config.PageSize = pDeviceConfig->PageSize;
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
@@ -2037,6 +2037,7 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
status = HAL_ERROR;
}
+ return status;
}
/**
@@ -2095,6 +2096,7 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
status = HAL_ERROR;
}
+ return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c
index ec246b445..49e9b59ee 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c
@@ -163,7 +163,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
- FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+ FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
+ FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
{
/* Check the PCCARD controller state */
if (hpccard == NULL)
@@ -187,7 +188,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_T
#else
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
}
/* Initialize the PCCARD state */
@@ -234,7 +235,7 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
#else
/* De-Initialize the low level hardware (MSP) */
HAL_PCCARD_MspDeInit(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Configure the PCCARD registers with their reset values */
FSMC_PCCARD_DeInit(hpccard->Instance);
@@ -307,8 +308,9 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
- uint8_t status = 0;
+ uint32_t timeout = 0U;
+ uint32_t index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -371,8 +373,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
- uint8_t status = 0;
+ uint32_t timeout = 0U;
+ uint32_t index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -448,8 +451,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
- uint8_t status = 0;
+ uint32_t timeout = 0U;
+ uint32_t index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -522,7 +526,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
- uint8_t status = 0;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -624,7 +628,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Rising edge pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
@@ -638,7 +642,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Level pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
@@ -652,7 +656,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Falling edge pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
@@ -666,7 +670,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt FIFO empty pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
@@ -823,7 +827,7 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, H
__HAL_UNLOCK(hpccard);
return status;
}
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
@@ -866,7 +870,8 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U;
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS;
+ uint32_t status_pccard = 0U;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
@@ -902,7 +907,8 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint8_t data = 0U, status_pccard = PCCARD_BUSY;
+ uint8_t data = 0U;
+ uint8_t status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c
index e01efe5ed..6a897389f 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c
@@ -130,9 +130,6 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
-#if defined (USB_OTG_FS)
- USB_OTG_GlobalTypeDef *USBx;
-#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
@@ -144,10 +141,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-#if defined (USB_OTG_FS)
- USBx = hpcd->Instance;
-#endif /* defined (USB_OTG_FS) */
-
if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -181,13 +174,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
-#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
- if ((USBx->CID & (0x1U << 8)) == 0U)
- {
- hpcd->Init.dma_enable = 0U;
- }
-#endif /* defined (USB_OTG_FS) */
+ hpcd->Init.dma_enable = 0U;
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -199,8 +187,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
return HAL_ERROR;
}
- /* Force Device Mode*/
- (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+ /* Force Device Mode */
+ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
@@ -2115,9 +2107,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (gSNPSiD == USB_OTG_CORE_ID_310A)
@@ -2162,9 +2154,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c
index db94d3b50..8713b9f2a 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c
@@ -403,7 +403,6 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
- HAL_StatusTypeDef status;
SD_InitTypeDef Init;
/* Default SDIO peripheral configuration for SD card initialization */
@@ -415,11 +414,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
Init.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO peripheral interface with default configuration */
- status = SDIO_Init(hsd->Instance, Init);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ SDIO_Init(hsd->Instance, Init);
/* Disable SDIO Clock */
__HAL_SD_DISABLE(hsd);
@@ -692,7 +687,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@@ -903,7 +898,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@@ -2864,13 +2859,13 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
}
@@ -2892,7 +2887,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
*pData = SDIO_ReadFIFO(hsd->Instance);
pData++;
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3084,13 +3079,13 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
break;
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c
index 634cdd0df..16c9c9350 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c
@@ -44,7 +44,8 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+ or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -190,7 +191,8 @@
@note The max SPI frequency depend on SPI data size (8bits, 16bits),
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
@note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and
+ HAL_SPI_TransmitReceive_DMA()
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
@@ -790,38 +792,35 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
uint16_t initial_TxXferCount;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
initial_TxXferCount = Size;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -860,7 +859,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -870,7 +869,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -879,9 +878,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -891,7 +890,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
@@ -900,7 +899,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
@@ -909,9 +908,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -936,19 +935,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -966,12 +964,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@@ -981,18 +977,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1051,9 +1046,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1075,9 +1070,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1100,8 +1095,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Receive last data in 16 Bit mode */
@@ -1119,8 +1114,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC to Flush DR and RXNE flag */
@@ -1155,18 +1151,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
}
#endif /* USE_SPI_CRC */
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1179,8 +1174,8 @@ error :
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
{
uint16_t initial_TxXferCount;
uint32_t tmp_mode;
@@ -1192,14 +1187,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -1209,18 +1200,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
initial_TxXferCount = Size;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1232,7 +1225,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
@@ -1260,16 +1253,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1295,9 +1297,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1306,16 +1308,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1341,9 +1351,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1357,8 +1367,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC */
tmpreg = READ_REG(hspi->Instance->DR);
@@ -1376,8 +1387,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
-
- errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
else
{
@@ -1389,9 +1400,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- errorcode = HAL_ERROR;
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
@@ -1400,18 +1411,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1422,32 +1434,30 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1483,10 +1493,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
@@ -1494,9 +1500,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
-error :
+ /* Process Unlocked */
__HAL_UNLOCK(hspi);
- return errorcode;
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ return HAL_OK;
}
/**
@@ -1509,13 +1518,10 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -1525,15 +1531,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1573,9 +1579,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
/* Note : The SPI must be enabled after unlocking current process
to avoid the risk of SPI interrupt handle execution before current
process unlock */
@@ -1587,10 +1590,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
- return errorcode;
+ /* Enable RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ return HAL_OK;
}
/**
@@ -1602,35 +1607,34 @@ error :
* @param Size amount of data to be sent and received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1639,7 +1643,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -1666,8 +1670,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
}
#endif /* USE_SPI_CRC */
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1676,10 +1678,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
- return errorcode;
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ return HAL_OK;
}
/**
@@ -1690,9 +1694,8 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
@@ -1700,25 +1703,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1763,9 +1764,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -1775,16 +1776,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1799,15 +1800,12 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -1821,15 +1819,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1877,9 +1874,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -1889,16 +1886,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1911,12 +1908,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check rx & tx dma handles */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
@@ -1925,26 +1921,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1953,7 +1948,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -1998,9 +1993,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Enable Rx DMA Request */
@@ -2019,9 +2014,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -2030,16 +2025,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2403,9 +2399,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback()
*/
/* Abort the SPI DMA tx Stream/Channel */
@@ -2690,7 +2688,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI state
*/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
{
/* Return SPI handle state */
return hspi->State;
@@ -2702,7 +2700,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
{
/* Return SPI ErrorCode */
return hspi->ErrorCode;
@@ -2729,7 +2727,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
/* Init tickstart for timeout management*/
@@ -2786,7 +2784,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -2885,7 +2883,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -2975,7 +2973,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Tx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -2993,7 +2991,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Rx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3011,7 +3009,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user TxRx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -3029,7 +3027,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
@@ -3052,7 +3050,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
@@ -3074,7 +3072,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
__IO uint32_t count;
hspi->hdmatx->XferAbortCallback = NULL;
@@ -3138,7 +3136,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -3259,7 +3257,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -3352,7 +3350,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -3514,7 +3512,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -3540,7 +3538,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -3673,6 +3671,13 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
+ /* Wait until TXE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
@@ -3988,7 +3993,8 @@ uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
{
#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
/* Check how to handle this CRC error (workaround to be applied or not) */
- /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
+ /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES
+ (DocID14732 Rev 13)) */
if (hspi->Instance == SPI2)
{
if (hspi->Instance->RXCRCR == 0U)
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c
index d136ea439..c5a37190d 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c
@@ -209,7 +209,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy
/* Initialize SRAM extended mode timing Interface */
(void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
- hsram->Init.ExtendedMode);
+ hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
@@ -1038,6 +1038,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1060,6 +1061,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1082,6 +1084,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c
index 40cee887d..c00a9deff 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c
@@ -3821,13 +3821,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
+ uint32_t itsource = htim->Instance->DIER;
+ uint32_t itflag = htim->Instance->SR;
+
/* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -3855,11 +3858,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3885,11 +3888,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3915,11 +3918,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3945,11 +3948,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -3958,11 +3961,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@@ -3971,11 +3974,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@@ -3984,11 +3987,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@@ -4475,7 +4478,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -6809,6 +6813,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -6933,7 +6944,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c
index ff8c8f59f..8a565a6b9 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c
@@ -835,7 +835,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1081,17 +1081,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
@endverbatim
* @{
*/
@@ -1317,7 +1306,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -2100,7 +2089,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
*/
/**
- * @brief Hall commutation changed callback in non-blocking mode
+ * @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2114,7 +2103,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
*/
}
/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2129,7 +2118,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
}
/**
- * @brief Hall Break detection callback in non-blocking mode
+ * @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2280,15 +2269,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
else
{
/* nothing to do */
@@ -2357,13 +2337,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
{
uint32_t tmp;
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
}
/**
* @}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c
index 6ab2edd0f..dba7cbbdd 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c
@@ -112,76 +112,94 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
#else
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
-
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ if (status == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ if (status == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
- hRTC_Handle.Instance = RTC;
/* Configure RTC time base to 10Khz */
+ hRTC_Handle.Instance = RTC;
hRTC_Handle.Init.AsynchPrediv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC) / 10000) - 1;
hRTC_Handle.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
- HAL_RTC_Init(&hRTC_Handle);
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ status = HAL_RTC_Init(&hRTC_Handle);
+ }
+ }
+ if (status == HAL_OK)
+ {
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
- counter = 0U;
- /* Wait till RTC ALRAF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF) != RESET)
+ counter = 0U;
+ /* Wait till RTC ALRAF flag is set and if Time out is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF) != RESET)
+ {
+ if (counter++ == SystemCoreClock / 48U) /* Timeout = ~ 1s */
{
- if (counter++ == SystemCoreClock / 48U) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
+ status = HAL_ERROR;
}
+ }
+ }
+ if (status == HAL_OK)
+ {
+ /* Set RTC COUNTER MSB word */
+ hRTC_Handle.Instance->ALRH = 0x00U;
+ /* Set RTC COUNTER LSB word */
+ hRTC_Handle.Instance->ALRL = 0x09U;
- /* Set RTC COUNTER MSB word */
- hRTC_Handle.Instance->ALRH = 0x00U;
- /* Set RTC COUNTER LSB word */
- hRTC_Handle.Instance->ALRL = 0x09U;
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
- /* Clear Second and overflow flags */
- CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
+ /* Clear Second and overflow flags */
+ CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
- /* Set RTC COUNTER MSB word */
- hRTC_Handle.Instance->CNTH = 0x00U;
- /* Set RTC COUNTER LSB word */
- hRTC_Handle.Instance->CNTL = 0x00U;
+ /* Set RTC COUNTER MSB word */
+ hRTC_Handle.Instance->CNTH = 0x00U;
+ /* Set RTC COUNTER LSB word */
+ hRTC_Handle.Instance->CNTL = 0x00U;
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- counter = 0U;
- while ((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ counter = 0U;
+ while ((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
+ {
+ if (counter++ == SystemCoreClock / 48U) /* Timeout = ~ 1s */
{
- if (counter++ == SystemCoreClock / 48U) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
+ status = HAL_ERROR;
}
+ }
+ }
+ if (status == HAL_OK)
+ {
+ /* Enable the RTC global Interrupt */
+ HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
- HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
- return HAL_OK;
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority ,0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
}
}
- return HAL_ERROR;
+
+ return status;
}
/**
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c
index 9e2dee084..4a00f663e 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c
@@ -100,14 +100,31 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
TimHandle.Init.ClockDivision = 0U;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ status = HAL_TIM_Base_Init(&TimHandle);
+ if (status == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
- return HAL_TIM_Base_Start_IT(&TimHandle);
+ status = HAL_TIM_Base_Start_IT(&TimHandle);
+ if (status == HAL_OK)
+ {
+ /* Enable the TIM2 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM2_IRQn);
+
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ /*Configure the TIM2 IRQ priority */
+ HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
}
/* Return function status */
- return HAL_ERROR;
+ return status;
}
/**
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c
index db1f087bd..b7cf66cc7 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c
@@ -1174,6 +1174,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1191,6 +1193,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
@@ -1258,6 +1262,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->RxState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1786,21 +1792,18 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
status = UART_Start_Receive_DMA(huart, pData, Size);
/* Check Rx process has been successfully started */
- if (status == HAL_OK)
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- {
- __HAL_UART_CLEAR_IDLEFLAG(huart);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
- else
- {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception abortion.
- (Overrun error for instance).
- In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
+ __HAL_UART_CLEAR_IDLEFLAG(huart);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
}
return status;
@@ -3188,19 +3191,31 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
+ return HAL_TIMEOUT;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
+ {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+ {
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_OREFLAG(huart);
- return HAL_TIMEOUT;
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_ERROR;
+ }
}
}
}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c
index eb5bacd01..4423252ea 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c
@@ -2081,6 +2081,9 @@ uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
return husart->ErrorCode;
}
+/**
+ * @}
+ */
/**
* @}
*/
@@ -2782,7 +2785,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/
- if((husart->Instance == USART1))
+ if (husart->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
@@ -2794,10 +2797,6 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
}
}
-/**
- * @}
- */
-
/**
* @}
*/
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c
index af3093a4b..dbf3aadee 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c
@@ -21,82 +21,108 @@
******************************************************************************
@verbatim
==============================================================================
- ##### WWDG specific features #####
+ ##### WWDG Specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
+ time period, unless the program refreshes the counter (T[6;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
+ value rolls down from 0x40 to 0x3F).
(+) An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
- (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+ (+) If required by application, an Early Wakeup Interrupt can be triggered
+ in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+ (EWI) can be used if specific safety operations or data logging must
+ be performed before the actual reset is generated. When the downcounter
+ reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+ line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+ disabled except by a system reset.
+ (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
- (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+ where T[5;0] are the lowest 6 bits of Counter.
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
- (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
-
- (+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms
-
- (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
- operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40, an EWI interrupt
- is generated and the corresponding interrupt service routine (ISR) can
- be used to trigger specific actions (such as communications or data
- logging), before resetting the device.
- In some applications, the EWI interrupt can be used to manage a software
- system check and/or system recovery/graceful degradation, without
- generating a WWDG reset. In this case, the corresponding interrupt
- service routine (ISR) should reload the WWDG counter to avoid the WWDG
- reset, then trigger the required actions.
- Note:When the EWI interrupt cannot be served, e.g. due to a system lock
- in a higher priority task, the WWDG reset will eventually be generated.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the WWDG counter either continues to work normally or stops, depending
- on DBG_WWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (+) Typical values:
+ (++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 910us
+ (++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler
+ dividing by 8:
+ max timeout before reset: approximately 58.25ms
##### How to use this driver #####
==============================================================================
- [..]
- (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
- (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
- Interrupt mode using using HAL_WWDG_Init() function.
- This enables WWDG peripheral and the downcounter starts downcounting
- from given counter value.
- Init function can be called again to modify all watchdog parameters,
- however if EWI mode has been set once, it can't be clear until next
- reset.
+ *** Common driver usage ***
+ ===========================
- (+) The application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset using
+ [..]
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+ (+) Configure the WWDG prescaler, refresh window value, counter value and early
+ interrupt status using HAL_WWDG_Init() function. This will automatically
+ enable WWDG and start its downcounter. Time reference can be taken from
+ function exit. Care must be taken to provide a counter value
+ greater than 0x40 to prevent generation of immediate reset.
+ (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+ generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+ triggered by the interrupt service routine, flag will be automatically
+ cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+ can add his own code by customization of callback HAL_WWDG_WakeupCallback.
+ (+) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the window value already programmed.
+ the counter is lower than the refresh window value already programmed.
- (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
- the counter reaches 0x40. User can add his own code in weak function
- HAL_WWDG_EarlyWakeupCallback().
+ *** Callback registration ***
+ =============================
- *** WWDG HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in WWDG HAL driver.
-
- (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+ [..]
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ the user to configure dynamically the driver callbacks. Use Functions
+ HAL_WWDG_RegisterCallback() to register a user callback.
+
+ (+) Function HAL_WWDG_RegisterCallback() allows to register following
+ callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
+ takes as parameters the HAL peripheral handle and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+
+ [..]
+ When calling HAL_WWDG_Init function, callbacks are reset to the
+ corresponding legacy weak (surcharged) functions:
+ HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ not been registered before.
+
+ [..]
+ When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ *** WWDG HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of available macros in WWDG HAL driver.
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c
index 3d42565db..f783c9977 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c
@@ -60,7 +60,7 @@
* @{
*/
#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \
- || defined(HAL_SRAM_MODULE_ENABLED)
+ || defined(HAL_SRAM_MODULE_ENABLED)
/** @defgroup FSMC_LL FSMC Low Layer
* @brief FSMC driver modules
@@ -206,7 +206,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_InitTypeDef *Init)
+ const FSMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
@@ -289,7 +289,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+ FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
@@ -326,7 +326,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
@@ -341,13 +341,14 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set FSMC_NORSRAM device timing parameters */
- MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) |
- ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ Device->BTCR[Bank + 1U] =
+ (Timing->AddressSetupTime << FSMC_BTRx_ADDSET_Pos) |
+ (Timing->AddressHoldTime << FSMC_BTRx_ADDHLD_Pos) |
+ (Timing->DataSetupTime << FSMC_BTRx_DATAST_Pos) |
+ (Timing->BusTurnAroundDuration << FSMC_BTRx_BUSTURN_Pos) |
+ ((Timing->CLKDivision - 1U) << FSMC_BTRx_CLKDIV_Pos) |
+ ((Timing->DataLatency - 2U) << FSMC_BTRx_DATLAT_Pos) |
+ Timing->AccessMode;
return HAL_OK;
}
@@ -365,8 +366,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
- uint32_t ExtendedMode)
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
@@ -526,7 +527,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
* @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
@@ -574,7 +575,7 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
@@ -614,7 +615,7 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
@@ -761,8 +762,8 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank
* @param Timeout Timeout wait value
* @retval HAL status
*/
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
- uint32_t Timeout)
+HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -854,7 +855,7 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
* @param Init Pointer to PCCARD Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
@@ -888,7 +889,7 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
@@ -917,7 +918,7 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
@@ -946,7 +947,7 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c
index 5f557d3aa..e528a6958 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c
@@ -119,7 +119,7 @@
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
@@ -168,8 +168,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in SPI configuration registers can only be written when the
+ * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior
+ * calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
@@ -348,7 +349,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
{
return LL_SPI_DeInit(SPIx);
}
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c
index 6e01d0f68..f111d51b1 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c
@@ -766,8 +766,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -795,8 +793,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -845,8 +845,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -874,8 +872,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -924,8 +924,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -953,8 +951,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1003,8 +1003,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1032,7 +1030,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
/* Set the Output Idle state */
@@ -1054,7 +1051,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
return SUCCESS;
}
-
/**
* @brief Configure the TIMx input channel 1.
* @param TIMx Timer Instance
diff --git a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c
index a25f30580..7e481aafe 100644
--- a/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c
+++ b/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c
@@ -221,9 +221,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDe
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else if (mode == USB_DEVICE_MODE)
{
@@ -231,16 +231,16 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDe
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else
{
return HAL_ERROR;
}
- if (ms == 50U)
+ if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
{
return HAL_ERROR;
}
@@ -383,7 +383,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -397,7 +397,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -420,7 +420,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -434,7 +434,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -452,7 +452,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -467,7 +467,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
* This parameter can be one of these values:
* @arg USBD_FS_SPEED: Full speed mode
*/
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t speed;
@@ -492,7 +492,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -530,7 +530,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -569,7 +569,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -616,7 +616,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -792,7 +792,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
__IO uint32_t count = 0U;
HAL_StatusTypeDef ret = HAL_OK;
@@ -852,7 +852,7 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param len Number of bytes to write
* @retval HAL status
*/
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -880,7 +880,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
* @param len Number of bytes to read
* @retval pointer to destination buffer
*/
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t *pDest = dest;
@@ -922,7 +922,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -953,7 +953,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -1023,7 +1023,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1038,7 +1038,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1055,7 +1055,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1088,7 +1088,7 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
* @param chnum Channel number
* @retval USB Channel Interrupt status
*/
-uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1104,7 +1104,7 @@ uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
* @param USBx Selected device
* @retval USB Device OUT EP interrupt status
*/
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1120,7 +1120,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval USB Device IN EP interrupt status
*/
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1138,7 +1138,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1156,7 +1156,7 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1190,7 +1190,7 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
* 0 : Host
* 1 : Device
*/
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
return ((USBx->GINTSTS) & 0x1U);
}
@@ -1200,7 +1200,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1218,10 +1218,10 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
* @param psetup pointer to setup packet
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
UNUSED(psetup);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
@@ -1254,7 +1254,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1268,7 +1268,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1349,7 +1349,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1379,7 +1379,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
* @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
*/
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1406,7 +1406,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
* 1 : Activate VBUS
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0 = 0U;
@@ -1704,7 +1704,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
* @param USBx Selected device
* @retval HAL state
*/
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1718,7 +1718,7 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t hcnum = (uint32_t)hc_num;
@@ -1802,7 +1802,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t chnum = (uint32_t)ch_num;
@@ -1891,7 +1891,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1909,7 +1909,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
diff --git a/stm32cube/stm32f1xx/release_note.html b/stm32cube/stm32f1xx/release_note.html
index 754d1b084..f7b5c57ca 100644
--- a/stm32cube/stm32f1xx/release_note.html
+++ b/stm32cube/stm32f1xx/release_note.html
@@ -36,7 +36,7 @@
Purpose
A consistent set of middleware components such as RTOS, USB, TCP/IP, Graphics
All embedded software utilities come with a full set of examples.
-
The STM32Cube firmware solution offers a straightforward API with a modular architecture, making it simple to fine tune custom applications and scalable to fit most requirements
+
The STM32Cube firmware solution offers a straightforward API with a modular architecture, making it simple to fine tune custom applications and scalable to fit most requirements
The HAL (Hardware Abstraction Layer) drivers provided within this package supports the following STM32F100xx STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx Series.
@@ -59,12 +59,224 @@
Purpose
Update History
-
+
Maintenance release
Main Changes
Patch release to fix known defects and enhancements implementation.
+
Upgrade FreeRTOS Lib to use v10.3.1 (ST modified 2023-08-18).
+
CMSIS updates
+
+
Update defined value of SystemCoreClock to be aligned with HSI value.
+
+
HAL updates
+
+
HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
+
LL/HAL CORTEX driver
+
+
Update HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
+
Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().
+
+
HAL FLASH driver
+
+
Remove HAL_LOCK/HAL_UNLOCK() from HAL_FLASH_Program_IT() and HAL_FLASHEx_Erase_IT() APIs.
+
+
HAL GPIO driver
+
+
Replace GPIO_Pin_x with GPIO_PIN_x to be compliant with macros definition.
+
+
HAL CAN driver
+
+
Clarify pin configuration in driver header by removing open-drain information.
+
+
HAL I2C driver
+
+
Update HAL_I2C_Mem_Read() API to clear ACK bit once 3 bytes to read remain to be able to send the NACK once the transfer ends.
+
Update HAL_I2C_Master_Abort_IT() API to support memory abort transfer.
+
Update the HAL I2C driver to reset PreviousState to I2C_STATE_NONE at the end of transfer.
+
+
HAL SDMMC driver
+
+
Update HAL SD processes to manage STBITERR flag.
+
+
HAL SPI driver
+
+
Update HAL_SPI_TransmitReceive() API to set the bit CRCNEXT in case of one byte transaction
+
Update IT APIs to enable interrupts after process unlock.
+
Add wait on flag TXE to be set at the end of transaction to be aligned with reference manual.
+
+
HAL I2S driver
+
+
Update HAL I2S driver to fix misplaced __HAL_LOCK() and remove ‘go to’ instruction.
+
+
LL/HAL TIM driver
+
+
Improve performance by removing multiple volatile reads or writes in interrupt handler.
+
HAL TIM driver’s operational behavior improvement.
+
Improve period configuration parameter check.
+
Update interrupt flag is cleared when the update event is generated by software.
+
Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().
+
Add LL_TIM_CC_IsEnabledPreload() API.
+
+
HAL UART driver
+
+
Avoid ORE flag to be cleared by a transmit process in polling mode.
+
Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
+
+
HAL USB_OTG driver
+
+
Fix device connection in case battery charging is used with HS instance linked to internal FS PHY.
+
ll_usb.c: increase timeout value to allow core reset to complete
+
ll_usb.c: improve delay management to set core mode
+
+
LL UTILS driver
+
+
Fix ‘Ticks’ parameter’s description of LL_InitTick() API.
+
+
+
Middleware
+
+
Upgrade FreeRTOS Lib to use v10.3.1 (ST modified 2023-08-18).
+
+
Projects updates
+
+
STM3210C_EVAL
+
+
USB Host MSC applications: fix stack corruption due to inconsistent type of local variable in MSC_File_Operations() API.
+
+
+
+
Contents
+
+
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Only template projects are migrated to Arm Compiler 6 with MDK-ARM 5.31 (“AC-like Warnings” mode).
+
+
System Workbench for STM32 (SW4STM32) (7-2018-q2-update) toolchain V2.9.0 + ST-Link
+
+
+
+
+
+
+
Maintenance release
+
Main Changes
+
+
Patch release to fix known defects and enhancements implementation.
All source files: update disclaimer to add reference to the new license agreement.
CMSIS updates
@@ -212,7 +424,7 @@
Main Changes
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
@@ -302,7 +514,7 @@
Contents
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 (or upper) + ST-LINK, pack available here:
@@ -317,8 +529,8 @@
Development Toolchains and Compile
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release to fix known defects and enhancements implementation.
CMSIS updates
@@ -451,7 +663,7 @@
Main Changes
Update examples and applications to avoid clearing DMA using global flag GIFx.
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -516,7 +728,7 @@
Contents
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-LINK
@@ -527,8 +739,8 @@
Development Toolchains and Compi
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release of STM32CubeF1 Firmware Package.
HAL
@@ -546,7 +758,7 @@
Main Changes
-
Contents
+
Contents
Drivers
@@ -569,8 +781,8 @@
Contents
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release to fix known defects and enhancements implementation
HAL
@@ -758,7 +970,7 @@
Main Changes
SystemInit(): update to don’t reset RCC registers to its reset values.
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -818,11 +1030,11 @@
Contents
-
Known Limitations
+
Known Limitations
SW4STM32 projects aren’t provided for STM32VL-Discovery board because it embeds STLinv1 version that is not hardware supported by SW4STM32 toolchain.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.26 + ST-LINK
@@ -849,8 +1061,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release to fix known defects and enhancements implementation
HAL
@@ -902,7 +1114,7 @@
Main Changes
-
Contents
+
Contents
Drivers
@@ -925,8 +1137,8 @@
Contents
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General updates to fix known defects and enhancements implementation
Remove support of TrueSTUDIO tool chain
@@ -1018,7 +1230,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -1233,12 +1445,12 @@
Contents
-
Known Limitations
+
Known Limitations
SW4STM32 projects aren’t provided for STM32VL-Discovery board because it embeds STLinv1 version that is not hardware supported by SW4STM32 toolchain.
Register callback feature will be deployed on HAL I2C driver in next release
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.26 + ST-LINK
@@ -1265,8 +1477,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General update to fix known defects and several implementations enhancement
The following changes done on the HAL drivers require an update on the application code based on older HAL versions
@@ -1294,7 +1506,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -1509,11 +1721,11 @@
Contents
-
Known Limitations
+
Known Limitations
SW4STM32 projects aren’t provided for STM32VL-Discovery board because it embeds STLinv1 version that is not hardware supported by SW4STM32 toolchain.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23
@@ -1541,12 +1753,12 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release to fix issues in GPIO, RCC, SMARTCARD, I2C and Generic HAL/LL drivers
-
Contents
+
Contents
@@ -1568,8 +1780,8 @@
Contents
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General update to fix known defects and several implementations enhancement
HAL
@@ -1584,7 +1796,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -1799,11 +2011,11 @@
Contents
-
Known Limitations
+
Known Limitations
SW4STM32 projects aren’t provided for STM32VL-Discovery board because it embeds STLinv1 version that is not hardware supported by SW4STM32 toolchain.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23
@@ -1831,8 +2043,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Add Low Layer drivers under Drivers32F1xx_HAL_Driver
@@ -1919,7 +2131,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -2134,11 +2346,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23
@@ -2166,8 +2378,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Maintenance release to fix known defects and several enhancements implementation.
HAL
@@ -2233,7 +2445,7 @@
Main Changes
Add latest version of STM32CubeUpdater (V4.10.0).
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -2447,11 +2659,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.17 + ST-LINK
@@ -2479,15 +2691,15 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release to fix issue in HAL driver:
Remove the #if defined(USE_HAL_LEGACY) condition to include Legacy/stm32_hal_legacy.h by default, in stm32f1xx_hal_def.h.
-
Contents
+
Contents
@@ -2504,11 +2716,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.17 + ST-LINK
@@ -2536,8 +2748,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Maintenance release to fix known defects and several enhancements implementation.
HAL
@@ -2570,7 +2782,7 @@
Main Changes
Add latest version of STM32CubeUpdater (V4.10.0).
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -2785,11 +2997,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.17 + ST-LINK
@@ -2817,8 +3029,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Maintenance release.
Fix known defects and several enhancements implementation.
@@ -2864,7 +3076,7 @@
Main Changes
CMSIS-RTOS V1.02 (unchanged)
-
Contents
+
Contents
The STM32CubeF1 Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with pre-configured projects for the main supported toolchains. The exhaustive list of projects is provided in this table STM32CubeProjectsList.html.
Projects release notes
@@ -3072,11 +3284,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -34,4 +33,3 @@
#endif /* __STM32F2xx_HAL_DCMI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_hash.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_hash.h
index 5712f532d..c14670185 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_hash.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_hash.h
@@ -117,13 +117,13 @@ typedef struct
{
HASH_InitTypeDef Init; /*!< HASH required parameters */
- uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+ uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
- uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
+ uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
uint32_t HashBuffSize; /*!< Size of buffer to be processed */
@@ -434,15 +434,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
/* HASH processing using polling *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout);
@@ -455,15 +457,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
*/
/* HASH processing using IT **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
@@ -475,9 +477,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
*/
/* HASH processing using DMA *************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
@@ -489,9 +491,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu
*/
/* HASH-MAC processing using polling *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout);
/**
@@ -502,9 +506,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @{
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer);
/**
@@ -516,8 +520,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
*/
/* HASH-HMAC processing using DMA ********************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
/**
* @}
@@ -529,13 +533,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
/* Peripheral State methods **************************************************/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
+HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash);
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
+uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
/**
* @}
@@ -552,19 +556,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
*/
/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm);
/**
* @}
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_nand.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_nand.h
index 9dca732b0..75289858a 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_nand.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_nand.h
@@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_Timing
FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pccard.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pccard.h
index ef7df02c0..f9e23b996 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pccard.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pccard.h
@@ -67,7 +67,7 @@ typedef enum
typedef struct __PCCARD_HandleTypeDef
#else
typedef struct
-#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
{
FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
@@ -81,7 +81,7 @@ typedef struct
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
} PCCARD_HandleTypeDef;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
@@ -99,7 +99,7 @@ typedef enum
* @brief HAL PCCARD Callback pointer definition
*/
typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -121,7 +121,7 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
} while(0)
#else
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -136,7 +136,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
- FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+ FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
+ FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
@@ -164,7 +165,7 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HA
pPCCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
HAL_PCCARD_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pcd.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pcd.h
index 173d4d22b..247c3ee87 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pcd.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_pcd.h
@@ -354,7 +354,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode);
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc.h
index e975bdcfe..e93c9caf8 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc.h
@@ -726,7 +726,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
#define RTC_TIMEOUT_VALUE 1000U
-#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 connected to the RTC Alarm event */
/**
* @}
*/
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc_ex.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc_ex.h
index b72c22f9d..520cf31e6 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc_ex.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_rtc_ex.h
@@ -527,13 +527,13 @@ typedef struct
* @brief Enable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Disable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
@@ -715,7 +715,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
* @{
*/
/* Extended RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_spi.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_spi.h
index 68503e4e4..072c88853 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_spi.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_spi.h
@@ -107,7 +107,7 @@ typedef struct __SPI_HandleTypeDef
SPI_InitTypeDef Init; /*!< SPI communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
@@ -339,11 +339,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval None
*/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
@@ -444,7 +445,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
__IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
- }while(0U)
+ } while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
@@ -488,8 +489,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
+#define SPI_RESET_CRC(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
+ } while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR register.
@@ -505,7 +509,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
- ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
+ ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 register.
@@ -517,7 +521,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
- (__INTERRUPT__)) ? SET : RESET)
+ (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
@@ -627,7 +631,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
- (((__POLYNOMIAL__)&0x1U) != 0U))
+ (((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
@@ -667,17 +671,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @{
*/
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
@@ -703,8 +707,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
* @{
*/
/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
/**
* @}
*/
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_tim.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_tim.h
index 1eb13ac4d..235806abe 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_tim.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_tim.h
@@ -385,29 +385,28 @@ typedef struct
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@@ -1654,8 +1653,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
-#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
- ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+ (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
+ ((__PERIOD__) > 0U))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
@@ -1708,7 +1708,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
@@ -2046,7 +2045,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_usart.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_usart.h
index 552a6ebe2..eb4b00df4 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_usart.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_usart.h
@@ -624,7 +624,7 @@ uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup USART_Private_Functions USART Private Functions
+/** @addtogroup USART_Private_Functions
* @{
*/
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_wwdg.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_wwdg.h
index 3d865e5cb..f95211d44 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_wwdg.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_hal_wwdg.h
@@ -183,7 +183,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_adc.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_adc.h
index 8eb1987a1..59fd2e71d 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_adc.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_adc.h
@@ -1656,18 +1656,17 @@ typedef struct
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((( ( \
- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
- * 1000) \
- - \
- (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
- * 1000) \
- ) \
- ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
- ) + (__TEMPSENSOR_CALX_TEMP__) \
- )
+ __ADC_RESOLUTION__) \
+(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000UL) \
+ - \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000UL) \
+ ) \
+ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
+)
/**
* @}
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_cortex.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_cortex.h
index 33a836243..3c76a065e 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_cortex.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_cortex.h
@@ -587,7 +587,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
- WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
}
/**
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_dac.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_dac.h
index 9207a1035..1ab688c92 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_dac.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_dac.h
@@ -87,7 +87,6 @@ extern "C" {
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-
#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
@@ -471,7 +470,7 @@ typedef struct
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval DAC conversion data (unit: digital value)
*/
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
/ (__VREFANALOG_VOLTAGE__) \
)
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_fsmc.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_fsmc.h
index 771cfff33..29abb61cd 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_fsmc.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_fsmc.h
@@ -40,42 +40,42 @@ extern "C" {
*/
#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
- ((__BANK__) == FSMC_NORSRAM_BANK2) || \
- ((__BANK__) == FSMC_NORSRAM_BANK3) || \
- ((__BANK__) == FSMC_NORSRAM_BANK4))
+ ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK4))
#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+ ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
- ((__MODE__) == FSMC_ACCESS_MODE_B) || \
- ((__MODE__) == FSMC_ACCESS_MODE_C) || \
- ((__MODE__) == FSMC_ACCESS_MODE_D))
+ ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_D))
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+ ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+ ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+ ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+ ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+ ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+ ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+ ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+ ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+ ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
@@ -88,18 +88,18 @@ extern "C" {
#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+ ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+ ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FSMC_NAND_ECC_ENABLE))
+ ((__STATE__) == FSMC_NAND_ECC_ENABLE))
#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
@@ -137,52 +137,53 @@ extern "C" {
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing*/
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
- This parameter can be a value of @ref FSMC_Memory_Type */
+ This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
+ This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
+ This parameter can be a value of @ref FSMC_Wait_Timing */
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device
+ by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
+ This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
+ This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
+ This parameter can be a value of @ref FSMC_Write_Burst */
} FSMC_NORSRAM_InitTypeDef;
@@ -227,7 +228,7 @@ typedef struct
in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
+ This parameter can be a value of @ref FSMC_Access_Mode */
} FSMC_NORSRAM_TimingTypeDef;
/**
@@ -305,7 +306,7 @@ typedef struct
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FSMC_PCCARD_InitTypeDef;
+} FSMC_PCCARD_InitTypeDef;
/**
* @}
@@ -586,7 +587,7 @@ typedef struct
* @retval None
*/
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- |= FSMC_BCR1_MBKEN)
+ |= FSMC_BCR1_MBKEN)
/**
* @brief Disable the NORSRAM device access.
@@ -595,7 +596,7 @@ typedef struct
* @retval None
*/
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- &= ~FSMC_BCR1_MBKEN)
+ &= ~FSMC_BCR1_MBKEN)
/**
* @}
@@ -612,8 +613,9 @@ typedef struct
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
-#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN) : \
+ ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
/**
* @brief Disable the NAND device access.
@@ -621,8 +623,9 @@ typedef struct
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
-#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \
- CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN))
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN) : \
+ CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN))
/**
* @}
@@ -665,8 +668,9 @@ typedef struct
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
-#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
@@ -679,8 +683,9 @@ typedef struct
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
-#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
/**
* @brief Get flag status of the NAND device.
@@ -694,8 +699,9 @@ typedef struct
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
-#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
@@ -709,8 +715,9 @@ typedef struct
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
-#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
+ ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
/**
* @}
@@ -795,14 +802,14 @@ typedef struct
* @{
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_InitTypeDef *Init);
+ const FSMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
- uint32_t ExtendedMode);
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode);
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+ FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
@@ -825,11 +832,11 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev
/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
* @{
*/
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
@@ -840,8 +847,8 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
- uint32_t Timeout);
+HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout);
/**
* @}
*/
@@ -855,13 +862,13 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
* @{
*/
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
+ const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
/**
* @}
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_iwdg.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_iwdg.h
index dc0eb4dac..91c38004a 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_iwdg.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_iwdg.h
@@ -207,7 +207,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
@@ -230,7 +230,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
@@ -249,7 +249,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
@@ -260,7 +260,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
@@ -272,7 +272,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
}
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_rtc.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_rtc.h
index 5ca0a5f99..76da8f3f8 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_rtc.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_rtc.h
@@ -391,8 +391,8 @@ typedef struct
/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
* @{
*/
-#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
-#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
+#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp event */
/**
* @}
*/
@@ -935,7 +935,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma
/**
* @brief Get time format (AM or PM notation)
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -969,7 +969,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
/**
* @brief Get Hours in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1004,7 +1004,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
/**
* @brief Get Minutes in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1039,7 +1039,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
/**
* @brief Get Seconds in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1089,7 +1089,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
/**
* @brief Get time (hour, minute and second) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1193,7 +1193,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
/**
* @brief Get Year in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
* @rmtoll DR YT LL_RTC_DATE_GetYear\n
@@ -1227,7 +1227,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
/**
* @brief Get Week day
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
* @param RTCx RTC Instance
@@ -1274,7 +1274,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
/**
* @brief Get Month in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll DR MT LL_RTC_DATE_GetMonth\n
@@ -1316,7 +1316,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
/**
* @brief Get Day in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll DR DT LL_RTC_DATE_GetDay\n
@@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
/**
* @brief Get date (WeekDay, Day, Month and Year) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter.
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_sdmmc.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_sdmmc.h
index 255c7f28c..51855dcc7 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_sdmmc.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_sdmmc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2018 STMicroelectronics.
+ * Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -300,10 +300,14 @@ typedef struct
#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
#define SDMMC_CARD_LOCKED 0x02000000U
-#ifndef SDMMC_DATATIMEOUT
-#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */
+#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
#endif /* SDMMC_DATATIMEOUT */
+#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
+#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT
+#endif /* SDMMC_SWDATATIMEOUT */
+
#define SDMMC_0TO7BITS 0x000000FFU
#define SDMMC_8TO15BITS 0x0000FF00U
#define SDMMC_16TO23BITS 0x00FF0000U
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_spi.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_spi.h
index 10d9772f9..a14e286c6 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_spi.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_spi.h
@@ -55,53 +55,66 @@ typedef struct
uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetTransferDirection().*/
uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_LL_EC_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetMode().*/
uint32_t DataWidth; /*!< Specifies the SPI data width.
This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetDataWidth().*/
uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_LL_EC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetClockPolarity().*/
uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_LL_EC_PHASE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetClockPhase().*/
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
+ or by software using the SSI bit.
This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetNSSMode().*/
- uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
+ to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+ @note The communication clock is derived from the master clock.
+ The slave clock does not need to be set.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetBaudRatePrescaler().*/
uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetTransferBitOrder().*/
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
- This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+ This feature can be modified afterwards using unitary
+ functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_SPI_SetCRCPolynomial().*/
} LL_SPI_InitTypeDef;
@@ -317,7 +330,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
@@ -347,7 +360,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
}
@@ -375,7 +388,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
* @arg @ref LL_SPI_PROTOCOL_TI
*/
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
}
@@ -404,7 +417,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
}
@@ -433,7 +446,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
}
@@ -473,7 +486,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
*/
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
}
@@ -501,7 +514,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
}
@@ -538,7 +551,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
}
@@ -565,7 +578,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
*/
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
}
@@ -609,7 +622,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
}
@@ -644,7 +657,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->CRCPR));
}
@@ -655,7 +668,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->RXCRCR));
}
@@ -666,7 +679,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->TXCRCR));
}
@@ -707,7 +720,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
*/
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
{
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
@@ -728,7 +741,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
}
@@ -739,7 +752,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
}
@@ -750,7 +763,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
}
@@ -761,7 +774,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
@@ -772,7 +785,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
@@ -790,7 +803,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
}
@@ -801,7 +814,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
}
@@ -874,7 +887,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
/**
* @brief Enable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @note This bit controls the generation of an interrupt when an error condition
+ * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
* @param SPIx SPI Instance
* @retval None
@@ -908,7 +922,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
/**
* @brief Disable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @note This bit controls the generation of an interrupt when an error condition
+ * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
* @param SPIx SPI Instance
* @retval None
@@ -946,7 +961,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
}
@@ -957,7 +972,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
}
@@ -968,7 +983,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
}
@@ -1009,7 +1024,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
}
@@ -1042,7 +1057,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
}
@@ -1053,7 +1068,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
{
return (uint32_t) &(SPIx->DR);
}
@@ -1130,7 +1145,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
* @{
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
@@ -1397,7 +1412,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
}
@@ -1430,7 +1445,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat
* @arg @ref LL_I2S_DATAFORMAT_24B
* @arg @ref LL_I2S_DATAFORMAT_32B
*/
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
}
@@ -1457,7 +1472,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
* @arg @ref LL_I2S_POLARITY_LOW
* @arg @ref LL_I2S_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
}
@@ -1492,7 +1507,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
* @arg @ref LL_I2S_STANDARD_PCM_LONG
*/
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
}
@@ -1523,7 +1538,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
* @arg @ref LL_I2S_MODE_MASTER_TX
* @arg @ref LL_I2S_MODE_MASTER_RX
*/
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
}
@@ -1546,7 +1561,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca
* @param SPIx SPI Instance
* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
}
@@ -1573,7 +1588,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
*/
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
}
@@ -1606,7 +1621,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
}
@@ -1625,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_RXNE(SPIx);
}
@@ -1636,7 +1651,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_TXE(SPIx);
}
@@ -1647,7 +1662,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_BSY(SPIx);
}
@@ -1658,7 +1673,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_OVR(SPIx);
}
@@ -1669,7 +1684,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
@@ -1680,7 +1695,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_FRE(SPIx);
}
@@ -1694,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
}
@@ -1816,7 +1831,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_ERR(SPIx);
}
@@ -1827,7 +1842,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_RXNE(SPIx);
}
@@ -1838,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_TXE(SPIx);
}
@@ -1879,7 +1894,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_RX(SPIx);
}
@@ -1912,7 +1927,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_TX(SPIx);
}
@@ -1957,7 +1972,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
* @{
*/
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_tim.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_tim.h
index 3608090af..7d3b66ace 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_tim.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_tim.h
@@ -562,10 +562,10 @@ typedef struct
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC);
}
+/**
+ * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+ * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usart.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usart.h
index 7da1de68f..1bbd4bcb6 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usart.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usart.h
@@ -345,7 +345,7 @@ typedef struct
* @}
*/
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper
* @{
*/
@@ -632,7 +632,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
@@ -649,7 +649,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
@@ -664,7 +664,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USA
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
@@ -680,7 +680,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
@@ -695,7 +695,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
@@ -711,7 +711,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
@@ -726,7 +726,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
@@ -754,7 +754,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
/**
* @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
@@ -767,7 +767,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
/**
* @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
@@ -780,7 +780,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
/**
* @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
@@ -882,7 +882,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
/**
* @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -895,7 +895,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -908,7 +908,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -921,7 +921,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -934,7 +934,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
@@ -953,7 +953,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
@@ -1077,7 +1077,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint3
/**
* @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
@@ -1090,7 +1090,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
/**
* @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
@@ -1103,7 +1103,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
/**
* @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
@@ -1116,7 +1116,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
@@ -1132,7 +1132,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
@@ -1148,7 +1148,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
@@ -1163,7 +1163,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
@@ -1184,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
/**
* @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
@@ -1197,7 +1197,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
/**
* @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
@@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
/**
* @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
@@ -1223,7 +1223,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *US
/**
* @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
@@ -1236,7 +1236,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
/**
* @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
@@ -1249,7 +1249,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
/**
* @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
@@ -1263,7 +1263,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
@@ -1278,7 +1278,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
@@ -1292,7 +1292,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USA
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
@@ -1307,7 +1307,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
@@ -1328,7 +1328,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USA
/**
* @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
@@ -1341,7 +1341,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
/**
* @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
@@ -1354,7 +1354,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
@@ -1375,7 +1375,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USART
/**
* @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -1391,7 +1391,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3
/**
* @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -1406,7 +1406,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USA
/**
* @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
@@ -1419,7 +1419,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
/**
* @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
@@ -1432,7 +1432,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
/**
* @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
@@ -1493,7 +1493,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1531,7 +1531,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
@@ -1571,7 +1571,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1610,7 +1610,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1652,7 +1652,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -1818,7 +1818,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll SR LBD LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
@@ -1831,7 +1831,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
@@ -1983,7 +1983,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
/**
* @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll SR LBD LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
@@ -1996,7 +1996,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
/**
* @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll SR CTS LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
@@ -2072,7 +2072,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
/**
* @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
@@ -2100,7 +2100,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
/**
* @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
@@ -2168,7 +2168,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
/**
* @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
@@ -2196,7 +2196,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
/**
* @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
@@ -2264,7 +2264,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
@@ -2288,7 +2288,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usb.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usb.h
index 553bd1c9b..905690603 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usb.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_usb.h
@@ -37,6 +37,13 @@ extern "C" {
*/
/* Exported types ------------------------------------------------------------*/
+#ifndef HAL_USB_TIMEOUT
+#define HAL_USB_TIMEOUT 0xF000000U
+#endif /* define HAL_USB_TIMEOUT */
+
+#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
+#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
+#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
/**
* @brief USB Mode definition
@@ -85,39 +92,39 @@ typedef enum
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
+ uint8_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t Host_channels; /*!< Host Channels number.
+ uint8_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t dma_enable; /*!< USB DMA state.
+ uint8_t dma_enable; /*!< USB DMA state.
If DMA is not supported this parameter shall be set by default to zero */
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Speed/HCD_Speed
- (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+ uint8_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+ uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
+ uint8_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
+ uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+ uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
- uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+ uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+ uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_CfgTypeDef;
@@ -495,41 +502,41 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup);
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
-uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
@@ -538,12 +545,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_utils.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_utils.h
index f4e01c689..f40a9a2f5 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_utils.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_utils.h
@@ -218,7 +218,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
+ * @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
diff --git a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_wwdg.h b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_wwdg.h
index 6c94d2ddd..f94171435 100644
--- a/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_wwdg.h
+++ b/stm32cube/stm32f2xx/drivers/include/stm32f2xx_ll_wwdg.h
@@ -131,7 +131,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
@@ -158,7 +158,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
@@ -191,7 +191,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
@@ -223,7 +223,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
@@ -244,7 +244,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
@@ -286,7 +286,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal.c
index e3939af9d..ffba97b6a 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal.c
@@ -54,7 +54,7 @@
*/
#define __STM32F2xx_HAL_VERSION_MAIN 0x01U /*!< [31:24] main version */
#define __STM32F2xx_HAL_VERSION_SUB1 0x02U /*!< [23:16] sub1 version */
-#define __STM32F2xx_HAL_VERSION_SUB2 0x08U /*!< [15:8] sub2 version */
+#define __STM32F2xx_HAL_VERSION_SUB2 0x09U /*!< [15:8] sub2 version */
#define __STM32F2xx_HAL_VERSION_RC 0x00U /*!< [7:0] release candidate */
#define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
@@ -381,7 +381,7 @@ HAL_TickFreqTypeDef HAL_GetTickFreq(void)
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
-__weak void HAL_Delay(__IO uint32_t Delay)
+__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_can.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_can.c
index c43c873fe..6d565b554 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_can.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_can.c
@@ -33,7 +33,7 @@
(++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
(++) Configure CAN pins
(+++) Enable the clock for the CAN GPIOs
- (+++) Configure CAN pins as alternate function open-drain
+ (+++) Configure CAN pins as alternate function
(++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
(+++) Configure the CAN interrupt priority using
HAL_NVIC_SetPriority()
@@ -235,6 +235,7 @@
* @{
*/
#define CAN_TIMEOUT_VALUE 10U
+#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
/**
* @}
*/
@@ -248,8 +249,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -328,7 +329,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@@ -482,7 +483,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -814,8 +815,8 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
*/
/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
- * @brief Configuration functions.
- *
+ * @brief Configuration functions.
+ *
@verbatim
==============================================================================
##### Configuration functions #####
@@ -868,7 +869,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
-#endif
+#endif /* CAN3 */
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
@@ -878,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
-#endif
+#endif /* CAN3 */
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
@@ -970,8 +971,8 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_Filter
*/
/** @defgroup CAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### Control functions #####
@@ -1143,7 +1144,6 @@ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
- uint32_t timeout = 1000000U;
HAL_CAN_StateTypeDef state = hcan->State;
if ((state == HAL_CAN_STATE_READY) ||
@@ -1159,15 +1159,14 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
count++;
/* Check if timeout is reached */
- if (count > timeout)
+ if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
return HAL_ERROR;
}
- }
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+ } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@@ -1608,8 +1607,8 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFi
*/
/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
- * @brief Interrupts management
- *
+ * @brief Interrupts management
+ *
@verbatim
==============================================================================
##### Interrupts management #####
@@ -2074,8 +2073,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group5 Callback functions
- * @brief CAN Callback functions
- *
+ * @brief CAN Callback functions
+ *
@verbatim
==============================================================================
##### Callback functions #####
@@ -2324,8 +2323,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
+ * @brief CAN Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_cortex.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_cortex.c
index 0429b1204..9d04e38bd 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_cortex.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_cortex.c
@@ -8,17 +8,6 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -77,6 +66,16 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -291,6 +290,38 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
__ISB();
}
+/**
+ * @brief Enable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
@@ -302,38 +333,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac.c
index a27cc292e..657a19825 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac.c
@@ -938,10 +938,7 @@ uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
uint32_t result;
/* Check the DAC peripheral handle */
- if (hdac == NULL)
- {
- return HAL_ERROR;
- }
+ assert_param(hdac != NULL);
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac_ex.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac_ex.c
index bc2c874af..95c73a7c8 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac_ex.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dac_ex.c
@@ -387,7 +387,6 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
}
-
/**
* @}
*/
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi.c
index 98c70f442..bdaf01a71 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -26,7 +37,7 @@
Synchronization Mode, code of the frame delimiter and data width
using HAL_DCMI_Init() function.
- (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
+ (#) Configure the selected DMA stream to transfer Data from DCMI DR
register to the destination memory buffer.
(#) Program the required configuration through following parameters:
@@ -35,7 +46,7 @@
(#) Optionally, configure and Enable the CROP feature to select a rectangular
window from the received image using HAL_DCMI_ConfigCrop()
- and HAL_DCMI_EnableCROP() functions
+ and HAL_DCMI_EnableCrop() functions
(#) The capture can be stopped using HAL_DCMI_Stop() function.
@@ -65,33 +76,33 @@
Use functions HAL_DCMI_RegisterCallback() to register a user callback.
Function HAL_DCMI_RegisterCallback() allows to register following callbacks:
- (+) FrameEventCallback : DCMI Frame Event.
- (+) VsyncEventCallback : DCMI Vsync Event.
- (+) LineEventCallback : DCMI Line Event.
- (+) ErrorCallback : DCMI error.
- (+) MspInitCallback : DCMI MspInit.
- (+) MspDeInitCallback : DCMI MspDeInit.
- This function takes as parameters the HAL peripheral handle, the callback ID
+ (+) FrameEventCallback : callback for DCMI Frame Event.
+ (+) VsyncEventCallback : callback for DCMI Vsync Event.
+ (+) LineEventCallback : callback for DCMI Line Event.
+ (+) ErrorCallback : callback for DCMI error detection.
+ (+) MspInitCallback : callback for DCMI MspInit.
+ (+) MspDeInitCallback : callback for DCMI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak (overridden) function.
HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
This function allows to reset following callbacks:
- (+) FrameEventCallback : DCMI Frame Event.
- (+) VsyncEventCallback : DCMI Vsync Event.
- (+) LineEventCallback : DCMI Line Event.
- (+) ErrorCallback : DCMI error.
- (+) MspInitCallback : DCMI MspInit.
- (+) MspDeInitCallback : DCMI MspDeInit.
+ (+) FrameEventCallback : callback for DCMI Frame Event.
+ (+) VsyncEventCallback : callback for DCMI Vsync Event.
+ (+) LineEventCallback : callback for DCMI Line Event.
+ (+) ErrorCallback : callback for DCMI error.
+ (+) MspInitCallback : callback for DCMI MspInit.
+ (+) MspDeInitCallback : callback for DCMI MspDeInit.
By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ all callbacks are reset to the corresponding legacy weak (overridden) functions:
examples FrameEventCallback(), HAL_DCMI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init
- and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
+ reset to the legacy weak (overridden) functions in the HAL_DCMI_Init
+ and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -105,24 +116,16 @@
When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_hal.h"
+#ifdef HAL_DCMI_MODULE_ENABLED
+#if defined (DCMI)
/** @addtogroup STM32F2xx_HAL_Driver
* @{
@@ -132,19 +135,35 @@
* @{
*/
-#ifdef HAL_DCMI_MODULE_ENABLED
-#if defined (DCMI)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+ * @{
+ */
+
+/** @defgroup DCMI_Stop_TimeOut DCMI Stop Time Out
+ * @{
+ */
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+ * @{
+ */
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
@@ -152,8 +171,8 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
*/
/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -195,6 +214,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Init the DCMI Callback settings */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
@@ -317,8 +337,8 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
* @}
*/
/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -344,8 +364,9 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
+ uint32_t tmp_length = Length;
/* Initialize the second memory address */
- uint32_t SecondMemAddress = 0;
+ uint32_t SecondMemAddress;
/* Check function parameters */
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
@@ -378,11 +399,18 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mo
hdcmi->XferSize = 0;
hdcmi->pBuffPtr = 0;
- if (Length <= 0xFFFFU)
+ if (tmp_length <= 0xFFFFU)
{
/* Enable the DMA Stream */
- if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, tmp_length) != HAL_OK)
{
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
return HAL_ERROR;
}
}
@@ -393,7 +421,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mo
/* Initialize transfer parameters */
hdcmi->XferCount = 1;
- hdcmi->XferSize = Length;
+ hdcmi->XferSize = tmp_length;
hdcmi->pBuffPtr = pData;
/* Get the number of buffer */
@@ -408,11 +436,18 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mo
hdcmi->XferTransferNumber = hdcmi->XferCount;
/* Update second memory address */
- SecondMemAddress = (uint32_t)(pData + (4 * hdcmi->XferSize));
+ SecondMemAddress = (uint32_t)(pData + (4U * hdcmi->XferSize));
/* Start DMA multi buffer transfer */
if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK)
{
+ /* Set Error Code */
+ hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+ /* Change DCMI state */
+ hdcmi->State = HAL_DCMI_STATE_READY;
+ /* Release Lock */
+ __HAL_UNLOCK(hdcmi);
+ /* Return function status */
return HAL_ERROR;
}
}
@@ -435,7 +470,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mo
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+ uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
@@ -450,7 +485,8 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
- if (count-- == 0U)
+ count-- ;
+ if (count == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
@@ -458,8 +494,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
status = HAL_TIMEOUT;
break;
}
- }
- while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+ } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
@@ -488,7 +523,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
{
- register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+ uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
@@ -505,7 +540,8 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
/* Check if the DCMI capture effectively disabled */
do
{
- if (count-- == 0U)
+ count-- ;
+ if (count == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
@@ -516,8 +552,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
status = HAL_TIMEOUT;
break;
}
- }
- while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+ } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
@@ -542,7 +577,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
- /* Disable Capture */
+ /* Enable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
}
/* Process Unlocked */
@@ -578,7 +613,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
- (void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
+ if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
+ {
+ DCMI_DMAError(hdcmi->DMA_Handle);
+ }
}
/* Overflow interrupt management ********************************************/
if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
@@ -679,6 +717,8 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
*/
__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_LineEventCallback could be implemented in the user file
*/
@@ -721,8 +761,8 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
*/
/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -746,7 +786,8 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
* @param Y0 DCMI window Y offset
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
+ uint32_t YSize)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
@@ -833,7 +874,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
* the embedded synchronization delimiters unmasks.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
@@ -861,8 +902,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn
*/
/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -882,32 +923,40 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn
* the configuration information for DCMI.
* @retval HAL state
*/
-HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->State;
}
/**
-* @brief Return the DCMI error code
-* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * @brief Return the DCMI error code
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
-* @retval DCMI Error Code
-*/
-uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
+ * @retval DCMI Error Code
+ */
+uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->ErrorCode;
}
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/**
- * @brief DCMI Callback registering
- * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
- * the configuration information for DCMI.
- * @param CallbackID dcmi Callback ID
- * @param pCallback pointer to DCMI_CallbackTypeDef structure
- * @retval status
+ * @brief Register a User DCMI Callback
+ * To be used instead of the weak predefined callback
+ * @param hdcmi DCMI handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
+ * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
+ * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
+ * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
+ pDCMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -987,10 +1036,18 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_
}
/**
- * @brief DCMI Callback Unregistering
- * @param hdcmi dcmi handle
- * @param CallbackID dcmi Callback ID
- * @retval status
+ * @brief Unregister a DCMI Callback
+ * DCMI callback is redirected to the weak predefined callback
+ * @param hdcmi DCMI handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
+ * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
+ * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
+ * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
{
@@ -1005,15 +1062,15 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
- hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
- hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
break;
case HAL_DCMI_ERROR_CB_ID :
- hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_DCMI_MSPINIT_CB_ID :
@@ -1067,52 +1124,65 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
/**
* @}
*/
+
+/**
+ * @}
+ */
+
/* Private functions ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
/**
-* @brief DMA conversion complete callback.
-* @param hdma pointer to a DMA_HandleTypeDef structure that contains
-* the configuration information for the specified DMA module.
-* @retval None
-*/
+ * @brief DMA conversion complete callback.
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
- uint32_t tmp = 0;
+ uint32_t tmp ;
DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- if (hdcmi->XferCount != 0)
+ if (hdcmi->XferCount != 0U)
{
/* Update memory 0 address location */
- tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
- if (((hdcmi->XferCount % 2) == 0) && (tmp != 0))
+ tmp = ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR) & DMA_SxCR_CT);
+ if (((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U))
{
- tmp = hdcmi->DMA_Handle->Instance->M0AR;
- HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY0);
+ tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR;
+ (void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY0);
hdcmi->XferCount--;
}
/* Update memory 1 address location */
- else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+ else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
{
- tmp = hdcmi->DMA_Handle->Instance->M1AR;
- HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY1);
+ tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR;
+ (void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY1);
hdcmi->XferCount--;
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/* Update memory 0 address location */
- else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
+ else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0U)
{
- hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
+ ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR = hdcmi->pBuffPtr;
}
/* Update memory 1 address location */
- else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+ else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U)
{
tmp = hdcmi->pBuffPtr;
- hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4 * hdcmi->XferSize));
+ ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4U * hdcmi->XferSize));
hdcmi->XferCount = hdcmi->XferTransferNumber;
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check if the frame is transferred */
if (hdcmi->XferCount == hdcmi->XferTransferNumber)
@@ -1157,10 +1227,6 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
}
-/**
- * @}
- */
-
/**
* @}
*/
@@ -1173,5 +1239,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi_ex.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi_ex.c
index aa737d293..77009818a 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi_ex.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_dcmi_ex.c
@@ -30,4 +30,3 @@
/* Exported functions --------------------------------------------------------*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash.c
index 81fa0638f..5aa3fd1dc 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash.c
@@ -216,9 +216,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
@@ -363,8 +360,6 @@ void HAL_FLASH_IRQHandler(void)
/* Disable Error source interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
}
}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash_ex.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash_ex.c
index be7aecc33..4d60fecc1 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash_ex.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_flash_ex.c
@@ -205,9 +205,6 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hash.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hash.c
index 6a72b3d2f..8919c4476 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hash.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hash.c
@@ -119,7 +119,7 @@
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
- This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ This is why, for driver implementation simplicity s sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@@ -268,10 +268,10 @@
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASH_DMAError(DMA_HandleTypeDef *hdma);
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size);
static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
uint32_t Timeout);
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
@@ -751,7 +751,8 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
@@ -777,7 +778,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -792,7 +793,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
@@ -809,7 +810,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
@@ -835,7 +837,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -850,7 +852,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
@@ -898,7 +900,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
@@ -922,7 +924,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -936,7 +938,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
@@ -952,7 +954,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
@@ -977,7 +979,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -991,7 +993,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
@@ -1060,7 +1062,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -1090,7 +1092,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -1147,7 +1149,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
@@ -1166,7 +1169,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
@@ -1208,7 +1212,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
@@ -1226,7 +1230,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
@@ -1237,7 +1241,6 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
*/
-
/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
* @brief HMAC processing functions using DMA modes.
*
@@ -1274,7 +1277,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
@@ -1293,7 +1296,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
@@ -1340,7 +1343,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
* @param hhash HASH handle.
* @retval HAL HASH state
*/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash)
{
return hhash->State;
}
@@ -1353,7 +1356,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
* @param hhash HASH handle.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
+HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash)
{
return hhash->Status;
}
@@ -1591,7 +1594,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
* @param hhash pointer to a HASH_HandleTypeDef structure.
* @retval HASH Error Code
*/
-uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
+uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash)
{
/* Return HASH Error Code */
return hhash->ErrorCode;
@@ -1785,12 +1788,13 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma)
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
{
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t tmp;
- for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
+ for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++)
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
@@ -1798,8 +1802,16 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size))
{
+ /* wait for flag BUSY not set before Wait for DINIS = 1*/
+ if ((buffercounter * 4U) >= 64U)
+ {
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
/* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
in the input buffer */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
@@ -1814,14 +1826,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashInCount = Size - (buffercounter + 4U);
+ hhash->HashInCount = Size - ((buffercounter * 4U) + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashKeyCount = Size - (buffercounter + 4U);
+ hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U);
}
else
{
@@ -1840,6 +1852,51 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
/* At this point, all the data have been entered to the Peripheral: exit */
+
+ if ((Size % 4U) != 0U)
+ {
+ if (hhash->Init.DataType == HASH_DATATYPE_16B)
+ {
+ /* Write remaining input data */
+
+ if ((Size % 4U) <= 2U)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if ((Size % 4U) == 3U)
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+
+ }
+ else if ((hhash->Init.DataType == HASH_DATATYPE_8B)
+ || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */
+ {
+ /* Write remaining input data */
+ if ((Size % 4U) == 1U)
+ {
+ HASH->DIN = (uint32_t) * (uint8_t *)inputaddr;
+ }
+ if ((Size % 4U) == 2U)
+ {
+ HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+ }
+ if ((Size % 4U) == 3U)
+ {
+ tmp = *(uint8_t *)inputaddr;
+ tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U;
+ tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U;
+ HASH->DIN = tmp;
+ }
+
+ }
+ else
+ {
+ HASH->DIN = *(uint32_t *)inputaddr;
+ }
+ }
+
+
return HAL_OK;
}
@@ -1849,7 +1906,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
* @param Size message digest size in bytes.
* @retval None
*/
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size)
{
uint32_t msgdigest = (uint32_t)pMsgDigest;
@@ -1882,7 +1939,6 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
}
-
/**
* @brief Handle HASH processing Timeout.
* @param hhash HASH handle.
@@ -2368,10 +2424,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm)
{
- uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -2403,7 +2460,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
- pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Set the phase */
@@ -2419,7 +2476,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
/* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
to the API input parameters but to those saved beforehand by HASH_WriteData()
when the processing was suspended */
- pInBuffer_tmp = hhash->pHashInBuffPtr;
+ pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr;
Size_tmp = hhash->HashInCount;
}
/* ... or multi-buffer HASH processing end */
@@ -2427,7 +2484,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
{
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
- pInBuffer_tmp = pInBuffer;
+ pInBuffer_tmp = (const uint8_t *)pInBuffer;
Size_tmp = Size;
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
@@ -2505,9 +2562,10 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm)
{
- uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -2539,7 +2597,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
to the API input parameters but to those saved beforehand by HASH_WriteData()
when the processing was suspended */
- pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
+ pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */
}
@@ -2550,7 +2608,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
- pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Check if initialization phase has already be performed */
@@ -2608,7 +2666,8 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
@@ -2718,7 +2777,6 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
}
-
/**
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest in interruption mode.
@@ -2730,7 +2788,8 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -2779,6 +2838,19 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
+ else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U))
+ {
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ /* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual.
+ Update HashInCount and pHashInBuffPtr accordingly. */
+ hhash->HashInCount = SizeVar;
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ /* Update the configuration of the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ }
+ }
else
{
initialization_skipped = 1; /* info user later on in case of multi-buffer */
@@ -2882,7 +2954,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm)
{
uint32_t inputaddr;
uint32_t inputSize;
@@ -3054,7 +3127,8 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -3118,7 +3192,6 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
}
-
/**
* @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
* read the computed digest in interruption mode.
@@ -3132,7 +3205,8 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer,
uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
@@ -3227,7 +3301,6 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
}
-
/**
* @brief Initialize the HASH peripheral in HMAC mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
@@ -3243,7 +3316,8 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+ uint32_t Algorithm)
{
uint32_t inputaddr;
uint32_t inputSize;
@@ -3362,7 +3436,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
/* Enable the DMA In DMA stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
- : (inputSize / 4U)));
+ : (inputSize / 4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hcd.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hcd.c
index 47603637a..8df2d18af 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hcd.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_hcd.c
@@ -109,7 +109,9 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx;
+#if defined (USB_OTG_FS)
+ const USB_OTG_GlobalTypeDef *USBx;
+#endif /* defined (USB_OTG_FS) */
/* Check the HCD handle allocation */
if (hhcd == NULL)
@@ -120,7 +122,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+#if defined (USB_OTG_FS)
USBx = hhcd->Instance;
+#endif /* defined (USB_OTG_FS) */
if (hhcd->State == HAL_HCD_STATE_RESET)
{
@@ -150,23 +154,37 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
hhcd->State = HAL_HCD_STATE_BUSY;
+#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
- if ((USBx->CID & (0x1U << 8)) == 0U)
+ if (USBx == USB_OTG_FS)
{
hhcd->Init.dma_enable = 0U;
}
+#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
- (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+ if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
- /* Force Host Mode*/
- (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+ /* Force Host Mode */
+ if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init Host */
- (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+ if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
hhcd->State = HAL_HCD_STATE_READY;
@@ -1261,7 +1279,7 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1580,7 +1598,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
uint32_t num_packets;
@@ -1815,7 +1833,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
@@ -1881,7 +1899,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2c.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2c.c
index 48eef2f09..af0030752 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2c.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2c.c
@@ -89,7 +89,7 @@
add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
@@ -139,7 +139,7 @@
or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
@@ -193,7 +193,7 @@
add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
@@ -2831,6 +2831,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
+ if (hi2c->XferSize == 3U)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
@@ -4708,7 +4713,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -4724,7 +4729,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
UNUSED(DevAddress);
/* Abort Master transfer during Receive or Transmit process */
- if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) ||
+ (CurrentMode == HAL_I2C_MODE_MEM)))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -5516,7 +5522,9 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
uint32_t tmp;
+ uint32_t CurrentXferOptions;
+ CurrentXferOptions = hi2c->XferOptions;
tmp = hi2c->XferCount;
if (tmp > 3U)
{
@@ -5572,7 +5580,14 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
@@ -5675,15 +5690,11 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
/* Enable Acknowledge */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
- else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
+ else
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
- else
- {
- /* Do nothing */
- }
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
@@ -5720,7 +5731,14 @@ static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
#else
@@ -7028,7 +7046,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2s.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2s.c
index 3f891a67b..af307e4b6 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2s.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_i2s.c
@@ -796,15 +796,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -915,15 +914,14 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1013,15 +1011,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1040,6 +1037,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
hi2s->TxXferCount = Size;
}
+ __HAL_UNLOCK(hi2s);
+
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -1050,7 +1049,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
__HAL_I2S_ENABLE(hi2s);
}
- __HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1079,15 +1077,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1106,6 +1103,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
hi2s->RxXferCount = Size;
}
+ __HAL_UNLOCK(hi2s);
+
/* Enable RXNE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -1116,7 +1115,6 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
__HAL_I2S_ENABLE(hi2s);
}
- __HAL_UNLOCK(hi2s);
return HAL_OK;
}
@@ -1143,15 +1141,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1193,12 +1190,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ __HAL_UNLOCK(hi2s);
/* Check if the I2S Tx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
@@ -1207,7 +1199,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- __HAL_UNLOCK(hi2s);
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
return HAL_OK;
}
@@ -1234,15 +1232,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1290,12 +1287,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
return HAL_ERROR;
}
- /* Check if the I2S is already enabled */
- if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ __HAL_UNLOCK(hi2s);
/* Check if the I2S Rx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
@@ -1304,7 +1296,13 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
- __HAL_UNLOCK(hi2s);
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
return HAL_OK;
}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_iwdg.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_iwdg.c
index 89d06006e..d9878d03f 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_iwdg.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_iwdg.c
@@ -91,7 +91,6 @@
the reload register
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -121,7 +120,8 @@
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
+ ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_mmc.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_mmc.c
index 9dcc03614..3cb2b1f2c 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_mmc.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_mmc.c
@@ -2328,7 +2328,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_nand.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_nand.c
index 0976a7a6f..2bf27d23a 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_nand.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_nand.c
@@ -506,7 +506,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig)
{
hnand->Config.PageSize = pDeviceConfig->PageSize;
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
@@ -2036,6 +2036,7 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
status = HAL_ERROR;
}
+ return status;
}
/**
@@ -2094,6 +2095,7 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
status = HAL_ERROR;
}
+ return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pccard.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pccard.c
index 2361d7e5e..fd998d9f9 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pccard.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pccard.c
@@ -162,7 +162,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
- FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+ FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
+ FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
{
/* Check the PCCARD controller state */
if (hpccard == NULL)
@@ -186,7 +187,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_T
#else
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
}
/* Initialize the PCCARD state */
@@ -233,7 +234,7 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
#else
/* De-Initialize the low level hardware (MSP) */
HAL_PCCARD_MspDeInit(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Configure the PCCARD registers with their reset values */
FSMC_PCCARD_DeInit(hpccard->Instance);
@@ -306,8 +307,9 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
- uint8_t status = 0;
+ uint32_t timeout = 0U;
+ uint32_t index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -318,6 +320,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
return HAL_BUSY;
}
+ /* Initialize timeout value */
+ timeout = PCCARD_TIMEOUT_READ_ID;
+
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
@@ -370,8 +375,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
- uint8_t status = 0;
+ uint32_t timeout = 0U;
+ uint32_t index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -382,6 +388,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
return HAL_BUSY;
}
+ /* Initialize timeout value */
+ timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
+
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
@@ -447,8 +456,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
- uint8_t status = 0;
+ uint32_t timeout = 0U;
+ uint32_t index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -459,6 +469,9 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
return HAL_BUSY;
}
+ /* Initialize timeout value */
+ timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
+
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
@@ -521,7 +534,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
- uint8_t status = 0;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -623,7 +636,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Rising edge pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
@@ -637,7 +650,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Level pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
@@ -651,7 +664,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Falling edge pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
@@ -665,7 +678,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt FIFO empty pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
@@ -822,7 +835,7 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, H
__HAL_UNLOCK(hpccard);
return status;
}
-#endif
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
@@ -865,7 +878,8 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U;
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS;
+ uint32_t status_pccard = 0U;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
@@ -901,7 +915,8 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint8_t data = 0U, status_pccard = PCCARD_BUSY;
+ uint8_t data = 0U;
+ uint8_t status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pcd.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pcd.c
index 9946ab054..ae9999a87 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pcd.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_pcd.c
@@ -122,7 +122,9 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
- USB_OTG_GlobalTypeDef *USBx;
+#if defined (USB_OTG_FS)
+ const USB_OTG_GlobalTypeDef *USBx;
+#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
@@ -134,7 +136,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+#if defined (USB_OTG_FS)
USBx = hpcd->Instance;
+#endif /* defined (USB_OTG_FS) */
if (hpcd->State == HAL_PCD_STATE_RESET)
{
@@ -169,11 +173,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
+#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
- if ((USBx->CID & (0x1U << 8)) == 0U)
+ if (USBx == USB_OTG_FS)
{
hpcd->Init.dma_enable = 0U;
}
+#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -185,8 +191,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
return HAL_ERROR;
}
- /* Force Device Mode*/
- (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+ /* Force Device Mode */
+ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
@@ -1300,16 +1310,17 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
{
+#if defined (USB_OTG_FS)
USB_OTG_GlobalTypeDef *USBx;
-
USBx = hpcd->Instance;
- if ((USBx->CID & (0x1U << 8)) == 0U)
+ if (USBx == USB_OTG_FS)
{
/* Clear EXTI pending Bit */
__HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG();
}
else
+#endif /* defined (USB_OTG_FS) */
{
/* Clear EXTI pending Bit */
__HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG();
@@ -1886,9 +1897,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
* @param testmode USB Device high speed test mode
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
switch (testmode)
@@ -1990,9 +2001,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_EPTypeDef *ep;
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
@@ -2101,9 +2112,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rng.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rng.c
index a49894b3f..acaf0e9e2 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rng.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rng.c
@@ -689,15 +689,16 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
uint32_t rngclockerror = 0U;
+ uint32_t itflag = hrng->Instance->SR;
/* RNG clock error interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+ if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
- else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
@@ -728,7 +729,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
}
/* Check RNG data ready interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc.c
index 30fe52ca4..71cae3520 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc.c
@@ -6,8 +6,8 @@
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization and de-initialization functions
- * + RTC Calendar (Time and Date) configuration functions
- * + RTC Alarms (Alarm A and Alarm B) configuration functions
+ * + Calendar (Time and Date) configuration functions
+ * + Alarms (Alarm A and Alarm B) configuration functions
* + Peripheral Control functions
* + Peripheral State functions
*
@@ -121,6 +121,12 @@
*** Callback registration ***
=============================================
[..]
+ When the compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all
+ callbacks are set to the corresponding weak functions.
+ This is the recommended configuration in order to optimize memory/code
+ consumption footprint/performances.
+ [..]
The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
@@ -152,25 +158,21 @@
[..]
By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions:
- examples AlarmAEventCallback(), WakeUpTimerEventCallback().
+ examples AlarmAEventCallback(), TimeStampEventCallback().
Exception done for MspInit() and MspDeInit() callbacks that are reset to the
- legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only
- when these callbacks are null (not registered beforehand).
+ legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these
+ callbacks are null (not registered beforehand).
If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
- Exception done MspInit()/MspDeInit() that can be registered/unregistered
+ Exception done for MspInit() and MspDeInit() that can be registered/unregistered
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state.
Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the
Init/DeInit.
- In that case first register the MspInit()/MspDeInit() user callbacks
- using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
- or HAL_RTC_Init() functions.
- [..]
- When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all
- callbacks are set to the corresponding weak functions.
+ In that case first register the MspInit()/MspDeInit() user callbacks using
+ HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() or HAL_RTC_Init()
+ functions.
@endverbatim
******************************************************************************
@@ -426,9 +428,9 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
- * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
- * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
- * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -523,9 +525,9 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
- * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
- * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
- * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
@@ -1006,7 +1008,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
@@ -1039,7 +1041,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
((uint32_t) sAlarm->AlarmMask));
@@ -1048,16 +1050,15 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Alarm register */
if (sAlarm->Alarm == RTC_ALARM_A)
{
- /* Disable the Alarm A */
+ /* Disable Alarm A */
__HAL_RTC_ALARMA_DISABLE(hrtc);
/* In case interrupt mode is used, the interrupt source must be disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
- /* Clear the Alarm flag */
+ /* Clear Alarm A flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Get tick */
@@ -1080,19 +1081,20 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
}
+ /* Configure Alarm A register */
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm A */
__HAL_RTC_ALARMA_ENABLE(hrtc);
}
else
{
- /* Disable the Alarm B */
+ /* Disable Alarm B */
__HAL_RTC_ALARMB_DISABLE(hrtc);
/* In case interrupt mode is used, the interrupt source must be disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
- /* Clear the Alarm flag */
+ /* Clear Alarm B flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Get tick */
@@ -1115,8 +1117,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
}
}
+ /* Configure Alarm B register */
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm B */
__HAL_RTC_ALARMB_ENABLE(hrtc);
}
@@ -1192,7 +1195,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
@@ -1225,7 +1228,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
((uint32_t) sAlarm->AlarmMask));
@@ -1234,13 +1237,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Alarm register */
if (sAlarm->Alarm == RTC_ALARM_A)
{
- /* Disable the Alarm A */
+ /* Disable Alarm A */
__HAL_RTC_ALARMA_DISABLE(hrtc);
- /* Clear the Alarm flag */
+ /* Clear Alarm A flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
/* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
@@ -1261,18 +1263,19 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
} while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U);
+ /* Configure Alarm A register */
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm A */
__HAL_RTC_ALARMA_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
+ /* Enable Alarm A interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
}
else
{
- /* Disable the Alarm B */
+ /* Disable Alarm B */
__HAL_RTC_ALARMB_DISABLE(hrtc);
- /* Clear the Alarm flag */
+ /* Clear Alarm B flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Reload the counter */
@@ -1296,14 +1299,15 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
}
} while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U);
+ /* Configure Alarm B register */
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm state: Enable Alarm */
+ /* Enable Alarm B */
__HAL_RTC_ALARMB_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
+ /* Enable Alarm B interrupt */
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
}
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Alarm interrupt */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
@@ -1355,7 +1359,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+ /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -1383,7 +1387,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+ /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -1476,7 +1480,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Clear the EXTI's line Flag for RTC Alarm */
+ /* Clear the EXTI flag associated to the RTC Alarm interrupt */
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Get the Alarm A interrupt source enable status */
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc_ex.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc_ex.c
index bacc521da..bcfa52e14 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc_ex.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_rtc_ex.c
@@ -58,7 +58,7 @@
*** Tamper configuration ***
============================
[..]
- (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger
+ (+) To enable the RTC Tamper and configure the Tamper filter count, trigger
Edge or Level according to the Tamper filter value (if equal to 0 Edge
else Level), sampling frequency, precharge or discharge and Pull-UP use
the HAL_RTCEx_SetTamper() function.
@@ -96,8 +96,8 @@
0 to 62.
(+) In order to measure the clock deviation, a 512 Hz clock is output for
calibration.
- (+) The RTC Coarse Digital Calibration value and sign can be calibrated using
- the HAL_RTCEx_SetCoarseCalib() function.
+ (+) To configure the RTC Coarse Digital Calibration value and sign use the
+ HAL_RTCEx_SetCoarseCalib() function.
@endverbatim
******************************************************************************
@@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RT
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* RTC Timestamp Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -303,7 +303,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* In case of interrupt mode is used, the interrupt source must disabled */
+ /* In case interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
/* Get the RTC_CR register and clear the bits to be configured */
@@ -493,7 +493,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/* Copy desired configuration into configuration register */
hrtc->Instance->TAFCR = tmpreg;
- /* RTC Tamper Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -543,7 +543,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Clear the EXTI's Flag for RTC Timestamp and Tamper */
+ /* Clear the EXTI flag associated to the RTC Timestamp and Tamper interrupts */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Get the Timestamp interrupt source enable status */
@@ -894,7 +894,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* RTC wakeup timer Interrupt Configuration: EXTI configuration */
+ /* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
@@ -936,7 +936,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/* Disable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
- /* In case of interrupt mode is used, the interrupt source must disabled */
+ /* In case interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
/* Get tick */
@@ -995,7 +995,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ /* Clear the EXTI flag associated to the RTC Wakeup Timer interrupt */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
/* Get the pending status of the Wakeup timer Interrupt */
@@ -1111,7 +1111,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
- tmp = (uint32_t) & (hrtc->Instance->BKP0R);
+ tmp = (uint32_t) &(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
/* Write the specified register */
@@ -1134,7 +1134,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
- tmp = (uint32_t) & (hrtc->Instance->BKP0R);
+ tmp = (uint32_t) &(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
/* Read the specified register */
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sd.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sd.c
index 30dddb5eb..dc21c76c7 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sd.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sd.c
@@ -403,7 +403,6 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
- HAL_StatusTypeDef status;
SD_InitTypeDef Init;
/* Default SDIO peripheral configuration for SD card initialization */
@@ -415,11 +414,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
Init.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO peripheral interface with default configuration */
- status = SDIO_Init(hsd->Instance, Init);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ SDIO_Init(hsd->Instance, Init);
/* Disable SDIO Clock */
__HAL_SD_DISABLE(hsd);
@@ -692,7 +687,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@@ -903,7 +898,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
@@ -2868,13 +2863,13 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
}
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
}
@@ -2896,7 +2891,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
*pData = SDIO_ReadFIFO(hsd->Instance);
pData++;
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3088,13 +3083,13 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
break;
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_spi.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_spi.c
index de0b4a998..c82cd4fff 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_spi.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_spi.c
@@ -44,7 +44,8 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+ or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -190,7 +191,8 @@
@note The max SPI frequency depend on SPI data size (8bits, 16bits),
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
@note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and
+ HAL_SPI_TransmitReceive_DMA()
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
@@ -765,38 +767,35 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
uint16_t initial_TxXferCount;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
initial_TxXferCount = Size;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -835,7 +834,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -845,7 +844,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
@@ -854,9 +853,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -866,7 +865,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
@@ -875,7 +874,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
@@ -884,9 +883,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -911,19 +910,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -941,12 +939,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
@@ -956,18 +952,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1026,9 +1021,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1050,9 +1045,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1069,8 +1064,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Receive last data in 16 Bit mode */
@@ -1088,8 +1083,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC to Flush DR and RXNE flag */
@@ -1114,18 +1110,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
}
#endif /* USE_SPI_CRC */
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1138,8 +1133,8 @@ error :
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
{
uint16_t initial_TxXferCount;
uint32_t tmp_mode;
@@ -1151,14 +1146,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -1168,18 +1159,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
initial_TxXferCount = Size;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1191,7 +1184,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
@@ -1219,16 +1212,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1254,9 +1256,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1265,16 +1267,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1300,9 +1310,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
- errorcode = HAL_TIMEOUT;
hspi->State = HAL_SPI_STATE_READY;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
}
}
@@ -1316,8 +1326,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return HAL_TIMEOUT;
}
/* Read CRC */
tmpreg = READ_REG(hspi->Instance->DR);
@@ -1331,17 +1342,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- errorcode = HAL_ERROR;
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- goto error;
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
@@ -1350,18 +1361,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- errorcode = HAL_ERROR;
+ return HAL_ERROR;
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
}
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
}
/**
@@ -1372,32 +1384,30 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1433,10 +1443,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
-
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
@@ -1444,9 +1450,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
-error :
+ /* Process Unlocked */
__HAL_UNLOCK(hspi);
- return errorcode;
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ return HAL_OK;
}
/**
@@ -1459,13 +1468,10 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -1475,15 +1481,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1523,9 +1529,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
#endif /* USE_SPI_CRC */
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
/* Note : The SPI must be enabled after unlocking current process
to avoid the risk of SPI interrupt handle execution before current
process unlock */
@@ -1537,10 +1540,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
- return errorcode;
+ /* Enable RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ return HAL_OK;
}
/**
@@ -1552,35 +1557,34 @@ error :
* @param Size amount of data to be sent and received
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1589,7 +1593,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -1616,8 +1620,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
}
#endif /* USE_SPI_CRC */
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1626,10 +1628,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
__HAL_SPI_ENABLE(hspi);
}
-error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
- return errorcode;
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ return HAL_OK;
}
/**
@@ -1640,9 +1644,8 @@ error :
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
@@ -1650,25 +1653,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- /* Process Locked */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->pTxBuffPtr = (const uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
@@ -1713,9 +1714,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -1725,16 +1726,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1749,15 +1750,12 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
@@ -1771,15 +1769,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
if ((pData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1827,9 +1824,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -1839,16 +1836,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
__HAL_SPI_ENABLE(hspi);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1861,12 +1858,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check rx & tx dma handles */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
@@ -1875,26 +1871,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
- __HAL_LOCK(hspi);
-
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) ||
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) &&
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
- errorcode = HAL_BUSY;
- goto error;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- errorcode = HAL_ERROR;
- goto error;
+ return HAL_ERROR;
}
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
@@ -1903,7 +1898,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->pTxBuffPtr = (const uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
hspi->pRxBuffPtr = (uint8_t *)pRxData;
@@ -1948,9 +1943,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Enable Rx DMA Request */
@@ -1969,9 +1964,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
-
- goto error;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return HAL_ERROR;
}
/* Check if the SPI is already enabled */
@@ -1980,16 +1975,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -2355,9 +2351,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or
+ HAL_SPI_TxRxCpltCallback()
*/
/* Abort the SPI DMA tx Stream/Channel */
@@ -2647,7 +2645,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI state
*/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
{
/* Return SPI handle state */
return hspi->State;
@@ -2659,7 +2657,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
{
/* Return SPI ErrorCode */
return hspi->ErrorCode;
@@ -2686,7 +2684,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
/* Init tickstart for timeout management*/
@@ -2743,7 +2741,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -2832,7 +2830,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
@@ -2912,7 +2910,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Tx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -2930,7 +2928,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user Rx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -2948,7 +2946,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Call user TxRx half complete callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
@@ -2966,7 +2964,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
@@ -2989,7 +2987,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
@@ -3011,7 +3009,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
__IO uint32_t count;
hspi->hdmatx->XferAbortCallback = NULL;
@@ -3076,7 +3074,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -3198,7 +3196,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -3291,7 +3289,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -3439,7 +3437,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr++;
hspi->TxXferCount--;
@@ -3465,7 +3463,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
@@ -3586,6 +3584,13 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
+ /* Wait until TXE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sram.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sram.c
index 2d907eb3e..04738f3b9 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sram.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_sram.c
@@ -208,7 +208,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy
/* Initialize SRAM extended mode timing Interface */
(void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
- hsram->Init.ExtendedMode);
+ hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
@@ -1037,6 +1037,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1059,6 +1060,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
@@ -1081,6 +1083,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
*/
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
{
+ /* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim.c
index 80cc1e8cb..30037a4c1 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim.c
@@ -3822,13 +3822,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
+ uint32_t itsource = htim->Instance->DIER;
+ uint32_t itflag = htim->Instance->SR;
+
/* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -3856,11 +3859,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3886,11 +3889,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3916,11 +3919,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3946,11 +3949,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -3959,11 +3962,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@@ -3972,11 +3975,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@@ -3985,11 +3988,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
}
}
/* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
{
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@@ -4476,7 +4479,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -6810,6 +6814,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -6934,7 +6945,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim_ex.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim_ex.c
index 85e84f50d..2af37ec3b 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim_ex.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_tim_ex.c
@@ -835,7 +835,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1081,17 +1081,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
@endverbatim
* @{
*/
@@ -1317,7 +1306,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -2122,7 +2111,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
*/
/**
- * @brief Hall commutation changed callback in non-blocking mode
+ * @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2136,7 +2125,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
*/
}
/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2151,7 +2140,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
}
/**
- * @brief Hall Break detection callback in non-blocking mode
+ * @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2302,15 +2291,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
else
{
/* nothing to do */
@@ -2379,13 +2359,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
{
uint32_t tmp;
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
}
/**
* @}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_uart.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_uart.c
index 0e117a598..3ea2da539 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_uart.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_uart.c
@@ -1165,6 +1165,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1182,6 +1184,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->gState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
@@ -1249,6 +1253,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
+ huart->RxState = HAL_UART_STATE_READY;
+
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
@@ -1777,21 +1783,18 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
status = UART_Start_Receive_DMA(huart, pData, Size);
/* Check Rx process has been successfully started */
- if (status == HAL_OK)
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- {
- __HAL_UART_CLEAR_IDLEFLAG(huart);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
- else
- {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception abortion.
- (Overrun error for instance).
- In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
+ __HAL_UART_CLEAR_IDLEFLAG(huart);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
}
return status;
@@ -3179,19 +3182,31 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
+ return HAL_TIMEOUT;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
+ {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+ {
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_OREFLAG(huart);
- return HAL_TIMEOUT;
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_ERROR;
+ }
}
}
}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_usart.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_usart.c
index dcc8ea9c9..32d42ead4 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_usart.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_usart.c
@@ -2080,6 +2080,9 @@ uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
return husart->ErrorCode;
}
+/**
+ * @}
+ */
/**
* @}
*/
@@ -2794,10 +2797,6 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
}
}
-/**
- * @}
- */
-
/**
* @}
*/
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_wwdg.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_wwdg.c
index 9cc9b1235..8ac487ee7 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_wwdg.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_hal_wwdg.c
@@ -122,7 +122,6 @@
(+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_fsmc.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_fsmc.c
index d4f52dc3d..5c0c20d73 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_fsmc.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_fsmc.c
@@ -60,7 +60,7 @@
* @{
*/
#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \
- || defined(HAL_SRAM_MODULE_ENABLED)
+ || defined(HAL_SRAM_MODULE_ENABLED)
/** @defgroup FSMC_LL FSMC Low Layer
* @brief FSMC driver modules
@@ -193,7 +193,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_InitTypeDef *Init)
+ const FSMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
@@ -273,7 +273,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+ FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
@@ -310,7 +310,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
@@ -325,13 +325,14 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set FSMC_NORSRAM device timing parameters */
- MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FSMC_BTR1_DATAST_Pos) |
- ((Timing->BusTurnAroundDuration) << FSMC_BTR1_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FSMC_BTR1_DATLAT_Pos) |
- (Timing->AccessMode)));
+ Device->BTCR[Bank + 1U] =
+ (Timing->AddressSetupTime << FSMC_BTR1_ADDSET_Pos) |
+ (Timing->AddressHoldTime << FSMC_BTR1_ADDHLD_Pos) |
+ (Timing->DataSetupTime << FSMC_BTR1_DATAST_Pos) |
+ (Timing->BusTurnAroundDuration << FSMC_BTR1_BUSTURN_Pos) |
+ ((Timing->CLKDivision - 1U) << FSMC_BTR1_CLKDIV_Pos) |
+ ((Timing->DataLatency - 2U) << FSMC_BTR1_DATLAT_Pos) |
+ Timing->AccessMode;
return HAL_OK;
}
@@ -349,8 +350,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
- uint32_t ExtendedMode)
+ const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
@@ -494,7 +495,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
* @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
@@ -542,7 +543,7 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
@@ -582,7 +583,7 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
@@ -729,8 +730,8 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank
* @param Timeout Timeout wait value
* @retval HAL status
*/
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
- uint32_t Timeout)
+HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -820,7 +821,7 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval,
* @param Init Pointer to PCCARD Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
@@ -854,7 +855,7 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
@@ -883,7 +884,7 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
@@ -912,7 +913,7 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing)
+ const FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_spi.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_spi.c
index 097ebf630..1ed0a4e00 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_spi.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_spi.c
@@ -119,7 +119,7 @@
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
@@ -168,8 +168,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in SPI configuration registers can only be written when the
+ * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior
+ * calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
@@ -345,7 +346,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
{
return LL_SPI_DeInit(SPIx);
}
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_tim.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_tim.c
index 4d067b304..e025d0406 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_tim.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_tim.c
@@ -748,8 +748,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -777,8 +775,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -827,8 +827,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -856,8 +854,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -906,8 +906,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -935,8 +933,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -985,8 +985,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1014,7 +1012,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
/* Set the Output Idle state */
@@ -1036,7 +1033,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM
return SUCCESS;
}
-
/**
* @brief Configure the TIMx input channel 1.
* @param TIMx Timer Instance
@@ -1161,7 +1157,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
- /* Select the Polarity and set the CC2E Bit */
+ /* Select the Polarity and set the CC4E Bit */
MODIFY_REG(TIMx->CCER,
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_usb.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_usb.c
index fbf6f2eed..5477e95ac 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_usb.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_usb.c
@@ -250,9 +250,9 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else if (mode == USB_DEVICE_MODE)
{
@@ -260,16 +260,16 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else
{
return HAL_ERROR;
}
- if (ms == 50U)
+ if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
{
return HAL_ERROR;
}
@@ -447,7 +447,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -461,7 +461,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -484,7 +484,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -498,7 +498,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -518,7 +518,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -534,7 +534,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
* @arg USBD_HS_SPEED: High speed mode
* @arg USBD_FS_SPEED: Full speed mode
*/
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t speed;
@@ -563,7 +563,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -601,7 +601,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -640,7 +640,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -687,7 +687,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -901,7 +901,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
__IO uint32_t count = 0U;
HAL_StatusTypeDef ret = HAL_OK;
@@ -965,7 +965,7 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* 1 : DMA feature used
* @retval HAL status
*/
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -996,7 +996,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
* @param len Number of bytes to read
* @retval pointer to destination buffer
*/
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t *pDest = dest;
@@ -1038,7 +1038,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -1069,7 +1069,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -1139,7 +1139,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1154,7 +1154,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1171,7 +1171,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1204,7 +1204,7 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
* @param chnum Channel number
* @retval USB Channel Interrupt status
*/
-uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1220,7 +1220,7 @@ uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
* @param USBx Selected device
* @retval USB Device OUT EP interrupt status
*/
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1236,7 +1236,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval USB Device IN EP interrupt status
*/
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1254,7 +1254,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1272,7 +1272,7 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1306,7 +1306,7 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
* 0 : Host
* 1 : Device
*/
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
return ((USBx->GINTSTS) & 0x1U);
}
@@ -1316,7 +1316,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1338,10 +1338,10 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
* @param psetup pointer to setup packet
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
{
@@ -1380,7 +1380,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1394,7 +1394,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1425,7 +1425,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSASEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSBSEN);
- if ((USBx->CID & (0x1U << 8)) != 0U)
+ if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U)
{
if (cfg.speed == USBH_FSLS_SPEED)
{
@@ -1467,8 +1467,8 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Clear any pending interrupts */
USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
-
- if ((USBx->CID & (0x1U << 8)) != 0U)
+#if defined (USB_OTG_HS)
+ if (USBx == USB_OTG_HS)
{
/* set Rx FIFO size */
USBx->GRXFSIZ = 0x200U;
@@ -1476,6 +1476,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
}
else
+#endif /* defined (USB_OTG_HS) */
{
/* set Rx FIFO size */
USBx->GRXFSIZ = 0x80U;
@@ -1507,7 +1508,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1537,7 +1538,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
* @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
*/
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1564,7 +1565,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
* 1 : Activate VBUS
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0 = 0U;
@@ -1670,11 +1671,13 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
}
else
{
- if ((USBx->CID & (0x1U << 8)) != 0U)
+#if defined (USB_OTG_HS)
+ if (USBx == USB_OTG_HS)
{
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
USB_OTG_HCINTMSK_ACKM;
}
+#endif /* defined (USB_OTG_HS) */
}
break;
@@ -1779,12 +1782,13 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
uint16_t num_packets;
uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT;
- if ((USBx->CID & (0x1U << 8)) != 0U)
+#if defined (USB_OTG_HS)
+ if (USBx == USB_OTG_HS)
{
/* in DMA mode host Core automatically issues ping in case of NYET/NAK */
if (dma == 1U)
{
- if ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))
+ if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U))
{
USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
@@ -1801,6 +1805,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
}
}
}
+#endif /* defined (USB_OTG_HS) */
if (hc->do_ssplit == 1U)
{
@@ -2030,7 +2035,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
* @param USBx Selected device
* @retval HAL state
*/
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -2044,7 +2049,7 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t hcnum = (uint32_t)hc_num;
@@ -2128,7 +2133,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t chnum = (uint32_t)ch_num;
@@ -2217,7 +2222,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -2235,7 +2240,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
diff --git a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_utils.c b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_utils.c
index 38ca8d95e..a12641085 100644
--- a/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_utils.c
+++ b/stm32cube/stm32f2xx/drivers/src/stm32f2xx_ll_utils.c
@@ -339,28 +339,25 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
latency = LL_FLASH_LATENCY_0;
}
}
- if (status != ERROR)
- {
- LL_FLASH_SetLatency(latency);
+ LL_FLASH_SetLatency(latency);
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- timeout = 2;
- do
- {
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ timeout = 2;
+ do
+ {
/* Wait for Flash latency to be updated */
getlatency = LL_FLASH_GetLatency();
timeout--;
- } while ((getlatency != latency) && (timeout > 0));
+ } while ((getlatency != latency) && (timeout > 0));
- if(getlatency != latency)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
+ if(getlatency != latency)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ /* No thing to do */
}
}
return status;
diff --git a/stm32cube/stm32f2xx/release_note.html b/stm32cube/stm32f2xx/release_note.html
index 4b730ea97..2ce81e847 100644
--- a/stm32cube/stm32f2xx/release_note.html
+++ b/stm32cube/stm32f2xx/release_note.html
@@ -37,7 +37,7 @@
Purpose
A consistent set of middleware components such as RTOS, USB, TCP/IP, Graphics
All embedded software utilities come with a full set of examples.
-
The STM32Cube firmware solution offers a straightforward API with a modular architecture, making it simple to fine tune custom applications and scalable to fit most requirements
+
The STM32Cube firmware solution offers a straightforward API with a modular architecture, making it simple to fine tune custom applications and scalable to fit most requirements
The HAL (Hardware Abstraction Layer) drivers provided within this package supports the following STM32F2 product lines 205xx/215xx/207xx/217xx
@@ -58,12 +58,240 @@
Purpose
Update History
-
+
Maintenance release
Main Changes
Patch release to fix known defects and enhancements implementation.
+
Upgrade FreeRTOS Lib to use v10.3.1 (ST modified 2023-08-18).
+
HAL updates
+
+
HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
+
HAL/LL CORTEX driver
+
+
Update HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
+
Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().
+
+
HAL/LL ADC driver
+
+
Update __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS() formula to be aligned with reference manual.
+
+
HAL FLASH driver
+
+
Remove HAL_LOCK()/HAL_UNLOCK() from HAL_FLASH_Program_IT() and HAL_FLASHEx_Erase_IT() APIs.
+
+
HAL HASH driver
+
+
Read the last remaining bytes (3 or 2 or 1) of the data in a temporary variable (taking into account swap mode) and enter this variable into the HASH->DIN when the data is not a multiple of 4 bytes.
+
+
HAL CAN driver
+
+
Clarify pin configuration in driver header by removing open-drain information.
+
+
HAL I2C driver
+
+
Solve Slave No stretch not functional by using HAL Slave interface.
+
Clear ACK bit once 3 bytes to read remain to be able to send the NACK once the transfer ends.
+
Update HAL_I2C_Master_Abort_IT() API to support memory abort transfer.
+
Update the HAL I2C driver to reset PreviousState to I2C_STATE_NONE at the end of transfer.
+
+
HAL RNG driver
+
+
Improve performance by removing multiple volatile reads or writes in interrupt handler.
+
+
LL RTC_BKP driver
+
+
Correct misleading note about shadow registers.
+
+
HAL SDMMC driver
+
+
Update HAL SD processes to manage STBITERR flag.
+
+
HAL DCMI driver
+
+
Remove ‘register’ storage class specifier.
+
+
HAL SPI driver
+
+
Update HAL_SPI_TransmitReceive() API to set the bit CRCNEXT in case of one byte transaction.
+
Update IT APIs to enable interrupts after process unlock.
+
Add wait on flag TXE to be set at the end of transaction to be aligned with reference manual.
+
+
HAL I2S driver
+
+
Update HAL I2S driver to fix misplaced __HAL_LOCK() and remove ‘go to’ instruction.
+
+
HAL/LL TIM driver
+
+
Improve performance by removing multiple volatile reads or writes in interrupt handler.
+
Update interrupt flag is cleared when the update event is generated by software.
+
Improve HAL TIM driver’s operational behavior.
+
Improve period configuration parameter check.
+
Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().
+
Add LL_TIM_CC_IsEnabledPreload() API.
+
+
HAL UART driver
+
+
Avoid ORE flag to be cleared by a transmit process in polling mode.
+
Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
+
+
HAL IWDG driver
+
+
Calculate the maximum IWDG Timeout period “HAL_IWDG_DEFAULT_TIMEOUT” based on a Prescaler=128 at LSI frequency=32kHz.
+
+
HAL USB_OTG driver
+
+
Fix device connection in case battery charging is used with HS instance linked to internal FS PHY.
+
ll_usb.c: increase timeout value to allow core reset to complete.
+
ll_usb.c: improve delay management to set core mode.
+
hal_hcd.c: ensure to reactivate the usb channel in case of transfer error.
+
+
LL UTILS_ driver
+
+
Fix a note about Ticks parameter.
+
+
+
Middleware
+
+
Upgrade FreeRTOS Lib to use v10.3.1 (ST modified 2023-08-18).
+
+
Projects updates
+
+
NUCLEO-F207ZG
+
+
USB Host MSC applications: fix Stack corruption due to inconsistent type of local variable in MSC_File_Operations().
+
+
STM322xG_EVAL
+
+
FreeRTOS_LowPower application: Update FreeRTOS LowPower application to support FreeRTOS v10.3.1.
Warnings detected with LibJPEG applications are related to the Libjpeg third party MW stack V8d with System Workbench for STM32 (SW4STM32) V2.9:
No impact of these warnings on the functional behavior
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-LINK
@@ -517,8 +745,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release of STM32CubeF2 Firmware Package.
HAL
@@ -532,7 +760,7 @@
Main Changes
-
Contents
+
Contents
Drivers
@@ -555,8 +783,8 @@
Contents
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General updates to fix known defects and enhancements implementation
HAL
@@ -816,7 +1044,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
@@ -838,11 +1066,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.26 + ST-LINK
@@ -866,8 +1094,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General updates to fix known defects and enhancements implementation
HAL
@@ -904,7 +1132,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
@@ -1065,14 +1293,14 @@
Contents
-
Known Limitations
+
Known Limitations
Warnings detected with LibJPEG applications are related to the Libjpeg third party MW stack V8d with System Workbench for STM32 (SW4STM32) V2.9:
No impact of these warnings on the functional behavior
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.26 + ST-LINK
@@ -1096,8 +1324,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General updates to fix known defects and enhancements implementation
General updates to fix CodeSonar compilation warnings
@@ -1220,7 +1448,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
@@ -1381,14 +1609,14 @@
Contents
-
Known Limitations
+
Known Limitations
Warnings detected with LibJPEG applications are related to the Libjpeg third party MW stack V8d with System Workbench for STM32 (SW4STM32) V2.9:
No impact of these warnings on the functional behavior
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2+ ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.26 + ST-LINK
@@ -1412,8 +1640,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General updates to be compliant with Linux platforms
General update to fix known defects and several implementations enhancement
@@ -1439,7 +1667,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
Drivers
@@ -1601,11 +1829,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.4 + ST-Link
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23 + ST-LINK
@@ -1629,8 +1857,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
General update to fix known defects and several implementations enhancement
HAL
@@ -1649,7 +1877,7 @@
Main Changes
-
Contents
+
Contents
Drivers
@@ -1811,11 +2039,11 @@
Contents
-
Known Limitations
+
Known Limitations
STemWin sample demo application on STM322xG_EVAL is not fully functional with MDK-ARM toolchain: the application doesn’t run successfully after the second hit of the Hide Button. in fact when pressing the button again while the progress bar displays the next steps, pressing Hide or Next Buttons are not working anymore.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23
@@ -1840,8 +2068,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Add Low Layer drivers under Drivers32F2xx_HAL_Driver
@@ -1901,7 +2129,7 @@
Main Changes
Update overall projects to be aligned with latest version of HAL, BSP and Middleware drivers
-
Contents
+
Contents
Drivers
@@ -2063,11 +2291,11 @@
Contents
-
Known Limitations
+
Known Limitations
STemWin sample demo application on STM322xG_EVAL is not fully functional with MDK-ARM toolchain: the application doesn’t run successfully after the second hit of the Hide Button. in fact when pressing the button again while the progress bar displays the next steps, pressing Hide or Next Buttons are not working anymore.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.80.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.23
@@ -2092,8 +2320,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Maintenance release to fix known defects and several enhancements implementation
HAL
@@ -2148,7 +2376,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
Drivers
@@ -2310,11 +2538,11 @@
Contents
-
Known Limitations
+
Known Limitations
STemWin sample demo application on STM322xG_EVAL is not fully functional with MDK-ARM toolchain: the application doesn’t run successfully after the second hit of the Hide Button. in fact when pressing the button again while the progress bar displays the next steps, pressing Hide or Next Buttons are not working anymore.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain v7.60.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain v5.20
@@ -2339,12 +2567,12 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release to fix issue in Ethernet HAL driver
-
Contents
+
Contents
Drivers
@@ -2362,11 +2590,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.40.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.16
@@ -2391,8 +2619,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Support new board: STM32F207ZG NUCLEO144
Fix known defects and enhancements implementation
@@ -2428,7 +2656,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
Drivers
@@ -2590,11 +2818,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V7.40.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.16
@@ -2619,8 +2847,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Maintenance release to fix known defects and several enhancements implementation
HAL
@@ -2659,7 +2887,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware components
-
Contents
+
Contents
Drivers
@@ -2811,11 +3039,11 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain v7.40.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain v5.16
A consistent set of middleware components such as RTOS, USB, TCP/IP, Graphics
All embedded software utilities come with a full set of examples.
-
The STM32Cube firmware solution offers a straightforward API with a modular architecture, making it simple to fine tune custom applications and scalable to fit most requirements
+
The STM32Cube firmware solution offers a straightforward API with a modular architecture, making it simple to fine tune custom applications and scalable to fit most requirements
The HAL (Hardware Abstraction Layer) drivers provided within this package supports the STM32F405/415/407/417/427/437/429/439/401xC/401xE/ 411xC/411xE/412x/413/423/446/469/479/410xx Lines
@@ -60,12 +60,595 @@
Purpose
Update History
-
+
Maintenance release
Main Changes
General updates to fix known defects and implementation enhancements.
+
Patch release to deploy HAL Ethernet enhancements.
+
General fixes to support GCC11 and GCC12 in all STM32CubeIDE projects.
+
Upgrade USB Device Lib to use V2.11.3.
+
Upgrade USB Host Lib to use V3.5.2.
+
CMSIS
+
+
Add MCO2PRE[2:0] and MCO2[1:0] bits definition within CMSIS files.
+
+
HAL
+
+
Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers.
+
HAL Generic
+
+
Update stm32h7xx_hal_conf_template.h file to support legacy HAL ETH driver.
+
+
HAL/LL ADC
+
+
Add macro UNUSED() to avoid the generation of a warning related to the unused argument ‘hadc’.
+
+
HAL RCC
+
+
Remove duplicate macro definition __HAL_RCC_AHB2_FORCE_RESET() for STM32F423xx devices.
+
+
HAL EXTI
+
+
Add macro UNUSED() to avoid the generation of a warning related to the unused argument ‘Edge’.
+
+
HAL HASH
+
+
Read the last remaining bytes (3 or 2 or 1) of the data in a temporary variable (taking into account swap mode) and enter this variable into the HASH->DIN when the data is not a multiple of 4 bytes.
+
+
HAL FLASH
+
+
Remove HAL_LOCK()/HAL_UNLOCK() APIs from HAL_FLASH_Program_IT() and HAL_FLASHEx_Erase_IT() APIs.
+
+
LL DMA
+
+
Fix typo in LL_DMA_GetCurrentTargetMem() API.
+
+
HAL LPTIM
+
+
Remove redundant macro IS_LPTIM_AUTORELOAD().
+
+
HAL/LL CORTEX
+
+
Updated HAL_MPU_ConfigRegion() API to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
+
Add new HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion() APIs.
+
Add missing parenthesis() in LL_MPU_ConfigRegion() API.
+
+
HAL DSI
+
+
Align DSI Initialization sequence to the recommended ‘Programing procedure overview’ part to avoid DSI read LCD controller register 0x0A error.
+
+
HAL QSPI
+
+
Clear the QSPI.AR register when sCommand.AddressMode is QSPI_ADDRESS_NONE.
+
+
HAL I2S
+
+
Update HAL I2S driver to fix misplaced __HAL_LOCK() API and remove ‘go to’ instruction.
+
+
HAL SPI
+
+
Update HAL SPI driver to remove “got to” instruction and avoid misplaced __HAL_LOCK() API issue.
+
+
HAL UART
+
+
Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
+
+
HAL ETH
+
+
Add missing system time in different PTP APIs.
+
Rename ETH_TxPacketConfig_t to ETH_TxPacketConfigTypeDef.
+
Update ETH_Start_IT sequence.
+
Update the PTP configuration state macros and Fix the wrong Doxygen comment descriptions.
+
Fix wrong Ethernet constant definitions .
+
Add condition to get the Timestamp only when it was captured (Check on Last Descriptor and TimeStamp flag set).
+
Replace ETH_RX_BUF_SIZE define in ETH_UpdateDescriptor() and ETH_DMARxDescListInit() by Init.RxBuffLen.
+
Get the latest buffer length received and not the predefined ethernet frame length.
+
Update HAL_ETH_SetMDIOClockRange API to manage different frequency ranges.
+
Remove multiple volatile reads or writes in interrupt handler for better performance.
+
Move the MMC interrupts disable section from HAL_ETH_Start_IT() to HAL_ETH_Init().
+
Change the way to increment the descriptor index within HAL_ETH_ReleaseTxPacket().
+
Update the entry to critical section without enabling unwanted global interrupts.
+
Add support of CRC stripping for Type frames (CSTF) feature.
+
Fix MisraC-2012 and MCU ASTYLE warnings and remove empty lines.
+
+
HAL USB
+
+
Ensure to reactivate the usb channel in case of transfer error.
+
+
LL UTILS
+
+
Fix a note about Ticks parameter.
+
+
+
BSP
+
+
BSP Boards
+
+
STM32F413H-Discovery
+
+
Update to manage touch screen components (ft6x06 & ft3x67) available on different STM32F413H-Discovery board revisions in dynamic approach.
+
+
STM32412G-Discovery
+
+
Update to manage touch screen components (ft6x06 & ft3x67) available on different STM32412G-Discovery board revisions in dynamic approach.
+
+
STM32469I-Discovery
+
+
Update to manage lcd controller components (nt35510 & otm8009a) available on different STM32469I-Discovery board revisions in dynamic approach.
+
+
+
BSP Components
+
+
nt35510
+
+
Fix setting of DPRSLCTR register.
+
+
lan8742
+
+
Remove unnecessary delay in PHY driver.
+
+
+
+
Middlewares
+
+
Upgrade USB Device Lib to use V2.11.3.
+
Upgrade USB Host Lib to use V3.5.2.
+
+
Projects
+
+
Applications MW LwIP
+
+
Fix Confusing comment in ethernet_if.
+
Fix Wrong use of DHCP API in application code & ethernet_link_thread() API.
+
Fix Ethernet low_level_init() API does not handle return code from LAN8742_init() API.
+
+
Examples I2C
+
+
Fix wrong check condition on HAL_TIMEOUT: this value is no longer returned by the HAL_I2C_IsDeviceReady() API.
+
+
+
For the complete list of changes, please refer to the release notes of each firmware component
STM32F429xx/439xx devices and STM324x9I-EVAL board RevB
+
STM32F429xx and STM32F429I-Discovery board RevB
+
STM32F407xx/417xx devices and STM324xG-EVAL board RevC
+
STM32F407xx and STM32F4-Discovery board RevC
+
STM32F401xC and STM32F401C-Discovery board RevB
+
STM32F401xE and STM32F401RE-Nucleo board RevC
+
STM32F411xE and STM32F411RE-Nucleo board RevC
+
STM32F411xE and STM32F411E-Discovery board RevC
+
STM32F412ZG and STM32F412ZG-Discovery board RevD
+
STM32F446ZE and STM32F446ZE-Nucleo board RevB
+
STM32F429ZI and STM32F429ZI-Nucleo board RevB
+
STM32F412ZG and STM32F412ZG-Nucleo board RevB
+
STM32F413ZHT6U and STM32F413ZH-Nucleo board RevB
+
STM32F413ZHT6U and STM32F413H-Discovery board RevD
+
+
Backward Compatibility
+
+
None
+
+
Dependencies
+
+
None
+
+
+
+
+
+
+
Maintenance release
+
Main Changes
+
+
General updates to fix known defects and implementation enhancements.
Deploy the support of STM32CubeIDE toolchain on all projects
SW4STM32 toolchain support is discontinued (Warning : Any reference to SW4STM32 in STM32CubeF4 firmware package documents should be interpreted as STM32CubeIDE).
@@ -312,7 +895,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
Drivers
@@ -669,7 +1252,7 @@
Contents
-
Known Limitations
+
Known Limitations
USB_Device_Standalone application for STM324x9I_EVAL
@@ -697,7 +1280,7 @@
Known Limitations
Only template projects migrated to Arm Compiler 6 with MDK-ARM 5.31 (“AC-like Warnings” mode).
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-Link.
STM32F413ZHT6U and STM32F413H-Discovery board RevD
-
Backward Compatibility
+
Backward Compatibility
None
-
Dependencies
+
Dependencies
None
@@ -3389,8 +3972,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Maintenance release:
@@ -3402,8 +3985,8 @@
Main Changes
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Thanks to the acquisition of Draupner Graphics A/S, ST is extending the STM32 ecosystem with advanced and easy to use graphic software solution enabling stunning GUI additions to embedded devices. TouchGFX solution is now fully part of STM32CubeF4.
TouchGFX examples and demonstrations can be accessed directly through the TouchGFX Designer tool. Here you simply create a new project, select the appropriate ST board in the Application Template section and select whatever demonstration or example you want in the UI Template selector. After this you will have a TouchGFX application ready to compile and flash to the selected ST board. More information are available here
@@ -3430,7 +4013,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
Drivers
@@ -3752,7 +4335,7 @@
Contents
-
Known Limitations
+
Known Limitations
USB_Device_Standalone application for STM324x9I_EVAL
@@ -3768,13 +4351,13 @@
Known Limitations
SW4STM32 projects are not provided for all EVAL and Discovery demonstrations
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2 + ST-Link.
RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
System Workbench for STM32 (SW4STM32) toolchain V2.6.0 + ST-Link
STM32F413ZHT6U and STM32F413H-Discovery board RevD
-
Backward Compatibility
+
Backward Compatibility
None
-
Dependencies
+
Dependencies
None
@@ -5846,8 +6429,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Official release to add the support of STM32F413xx and STM32F423xx devices
Fix known defects and several implementation enhancement
@@ -5897,7 +6480,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
Drivers
@@ -6209,7 +6792,7 @@
Contents
-
Known Limitations
+
Known Limitations
USB_Device_Standalone application for STM324x9I_EVAL
@@ -6218,14 +6801,14 @@
Known Limitations
TrueSTUDIO and SW4STM32 projects are not provided for all EVAL and Discovery demonstrations
STemWin sample demo applications with all STM32 platforms are not fully functional with MDK-ARM toolchain: the application doesn t run successfully after the second hit of the Hide Button. in fact when presing the button again while the progress bar displays the next steps, pressing Hide or Next Buttons are not working anymore.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain v7.60.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain v5.21a + Keil.STM32F4xx_DFP.2.11.0.pack
Patch release to fix issues in I2C/FMPI2C HAL drivers
-
Contents
+
Contents
@@ -6285,8 +6868,8 @@
Contents
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Fix known defects and enhancements implementation
HAL
@@ -6333,7 +6916,7 @@
Main Changes
For the complete list of changes, please refer to the release notes of each firmware component
-
Contents
+
Contents
Drivers
@@ -6645,21 +7228,21 @@
Contents
-
Known Limitations
+
Known Limitations
USB_Device_Standalone application for STM324x9I_EVAL
MDK-ARM and TrueSTUDIO projects are provided with optimization set to None, to avoid audio glitch when USB cable is disconnected
TrueSTUDIO and SW4STM32 projects are not provided for all EVAL and Discovery demonstrations
STemWin sample demo applications with all STM32 platforms are not fully functional with MDK-ARM toolchain: the application doesn t run successfully after the second hit of the Hide Button. in fact when presing the button again while the progress bar displays the next steps, pressing Hide or Next Buttons are not working anymore.
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain v7.60.1
RealView Microcontroller Development Kit (MDK-ARM) toolchain v5.20 + Keil.STM32F4xx_DFP.2.6.1.pack
System Workbench for STM32 (SW4STM32) toolchain V1.1.0 + ST-Link
-
Supported Devices and EVAL boards
+
Supported Devices and EVAL boards
STM32F446xx devices STM32446E_EVAL board RevB
STM32F429xx/439xx devices and STM324x9I-EVAL board RevB
@@ -9051,11 +9634,11 @@
Supported Devices and EVAL boards<
STM32F411xE and STM32F411RE-Nucleo board RevC
STM32F446RE and STM32446E-Nucleo board RevC
-
Backward Compatibility
+
Backward Compatibility
None
-
Dependencies
+
Dependencies
None
@@ -9064,8 +9647,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Add support of System Workbench for STM32 (SW4STM32) toolchain
Maintenance release to fix known defects
@@ -9105,7 +9688,7 @@
Main Changes
Fix compile issue in some projects (9 in total), mainly due to bad project settings
-
Contents
+
Contents
Drivers
@@ -9392,7 +9975,7 @@
Contents
-
Known Limitations
+
Known Limitations
SW4STM32 projects are not provided for STM32446E_EVAL board, will be added in next release
The following issues are detected when using EWARM V7.30, however they are not present when using EWARM V7.10, they will be fixed in next release:
@@ -9424,7 +10007,7 @@
Known Limitations
Robustness to be improved, the application may not work correctly after several board reset
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain v7.30
System Workbench for STM32 (SW4STM32) toolchain V1.1.0 + ST-Link
-
Supported Devices and EVAL boards
+
Supported Devices and EVAL boards
STM32F429xx/439xx devices and STM324x9I-EVAL board RevB
STM32F429xx and STM32F429I-Discovery board RevB
@@ -10598,11 +11181,11 @@
Supported Devices and EVAL boards<
STM32F401xE and STM32F401RE-Nucleo board RevC
STM32F411xE and STM32F411RE-Nucleo board RevC
-
Backward Compatibility
+
Backward Compatibility
None
-
Dependencies
+
Dependencies
None
@@ -10611,20 +11194,24 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Patch release for STM32CubeF4, adding support of STM32F411xE devices with several enhancements and bugs fix
-
In this release; only the Firmware components drivers are provided, the projects for the supported boards will be provided in the upcoming release V1.2.1
-
HAL and CMSIS
+
In this release; only the Firmware components drivers are provided, the projects for the supported boards will be provided in the upcoming release V1.2.1
+
+
HAL and CMSIS
+
Add support of STM32F411xE devices
Several enhancements and bugs fix
-
Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.x version
-
Middleware
+
Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.x version
+
+
Middleware
+
Use updated version V5.24b of STemWin; adding many new features, with PC simulation resources added and binaries compiled for high speed optimization
Add LibJPEG library for JPEG images encoding and decoding
-
Miscellaneous update and minor bugs fix
+
Miscellaneous update and minor bugs fix
BSP
@@ -10634,7 +11221,7 @@
Main Changes
Note: for the complete list of changes, please refer to the release notes of each Firmware component
-
Contents
+
Contents
Drivers
@@ -10916,17 +11503,17 @@
Contents
-
Known Limitations
+
Known Limitations
None
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain v7.10.2
RealView Microcontroller Development Kit (MDK-ARM) toolchain v5.10
STM32F429xx/439xx devices and STM324x9I-EVAL board RevB
STM32F429xx and STM32F429I-Discovery board RevB
@@ -10936,11 +11523,11 @@
Supported Devices and EVAL boards<
STM32F401xE and STM32F401RE-Nucleo board RevC
STM32F411xE and STM32F411RE-Nucleo board RevC
-
Backward Compatibility
+
Backward Compatibility
None
-
Dependencies
+
Dependencies
None
@@ -10949,8 +11536,8 @@
Dependencies
-
Maintenance release
-
Main Changes
+
Maintenance release
+
Main Changes
Add sources of STM324x9I-EVAL (both references MB1046 and MB1063), STM324xG-EVAL and STM32F429I-Discovery Demonstration (only for EWARM and MDK-ARM)
@@ -10960,7 +11547,7 @@
Main Changes
Miscellaneous update on Examples, Applications, Demonstrations and Templates projects for some boards; for more details refer to the associated release notes
Minor update in STM324x9I-EVAL, STM324xG-EVAL and STM32F429I-Discovery uSD and EEPROM BSP drivers
-
Contents
+
Contents
Drivers
@@ -11227,11 +11814,11 @@
Contents
-
Known Limitations
+
Known Limitations
TrueSTUDIO projects are not provided for few Applications and Demonstrations (10 in total)
-
Development Toolchains and Compilers
+
Development Toolchains and Compilers
IAR Embedded Workbench for ARM (EWARM) toolchain V6.70.3