From 34461b8d546679cb32e0fa5b728482e208388c7f Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Tue, 30 Jul 2024 15:22:41 -0400
Subject: [PATCH 1/6] update SC

---
 umi/__init__.py      | 27 +++++----------------------
 umi/lumi/__init__.py | 21 +++++++++++++++++++++
 umi/umi/__init__.py  | 19 +++++++++++++++++++
 3 files changed, 45 insertions(+), 22 deletions(-)
 create mode 100644 umi/lumi/__init__.py
 create mode 100644 umi/umi/__init__.py

diff --git a/umi/__init__.py b/umi/__init__.py
index 3e04bd4..be7a7c7 100644
--- a/umi/__init__.py
+++ b/umi/__init__.py
@@ -1,28 +1,11 @@
-from siliconcompiler import Library
-import lambdalib
+from umi import umi, lumi
 
 
 __version__ = "0.1.1"
 
 
-def _register_umi(lib):
-    lib.register_source("umi", "python://umi")
-
-
 def setup(chip):
-    libs = []
-
-    for name in ('umi', 'lumi'):
-        lib = Library(chip, name, package="umi")
-        _register_umi(lib)
-        lib.use(lambdalib)
-
-        lib.add("option", "idir", f"{name}/rtl")
-        lib.add("option", "ydir", f"{name}/rtl")
-
-        lib.add("option", "idir", "utils/rtl")
-        lib.add("option", "ydir", "utils/rtl")
-
-        libs.append(lib)
-
-    return libs
+    return [
+        umi.setup(chip),
+        lumi.setup(chip)
+    ]
diff --git a/umi/lumi/__init__.py b/umi/lumi/__init__.py
new file mode 100644
index 0000000..944d14f
--- /dev/null
+++ b/umi/lumi/__init__.py
@@ -0,0 +1,21 @@
+from siliconcompiler import Library
+from umi import umi
+from lambdalib import auxlib, ramlib
+
+
+def setup(chip):
+    lib = Library(chip, "lumi", package="umi", auto_enable=True)
+    lib.register_source("umi", "python://umi")
+
+    lib.add("option", "idir", "lumi/rtl")
+    lib.add("option", "ydir", "lumi/rtl")
+
+    lib.add("option", "idir", "utils/rtl")
+    lib.add("option", "ydir", "utils/rtl")
+
+    lib.use(umi)
+
+    lib.use(auxlib)
+    lib.use(ramlib)
+
+    return lib
diff --git a/umi/umi/__init__.py b/umi/umi/__init__.py
new file mode 100644
index 0000000..bb9fd60
--- /dev/null
+++ b/umi/umi/__init__.py
@@ -0,0 +1,19 @@
+from siliconcompiler import Library
+from lambdalib import auxlib, ramlib, vectorlib
+
+
+def setup(chip):
+    lib = Library(chip, "umi", package="umi", auto_enable=True)
+    lib.register_source("umi", "python://umi")
+
+    lib.add("option", "idir", "umi/rtl")
+    lib.add("option", "ydir", "umi/rtl")
+
+    lib.add("option", "idir", "utils/rtl")
+    lib.add("option", "ydir", "utils/rtl")
+
+    lib.use(auxlib)
+    lib.use(ramlib)
+    lib.use(vectorlib)
+
+    return lib

From 629ca4356d02fed0081a7cf3a8869f477fe67588 Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Tue, 30 Jul 2024 15:24:31 -0400
Subject: [PATCH 2/6] update dependencies

---
 pyproject.toml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pyproject.toml b/pyproject.toml
index f715f97..7b0dd51 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -17,8 +17,8 @@ urls = {Homepage = "https://github.com/zeroasiccorp/umi"}
 requires-python = ">= 3.8"
 license = {file = "LICENSE"}
 dependencies = [
-    "siliconcompiler>=0.24.0",
-    "lambdalib>=0.2.4, <0.2.7"
+    "siliconcompiler>=0.26.0",
+    "lambdalib>=0.2.8, <0.2.9"
 ]
 dynamic = [
     "version"

From 318e384c3a238635efaff8a9d691ebc4895bc060 Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Tue, 30 Jul 2024 15:36:35 -0400
Subject: [PATCH 3/6] update testbenches

---
 umi/lumi/testbench/test_lumi.py                     | 8 ++------
 umi/lumi/testbench/test_lumi_rnd.py                 | 8 ++------
 umi/umi/testbench/test_crossbar.py                  | 6 +-----
 umi/umi/testbench/test_fifo.py                      | 5 +----
 umi/umi/testbench/test_fifo_flex.py                 | 5 +----
 umi/umi/testbench/test_mem_agent.py                 | 5 +----
 umi/umi/testbench/test_regif.py                     | 4 +---
 umi/umi/testbench/test_umi_ram.py                   | 6 +-----
 umi/utils/testbench/test_tl2umi_np.py               | 7 +------
 umi/utils/testbench/test_umi2apb.py                 | 4 +---
 umi/utils/testbench/test_umi2axilite.py             | 6 +-----
 umi/utils/testbench/test_umi2tl_np.py               | 3 +--
 umi/utils/testbench/test_umi_address_remap.py       | 3 +--
 umi/utils/testbench/test_umi_packet_merge_greedy.py | 3 +--
 14 files changed, 16 insertions(+), 57 deletions(-)

diff --git a/umi/lumi/testbench/test_lumi.py b/umi/lumi/testbench/test_lumi.py
index 0ab114f..c5ed235 100755
--- a/umi/lumi/testbench/test_lumi.py
+++ b/umi/lumi/testbench/test_lumi.py
@@ -9,7 +9,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue
-import umi
+from umi import lumi
 
 
 def build_testbench(topo="2d", trace=False):
@@ -24,11 +24,7 @@ def build_testbench(topo="2d", trace=False):
     else:
         raise ValueError('Invalid topology')
 
-    dut.use(umi)
-    dut.add('option', 'library', ['lumi', 'umi'])
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
+    dut.use(lumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'lumi/testbench/config.vlt', package='umi')
diff --git a/umi/lumi/testbench/test_lumi_rnd.py b/umi/lumi/testbench/test_lumi_rnd.py
index 118f692..a7f65f3 100755
--- a/umi/lumi/testbench/test_lumi_rnd.py
+++ b/umi/lumi/testbench/test_lumi_rnd.py
@@ -9,7 +9,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue
-import umi
+from umi import lumi
 
 
 def build_testbench(topo="2d", trace=False):
@@ -24,11 +24,7 @@ def build_testbench(topo="2d", trace=False):
     else:
         raise ValueError('Invalid topology')
 
-    dut.use(umi)
-    dut.add('option', 'library', ['lumi', 'umi'])
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
+    dut.use(lumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'lumi/testbench/config.vlt', package='umi')
diff --git a/umi/umi/testbench/test_crossbar.py b/umi/umi/testbench/test_crossbar.py
index d43e584..fd35cfd 100755
--- a/umi/umi/testbench/test_crossbar.py
+++ b/umi/umi/testbench/test_crossbar.py
@@ -8,7 +8,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import UmiTxRx, random_umi_packet, delete_queue, verilator_run, SbDut
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -18,10 +18,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_crossbar.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
diff --git a/umi/umi/testbench/test_fifo.py b/umi/umi/testbench/test_fifo.py
index d4b3d24..b25e63d 100755
--- a/umi/umi/testbench/test_fifo.py
+++ b/umi/umi/testbench/test_fifo.py
@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -17,9 +17,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_fifo.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
diff --git a/umi/umi/testbench/test_fifo_flex.py b/umi/umi/testbench/test_fifo_flex.py
index 5437674..e379a5d 100755
--- a/umi/umi/testbench/test_fifo_flex.py
+++ b/umi/umi/testbench/test_fifo_flex.py
@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench(split=False):
@@ -17,9 +17,6 @@ def build_testbench(split=False):
     dut.input('umi/testbench/testbench_fifo_flex.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     dut.add('option', 'define', f'SPLIT={int(split)}')
 
diff --git a/umi/umi/testbench/test_mem_agent.py b/umi/umi/testbench/test_mem_agent.py
index 72601cb..4214a42 100755
--- a/umi/umi/testbench/test_mem_agent.py
+++ b/umi/umi/testbench/test_mem_agent.py
@@ -6,7 +6,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -16,9 +16,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_mem_agent.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
diff --git a/umi/umi/testbench/test_regif.py b/umi/umi/testbench/test_regif.py
index 9ea7857..f9f2378 100755
--- a/umi/umi/testbench/test_regif.py
+++ b/umi/umi/testbench/test_regif.py
@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -17,8 +17,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_regif.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
diff --git a/umi/umi/testbench/test_umi_ram.py b/umi/umi/testbench/test_umi_ram.py
index 3db6cb3..a0479e0 100755
--- a/umi/umi/testbench/test_umi_ram.py
+++ b/umi/umi/testbench/test_umi_ram.py
@@ -6,7 +6,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -16,10 +16,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_umi_ram.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')
diff --git a/umi/utils/testbench/test_tl2umi_np.py b/umi/utils/testbench/test_tl2umi_np.py
index 5242abf..b84e422 100755
--- a/umi/utils/testbench/test_tl2umi_np.py
+++ b/umi/utils/testbench/test_tl2umi_np.py
@@ -3,7 +3,7 @@
 from siliconcompiler import Chip
 from siliconcompiler.flows import dvflow
 from siliconcompiler.package import path as sc_path
-import umi
+from umi import umi
 
 
 def build():
@@ -15,11 +15,6 @@ def build():
 
     chip.input('utils/testbench/tb_tl2umi_np.v', package='umi')
 
-    chip.add('option', 'library', 'umi')
-    chip.add('option', 'library', 'lambdalib_auxlib')
-    chip.add('option', 'library', 'lambdalib_ramlib')
-    chip.add('option', 'library', 'lambdalib_vectorlib')
-
     memfile = f"{sc_path(chip, 'umi')}/utils/testbench/buffer.memh"
 
     chip.add('tool', 'execute', 'task', 'exec_input', 'option', f'+MEMHFILE={memfile}')
diff --git a/umi/utils/testbench/test_umi2apb.py b/umi/utils/testbench/test_umi2apb.py
index c3e18bb..feac78e 100755
--- a/umi/utils/testbench/test_umi2apb.py
+++ b/umi/utils/testbench/test_umi2apb.py
@@ -6,7 +6,7 @@
 import random
 import numpy as np
 from switchboard import SbDut, UmiTxRx, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench(dut):
@@ -14,8 +14,6 @@ def build_testbench(dut):
     dut.input('utils/testbench/testbench_umi2apb.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'utils/testbench/config.vlt',
diff --git a/umi/utils/testbench/test_umi2axilite.py b/umi/utils/testbench/test_umi2axilite.py
index 23dda57..538c518 100755
--- a/umi/utils/testbench/test_umi2axilite.py
+++ b/umi/utils/testbench/test_umi2axilite.py
@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -17,10 +17,6 @@ def build_testbench():
     dut.input('utils/testbench/testbench_umi2axilite.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config',
diff --git a/umi/utils/testbench/test_umi2tl_np.py b/umi/utils/testbench/test_umi2tl_np.py
index 85c6aba..6453353 100755
--- a/umi/utils/testbench/test_umi2tl_np.py
+++ b/umi/utils/testbench/test_umi2tl_np.py
@@ -8,7 +8,7 @@
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
 from siliconcompiler.package import path as sc_path
-import umi
+from umi import umi
 
 
 def build_testbench(topo="2d"):
@@ -29,7 +29,6 @@ def build_testbench(topo="2d"):
     dut.input('utils/testbench/tlmemsim.cpp', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', ['umi', 'lambdalib_auxlib'])
 
     # Verilator configuration
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '--coverage')
diff --git a/umi/utils/testbench/test_umi_address_remap.py b/umi/utils/testbench/test_umi_address_remap.py
index 6297379..dee3129 100755
--- a/umi/utils/testbench/test_umi_address_remap.py
+++ b/umi/utils/testbench/test_umi_address_remap.py
@@ -5,7 +5,7 @@
 import random
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run, random_umi_packet
-import umi
+from umi import umi
 
 
 def build_testbench(topo="2d"):
@@ -23,7 +23,6 @@ def build_testbench(topo="2d"):
         raise ValueError('Invalid topology')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'utils/testbench/config.vlt', package='umi')
diff --git a/umi/utils/testbench/test_umi_packet_merge_greedy.py b/umi/utils/testbench/test_umi_packet_merge_greedy.py
index 6c86ead..6dacc51 100755
--- a/umi/utils/testbench/test_umi_packet_merge_greedy.py
+++ b/umi/utils/testbench/test_umi_packet_merge_greedy.py
@@ -4,7 +4,7 @@
 
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run, random_umi_packet
-import umi
+from umi import umi
 
 
 def build_testbench(topo="2d"):
@@ -24,7 +24,6 @@ def build_testbench(topo="2d"):
     dut.input('utils/testbench/testbench_umi_packet_merge_greedy.cc', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'utils/testbench/config.vlt', package='umi')

From e202ad94eda396d15abd84a4ecf8ab2161df5730 Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Tue, 30 Jul 2024 16:02:03 -0400
Subject: [PATCH 4/6] pin lambdalib version

---
 pyproject.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pyproject.toml b/pyproject.toml
index 7b0dd51..fe585cc 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -18,7 +18,7 @@ requires-python = ">= 3.8"
 license = {file = "LICENSE"}
 dependencies = [
     "siliconcompiler>=0.26.0",
-    "lambdalib>=0.2.8, <0.2.9"
+    "lambdalib>=0.2.9, <0.2.10"
 ]
 dynamic = [
     "version"

From ff7236b9c5919f6bcb16ab42cdf9bbb057629fd8 Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Tue, 30 Jul 2024 16:13:43 -0400
Subject: [PATCH 5/6] pin SB to 0.2.14

---
 pyproject.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pyproject.toml b/pyproject.toml
index fe585cc..bf05348 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -29,7 +29,7 @@ version = {attr = "umi.__version__"}
 
 [project.optional-dependencies]
 test = [
-    "switchboard-hw",
+    "switchboard-hw>=0.2.14",
     "flake8==7.1.0"
 ]
 

From befbb27ec54e541f0e13d3ac0794f3243fb9ca2a Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Tue, 30 Jul 2024 16:27:15 -0400
Subject: [PATCH 6/6] TYPE->PROP

---
 umi/lumi/rtl/lumi_rx.v      | 10 +++++-----
 umi/lumi/rtl/lumi_tx.v      |  2 +-
 umi/umi/rtl/umi_mem_agent.v |  2 +-
 umi/utils/rtl/tl2umi_np.v   |  2 +-
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/umi/lumi/rtl/lumi_rx.v b/umi/lumi/rtl/lumi_rx.v
index 5cf22fc..c36e756 100644
--- a/umi/lumi/rtl/lumi_rx.v
+++ b/umi/lumi/rtl/lumi_rx.v
@@ -550,7 +550,7 @@ module lumi_rx
                       .CHAOS(0),         // generates random full logic when set
                       .CTRLW(1),         // width of asic ctrl interface
                       .TESTW(1),         // width of asic test interface
-                      .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                      .PROP("DEFAULT"))  // Pass through variable for hard macro
         req_fifo_i(// Outputs
                    .wr_full          (req_fifo_full[j]),
                    .rd_dout          (req_fifo_dout[j*RXFIFOW+:RXFIFOW]),
@@ -598,7 +598,7 @@ module lumi_rx
                       .CHAOS(0),         // generates random full logic when set
                       .CTRLW(1),         // width of asic ctrl interface
                       .TESTW(1),         // width of asic test interface
-                      .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                      .PROP("DEFAULT"))  // Pass through variable for hard macro
         resp_fifo_i(// Outputs
                     .wr_full          (resp_fifo_full[k]),
                     .rd_dout          (resp_fifo_dout[k*RXFIFOW+:RXFIFOW]),
@@ -663,7 +663,7 @@ module lumi_rx
                   .CHAOS(0),  // generates random full logic when set
                   .CTRLW(1),  // width of asic ctrl interface
                   .TESTW(1),  // width of asic test interface
-                  .TYPE("DEFAULT")) // Pass through variable for hard macro
+                  .PROP("DEFAULT")) // Pass through variable for hard macro
    lnk_fifo_i(// Outputs
               .wr_full          (),
               .rd_dout          (lnk_fifo_dout[CW-1:0]),
@@ -782,7 +782,7 @@ module lumi_rx
                   .CHAOS(0),              // generates random full logic when set
                   .CTRLW(1),              // width of asic ctrl interface
                   .TESTW(1),              // width of asic test interface
-                  .TYPE("DEFAULT"))       // Pass through variable for hard macro
+                  .PROP("DEFAULT"))       // Pass through variable for hard macro
    req_syncfifo_i(// Outputs
                   .wr_full          (sync_fifo_full[0]),
                   .rd_dout          (sync_fifo_dout[IOW-1:0]),
@@ -810,7 +810,7 @@ module lumi_rx
                   .CHAOS(0),              // generates random full logic when set
                   .CTRLW(1),              // width of asic ctrl interface
                   .TESTW(1),              // width of asic test interface
-                  .TYPE("DEFAULT"))       // Pass through variable for hard macro
+                  .PROP("DEFAULT"))       // Pass through variable for hard macro
    resp_syncfifo_i(// Outputs
                    .wr_full          (sync_fifo_full[1]),
                    .rd_dout          (sync_fifo_dout[2*IOW-1:IOW]),
diff --git a/umi/lumi/rtl/lumi_tx.v b/umi/lumi/rtl/lumi_tx.v
index 5d942a9..6d74836 100644
--- a/umi/lumi/rtl/lumi_tx.v
+++ b/umi/lumi/rtl/lumi_tx.v
@@ -597,7 +597,7 @@ module lumi_tx
                   .CHAOS(0),         // generates random full logic when set
                   .CTRLW(1),         // width of asic ctrl interface
                   .TESTW(1),         // width of asic test interface
-                  .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                  .PROP("DEFAULT"))  // Pass through variable for hard macro
    phy_fifo_i(// Outputs
               .wr_full          (phy_fifo_full),
               .rd_dout          (phy_txdata[IOW-1:0]),
diff --git a/umi/umi/rtl/umi_mem_agent.v b/umi/umi/rtl/umi_mem_agent.v
index 3d9600c..0bca370 100644
--- a/umi/umi/rtl/umi_mem_agent.v
+++ b/umi/umi/rtl/umi_mem_agent.v
@@ -260,7 +260,7 @@ module umi_mem_agent
 
    la_spram #(.DW    (DW),               // Memory width
               .AW    ($clog2(RAMDEPTH)), // Address width (derived)
-              .TYPE  (SRAMTYPE),         // Pass through variable for hard macro
+              .PROP  (SRAMTYPE),         // Pass through variable for hard macro
               .CTRLW (CTRLW),            // Width of asic ctrl interface
               .TESTW (128)               // Width of asic test interface
               )
diff --git a/umi/utils/rtl/tl2umi_np.v b/umi/utils/rtl/tl2umi_np.v
index 2e40f0c..d4cfc5d 100644
--- a/umi/utils/rtl/tl2umi_np.v
+++ b/umi/utils/rtl/tl2umi_np.v
@@ -468,7 +468,7 @@ module tl2umi_np #(
     la_syncfifo #(
         .DW     (CW + AW + AW + DW),
         .DEPTH  (2),
-        .TYPE   ("DEFAULT")
+        .PROP   ("DEFAULT")
     ) tl2umi_req_fifo (
         .clk        (clk),
         .nreset     (nreset),