From befbb27ec54e541f0e13d3ac0794f3243fb9ca2a Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Tue, 30 Jul 2024 16:27:15 -0400 Subject: [PATCH] TYPE->PROP --- umi/lumi/rtl/lumi_rx.v | 10 +++++----- umi/lumi/rtl/lumi_tx.v | 2 +- umi/umi/rtl/umi_mem_agent.v | 2 +- umi/utils/rtl/tl2umi_np.v | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/umi/lumi/rtl/lumi_rx.v b/umi/lumi/rtl/lumi_rx.v index 5cf22fc..c36e756 100644 --- a/umi/lumi/rtl/lumi_rx.v +++ b/umi/lumi/rtl/lumi_rx.v @@ -550,7 +550,7 @@ module lumi_rx .CHAOS(0), // generates random full logic when set .CTRLW(1), // width of asic ctrl interface .TESTW(1), // width of asic test interface - .TYPE("DEFAULT")) // Pass through variable for hard macro + .PROP("DEFAULT")) // Pass through variable for hard macro req_fifo_i(// Outputs .wr_full (req_fifo_full[j]), .rd_dout (req_fifo_dout[j*RXFIFOW+:RXFIFOW]), @@ -598,7 +598,7 @@ module lumi_rx .CHAOS(0), // generates random full logic when set .CTRLW(1), // width of asic ctrl interface .TESTW(1), // width of asic test interface - .TYPE("DEFAULT")) // Pass through variable for hard macro + .PROP("DEFAULT")) // Pass through variable for hard macro resp_fifo_i(// Outputs .wr_full (resp_fifo_full[k]), .rd_dout (resp_fifo_dout[k*RXFIFOW+:RXFIFOW]), @@ -663,7 +663,7 @@ module lumi_rx .CHAOS(0), // generates random full logic when set .CTRLW(1), // width of asic ctrl interface .TESTW(1), // width of asic test interface - .TYPE("DEFAULT")) // Pass through variable for hard macro + .PROP("DEFAULT")) // Pass through variable for hard macro lnk_fifo_i(// Outputs .wr_full (), .rd_dout (lnk_fifo_dout[CW-1:0]), @@ -782,7 +782,7 @@ module lumi_rx .CHAOS(0), // generates random full logic when set .CTRLW(1), // width of asic ctrl interface .TESTW(1), // width of asic test interface - .TYPE("DEFAULT")) // Pass through variable for hard macro + .PROP("DEFAULT")) // Pass through variable for hard macro req_syncfifo_i(// Outputs .wr_full (sync_fifo_full[0]), .rd_dout (sync_fifo_dout[IOW-1:0]), @@ -810,7 +810,7 @@ module lumi_rx .CHAOS(0), // generates random full logic when set .CTRLW(1), // width of asic ctrl interface .TESTW(1), // width of asic test interface - .TYPE("DEFAULT")) // Pass through variable for hard macro + .PROP("DEFAULT")) // Pass through variable for hard macro resp_syncfifo_i(// Outputs .wr_full (sync_fifo_full[1]), .rd_dout (sync_fifo_dout[2*IOW-1:IOW]), diff --git a/umi/lumi/rtl/lumi_tx.v b/umi/lumi/rtl/lumi_tx.v index 5d942a9..6d74836 100644 --- a/umi/lumi/rtl/lumi_tx.v +++ b/umi/lumi/rtl/lumi_tx.v @@ -597,7 +597,7 @@ module lumi_tx .CHAOS(0), // generates random full logic when set .CTRLW(1), // width of asic ctrl interface .TESTW(1), // width of asic test interface - .TYPE("DEFAULT")) // Pass through variable for hard macro + .PROP("DEFAULT")) // Pass through variable for hard macro phy_fifo_i(// Outputs .wr_full (phy_fifo_full), .rd_dout (phy_txdata[IOW-1:0]), diff --git a/umi/umi/rtl/umi_mem_agent.v b/umi/umi/rtl/umi_mem_agent.v index 3d9600c..0bca370 100644 --- a/umi/umi/rtl/umi_mem_agent.v +++ b/umi/umi/rtl/umi_mem_agent.v @@ -260,7 +260,7 @@ module umi_mem_agent la_spram #(.DW (DW), // Memory width .AW ($clog2(RAMDEPTH)), // Address width (derived) - .TYPE (SRAMTYPE), // Pass through variable for hard macro + .PROP (SRAMTYPE), // Pass through variable for hard macro .CTRLW (CTRLW), // Width of asic ctrl interface .TESTW (128) // Width of asic test interface ) diff --git a/umi/utils/rtl/tl2umi_np.v b/umi/utils/rtl/tl2umi_np.v index 2e40f0c..d4cfc5d 100644 --- a/umi/utils/rtl/tl2umi_np.v +++ b/umi/utils/rtl/tl2umi_np.v @@ -468,7 +468,7 @@ module tl2umi_np #( la_syncfifo #( .DW (CW + AW + AW + DW), .DEPTH (2), - .TYPE ("DEFAULT") + .PROP ("DEFAULT") ) tl2umi_req_fifo ( .clk (clk), .nreset (nreset),