From 74c124e222ccf068a7a7822686dd5b955dc5c8de Mon Sep 17 00:00:00 2001 From: azaidy Date: Wed, 2 Oct 2024 23:09:25 -0400 Subject: [PATCH 1/3] Make performance counter names more descriptive and add comments --- umi/lumi/rtl/lumi.v | 140 ++++++++++++++++++------------------ umi/lumi/rtl/lumi_regmap.vh | 20 +++--- umi/lumi/rtl/lumi_regs.v | 30 ++++---- umi/lumi/rtl/lumi_tx.v | 35 +++++---- 4 files changed, 116 insertions(+), 109 deletions(-) diff --git a/umi/lumi/rtl/lumi.v b/umi/lumi/rtl/lumi.v index aeb295e..9be21be 100644 --- a/umi/lumi/rtl/lumi.v +++ b/umi/lumi/rtl/lumi.v @@ -141,10 +141,10 @@ module lumi wire [7:0] csr_rxiowidth; wire csr_txcrdt_en; wire [15:0] csr_txcrdt_intrvl; - wire [31:0] csr_req_txcrdt_navail; - wire [31:0] csr_resp_txcrdt_navail; - wire [31:0] csr_req_txcrdt_avail; - wire [31:0] csr_resp_txcrdt_avail; + wire [31:0] csr_req_txcrdt_navail_cycles; + wire [31:0] csr_resp_txcrdt_navail_cycles; + wire [31:0] csr_req_txcrdt_avail_cycles; + wire [31:0] csr_resp_txcrdt_avail_cycles; wire csr_txen; wire [7:0] csr_txiowidth; wire [CW-1:0] fifo2cb_cmd; @@ -196,39 +196,39 @@ module lumi ) lumi_regs(/*AUTOINST*/ // Outputs - .udev_req_ready (cb2regs_ready), // Templated - .udev_resp_valid (regs2cb_valid), // Templated - .udev_resp_cmd (regs2cb_cmd[CW-1:0]), // Templated - .udev_resp_dstaddr (regs2cb_dstaddr[AW-1:0]), // Templated - .udev_resp_srcaddr (regs2cb_srcaddr[AW-1:0]), // Templated - .udev_resp_data (regs2cb_data[RW-1:0]), // Templated - .host_linkactive (host_linkactive), - .csr_arbmode (), // Templated - .csr_txen (csr_txen), - .csr_txcrdt_en (csr_txcrdt_en), - .csr_txiowidth (csr_txiowidth[7:0]), - .csr_rxen (csr_rxen), - .csr_rxiowidth (csr_rxiowidth[7:0]), - .csr_txcrdt_intrvl (csr_txcrdt_intrvl[15:0]), - .csr_rxcrdt_req_init (csr_rxcrdt_req_init[15:0]), - .csr_rxcrdt_resp_init (csr_rxcrdt_resp_init[15:0]), + .udev_req_ready (cb2regs_ready), // Templated + .udev_resp_valid (regs2cb_valid), // Templated + .udev_resp_cmd (regs2cb_cmd[CW-1:0]), // Templated + .udev_resp_dstaddr (regs2cb_dstaddr[AW-1:0]), // Templated + .udev_resp_srcaddr (regs2cb_srcaddr[AW-1:0]), // Templated + .udev_resp_data (regs2cb_data[RW-1:0]), // Templated + .host_linkactive (host_linkactive), + .csr_arbmode (), // Templated + .csr_txen (csr_txen), + .csr_txcrdt_en (csr_txcrdt_en), + .csr_txiowidth (csr_txiowidth[7:0]), + .csr_rxen (csr_rxen), + .csr_rxiowidth (csr_rxiowidth[7:0]), + .csr_txcrdt_intrvl (csr_txcrdt_intrvl[15:0]), + .csr_rxcrdt_req_init (csr_rxcrdt_req_init[15:0]), + .csr_rxcrdt_resp_init (csr_rxcrdt_resp_init[15:0]), // Inputs - .devicemode (devicemode), - .deviceready (deviceready), - .nreset (nreset), - .clk (clk), - .udev_req_valid (cb2regs_valid), // Templated - .udev_req_cmd (cb2regs_cmd[CW-1:0]), // Templated - .udev_req_dstaddr (cb2regs_dstaddr[AW-1:0]), // Templated - .udev_req_srcaddr (cb2regs_srcaddr[AW-1:0]), // Templated - .udev_req_data (cb2regs_data[RW-1:0]), // Templated - .udev_resp_ready (regs2cb_ready), // Templated - .phy_linkactive (phy_linkactive), - .phy_iow (phy_iow[7:0]), - .csr_req_txcrdt_navail (csr_req_txcrdt_navail), - .csr_resp_txcrdt_navail (csr_resp_txcrdt_navail), - .csr_req_txcrdt_avail (csr_req_txcrdt_avail), - .csr_resp_txcrdt_avail (csr_resp_txcrdt_avail)); + .devicemode (devicemode), + .deviceready (deviceready), + .nreset (nreset), + .clk (clk), + .udev_req_valid (cb2regs_valid), // Templated + .udev_req_cmd (cb2regs_cmd[CW-1:0]), // Templated + .udev_req_dstaddr (cb2regs_dstaddr[AW-1:0]), // Templated + .udev_req_srcaddr (cb2regs_srcaddr[AW-1:0]), // Templated + .udev_req_data (cb2regs_data[RW-1:0]), // Templated + .udev_resp_ready (regs2cb_ready), // Templated + .phy_linkactive (phy_linkactive), + .phy_iow (phy_iow[7:0]), + .csr_req_txcrdt_navail_cycles (csr_req_txcrdt_navail_cycles), + .csr_resp_txcrdt_navail_cycles (csr_resp_txcrdt_navail_cycles), + .csr_req_txcrdt_avail_cycles (csr_req_txcrdt_avail_cycles), + .csr_resp_txcrdt_avail_cycles (csr_resp_txcrdt_avail_cycles)); //########################### // Register Crossbar @@ -468,41 +468,41 @@ module lumi .DW(DW)) lumi_tx(/*AUTOINST*/ // Outputs - .umi_req_in_ready (udev_req_ready), // Templated - .umi_resp_in_ready (uhost_resp_ready), // Templated - .phy_txdata (phy_txdata[IOW-1:0]), - .phy_txvld (phy_txvld), - .csr_req_crdt_navail (csr_req_txcrdt_navail), // Templated - .csr_resp_crdt_navail(csr_resp_txcrdt_navail), // Templated - .csr_req_crdt_avail (csr_req_txcrdt_avail), // Templated - .csr_resp_crdt_avail (csr_resp_txcrdt_avail), // Templated + .umi_req_in_ready (udev_req_ready), // Templated + .umi_resp_in_ready (uhost_resp_ready), // Templated + .phy_txdata (phy_txdata[IOW-1:0]), + .phy_txvld (phy_txvld), + .csr_req_crdt_navail_cycles (csr_req_txcrdt_navail_cycles), // Templated + .csr_resp_crdt_navail_cycles(csr_resp_txcrdt_navail_cycles), // Templated + .csr_req_crdt_avail_cycles (csr_req_txcrdt_avail_cycles), // Templated + .csr_resp_crdt_avail_cycles (csr_resp_txcrdt_avail_cycles), // Templated // Inputs - .clk (clk), - .nreset (nreset), - .csr_en (csr_txen), // Templated - .csr_crdt_en (csr_txcrdt_en), // Templated - .csr_iowidth (csr_txiowidth[7:0]), // Templated - .vss (vss), - .vdd (vdd), - .umi_req_in_valid (udev_req_valid), // Templated - .umi_req_in_cmd (udev_req_cmd[CW-1:0]), // Templated - .umi_req_in_dstaddr (udev_req_dstaddr[AW-1:0]), // Templated - .umi_req_in_srcaddr (udev_req_srcaddr[AW-1:0]), // Templated - .umi_req_in_data (udev_req_data[DW-1:0]), // Templated - .umi_resp_in_valid (uhost_resp_valid), // Templated - .umi_resp_in_cmd (uhost_resp_cmd[CW-1:0]), // Templated - .umi_resp_in_dstaddr (uhost_resp_dstaddr[AW-1:0]), // Templated - .umi_resp_in_srcaddr (uhost_resp_srcaddr[AW-1:0]), // Templated - .umi_resp_in_data (uhost_resp_data[DW-1:0]), // Templated - .ioclk (txclk), // Templated - .ionreset (txnreset), // Templated - .csr_crdt_intrvl (csr_txcrdt_intrvl[15:0]), // Templated - .rmt_crdt_req (rmt_crdt_req[15:0]), - .rmt_crdt_resp (rmt_crdt_resp[15:0]), - .loc_crdt_req (loc_crdt_req[15:0]), - .loc_crdt_resp (loc_crdt_resp[15:0]), - .loc_crdt_init (loc_crdt_init[1:0]), - .rmt_crdt_init (rmt_crdt_init[1:0])); + .clk (clk), + .nreset (nreset), + .csr_en (csr_txen), // Templated + .csr_crdt_en (csr_txcrdt_en), // Templated + .csr_iowidth (csr_txiowidth[7:0]), // Templated + .vss (vss), + .vdd (vdd), + .umi_req_in_valid (udev_req_valid), // Templated + .umi_req_in_cmd (udev_req_cmd[CW-1:0]), // Templated + .umi_req_in_dstaddr (udev_req_dstaddr[AW-1:0]), // Templated + .umi_req_in_srcaddr (udev_req_srcaddr[AW-1:0]), // Templated + .umi_req_in_data (udev_req_data[DW-1:0]), // Templated + .umi_resp_in_valid (uhost_resp_valid), // Templated + .umi_resp_in_cmd (uhost_resp_cmd[CW-1:0]), // Templated + .umi_resp_in_dstaddr (uhost_resp_dstaddr[AW-1:0]), // Templated + .umi_resp_in_srcaddr (uhost_resp_srcaddr[AW-1:0]), // Templated + .umi_resp_in_data (uhost_resp_data[DW-1:0]), // Templated + .ioclk (txclk), // Templated + .ionreset (txnreset), // Templated + .csr_crdt_intrvl (csr_txcrdt_intrvl[15:0]), // Templated + .rmt_crdt_req (rmt_crdt_req[15:0]), + .rmt_crdt_resp (rmt_crdt_resp[15:0]), + .loc_crdt_req (loc_crdt_req[15:0]), + .loc_crdt_resp (loc_crdt_resp[15:0]), + .loc_crdt_init (loc_crdt_init[1:0]), + .rmt_crdt_init (rmt_crdt_init[1:0])); endmodule // clink // Local Variables: diff --git a/umi/lumi/rtl/lumi_regmap.vh b/umi/lumi/rtl/lumi_regmap.vh index 83c18b1..b6b4566 100644 --- a/umi/lumi/rtl/lumi_regmap.vh +++ b/umi/lumi/rtl/lumi_regmap.vh @@ -21,13 +21,13 @@ ******************************************************************************/ // registers (addr[7:0]), 32bit aligned -localparam LUMI_CTRL = 8'h00; // device configuration -localparam LUMI_STATUS = 8'h04; // device status -localparam LUMI_TXMODE = 8'h10; // tx operating mode -localparam LUMI_RXMODE = 8'h14; // rx operating mode -localparam LUMI_CRDTINIT = 8'h20; // Credit init value -localparam LUMI_CRDTINTRVL = 8'h24; // Credir update interval -localparam LUMI_REQCRDTNAVAIL = 8'h30; // Req credit not available -localparam LUMI_RESPCRDTNAVAIL = 8'h34; // Resp credit not available -localparam LUMI_REQCRDTAVAIL = 8'h38; // Req credit available -localparam LUMI_RESPCRDTAVAIL = 8'h3C; // Resp credit available +localparam LUMI_CTRL = 8'h00; // device configuration +localparam LUMI_STATUS = 8'h04; // device status +localparam LUMI_TXMODE = 8'h10; // tx operating mode +localparam LUMI_RXMODE = 8'h14; // rx operating mode +localparam LUMI_CRDTINIT = 8'h20; // Credit init value +localparam LUMI_CRDTINTRVL = 8'h24; // Credir update interval +localparam LUMI_REQCRDTNAVAILCYC = 8'h30; // Cycle count of outstanding request transaction and credits are not available +localparam LUMI_RESPCRDTNAVAILCYC = 8'h34; // Cycle count of outstanding response transaction and credits are not available +localparam LUMI_REQCRDTAVAILCYC = 8'h38; // Cycle count of outstanding request transaction and credits are available +localparam LUMI_RESPCRDTAVAILCYC = 8'h3C; // Cycle count of outstanding response transaction and credits are available diff --git a/umi/lumi/rtl/lumi_regs.v b/umi/lumi/rtl/lumi_regs.v index a97d26c..d554399 100644 --- a/umi/lumi/rtl/lumi_regs.v +++ b/umi/lumi/rtl/lumi_regs.v @@ -74,10 +74,12 @@ module lumi_regs output [15:0] csr_rxcrdt_req_init, output [15:0] csr_rxcrdt_resp_init, // performance counters - input [31:0] csr_req_txcrdt_navail, - input [31:0] csr_resp_txcrdt_navail, - input [31:0] csr_req_txcrdt_avail, - input [31:0] csr_resp_txcrdt_avail + // cycle counters indicating if credits are available or not for an + // outstanding transaction + input [31:0] csr_req_txcrdt_navail_cycles, + input [31:0] csr_resp_txcrdt_navail_cycles, + input [31:0] csr_req_txcrdt_avail_cycles, + input [31:0] csr_resp_txcrdt_avail_cycles ); `include "lumi_regmap.vh" @@ -304,16 +306,16 @@ module lumi_regs else if (reg_read) case (reg_addr[7:2]) - LUMI_CTRL[7:2] : reg_rddata[RW-1:0] <= ctrl_reg[RW-1:0]; - LUMI_STATUS[7:2] : reg_rddata[RW-1:0] <= status_reg[RW-1:0]; - LUMI_TXMODE[7:2] : reg_rddata[RW-1:0] <= txmode_reg[RW-1:0]; - LUMI_RXMODE[7:2] : reg_rddata[RW-1:0] <= rxmode_reg[RW-1:0]; - LUMI_CRDTINIT[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},rxcrdt_init_reg[31:0]}; - LUMI_CRDTINTRVL[7:2] : reg_rddata[RW-1:0] <= {{RW-16{1'b0}},txcrdt_intrvl_reg[15:0]}; - LUMI_REQCRDTNAVAIL[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_navail[31:0]}; - LUMI_RESPCRDTNAVAIL[7:2]: reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_navail[31:0]}; - LUMI_REQCRDTAVAIL[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_avail[31:0]}; - LUMI_RESPCRDTAVAIL[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_avail[31:0]}; + LUMI_CTRL[7:2] : reg_rddata[RW-1:0] <= ctrl_reg[RW-1:0]; + LUMI_STATUS[7:2] : reg_rddata[RW-1:0] <= status_reg[RW-1:0]; + LUMI_TXMODE[7:2] : reg_rddata[RW-1:0] <= txmode_reg[RW-1:0]; + LUMI_RXMODE[7:2] : reg_rddata[RW-1:0] <= rxmode_reg[RW-1:0]; + LUMI_CRDTINIT[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},rxcrdt_init_reg[31:0]}; + LUMI_CRDTINTRVL[7:2] : reg_rddata[RW-1:0] <= {{RW-16{1'b0}},txcrdt_intrvl_reg[15:0]}; + LUMI_REQCRDTNAVAILCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_navail_cycles[31:0]}; + LUMI_RESPCRDTNAVAILCYC[7:2]: reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_navail_cycles[31:0]}; + LUMI_REQCRDTAVAILCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_avail_cycles[31:0]}; + LUMI_RESPCRDTAVAILCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_avail_cycles[31:0]}; default: reg_rddata[RW-1:0] <= 'b0; endcase diff --git a/umi/lumi/rtl/lumi_tx.v b/umi/lumi/rtl/lumi_tx.v index 1cca603..76f60e1 100644 --- a/umi/lumi/rtl/lumi_tx.v +++ b/umi/lumi/rtl/lumi_tx.v @@ -55,11 +55,14 @@ module lumi_tx output phy_txvld, // valid signal to the phy input ioclk, input ionreset, + // performance counters + // cycle counters indicating if credits are available or not for an + // outstanding transaction + output reg [31:0] csr_req_crdt_navail_cycles, + output reg [31:0] csr_resp_crdt_navail_cycles, + output reg [31:0] csr_req_crdt_avail_cycles, + output reg [31:0] csr_resp_crdt_avail_cycles, // Credit interface - output reg [31:0] csr_req_crdt_navail, - output reg [31:0] csr_resp_crdt_navail, - output reg [31:0] csr_req_crdt_avail, - output reg [31:0] csr_resp_crdt_avail, input [15:0] csr_crdt_intrvl, input [15:0] rmt_crdt_req, input [15:0] rmt_crdt_resp, @@ -209,30 +212,32 @@ module lumi_tx always @(posedge clk or negedge nreset) if (~nreset) - csr_req_crdt_navail[31:0] <= 'b0; + csr_req_crdt_navail_cycles[31:0] <= 'b0; else - csr_req_crdt_navail[31:0] <= csr_req_crdt_navail[31:0] + - {31'h0, (umi_req_in_valid & phy_txrdy & ~rxready[0] & - ~umi_resp_in_gated)}; + csr_req_crdt_navail_cycles[31:0] <= csr_req_crdt_navail_cycles[31:0] + + {31'h0, (umi_req_in_valid & phy_txrdy & ~rxready[0] & + ~umi_resp_in_gated)}; always @(posedge clk or negedge nreset) if (~nreset) - csr_resp_crdt_navail[31:0] <= 'b0; + csr_resp_crdt_navail_cycles[31:0] <= 'b0; else - csr_resp_crdt_navail[31:0] <= csr_resp_crdt_navail[31:0] + - {31'h0, (umi_resp_in_valid & phy_txrdy & ~rxready[1])}; + csr_resp_crdt_navail_cycles[31:0] <= csr_resp_crdt_navail_cycles[31:0] + + {31'h0, (umi_resp_in_valid & phy_txrdy & ~rxready[1])}; always @(posedge clk or negedge nreset) if (~nreset) - csr_req_crdt_avail[31:0] <= 'b0; + csr_req_crdt_avail_cycles[31:0] <= 'b0; else - csr_req_crdt_avail[31:0] <= csr_req_crdt_avail[31:0] + {31'h0, umi_req_in_ready}; + csr_req_crdt_avail_cycles[31:0] <= csr_req_crdt_avail_cycles[31:0] + + {31'h0, umi_req_in_ready}; always @(posedge clk or negedge nreset) if (~nreset) - csr_resp_crdt_avail[31:0] <= 'b0; + csr_resp_crdt_avail_cycles[31:0] <= 'b0; else - csr_resp_crdt_avail[31:0] <= csr_resp_crdt_avail[31:0] + {31'h0, umi_resp_in_ready}; + csr_resp_crdt_avail_cycles[31:0] <= csr_resp_crdt_avail_cycles[31:0] + + {31'h0, umi_resp_in_ready}; //######################################## //# Credit message generation for the remote side From 1208827c470fc65618e65f545136ab754f6bacca Mon Sep 17 00:00:00 2001 From: azaidy Date: Thu, 3 Oct 2024 16:14:55 -0400 Subject: [PATCH 2/3] Rename performance counters to stall and active cycles --- umi/lumi/rtl/lumi.v | 84 ++++++++++++++++++------------------- umi/lumi/rtl/lumi_regmap.vh | 8 ++-- umi/lumi/rtl/lumi_regs.v | 16 +++---- umi/lumi/rtl/lumi_tx.v | 34 +++++++-------- 4 files changed, 71 insertions(+), 71 deletions(-) diff --git a/umi/lumi/rtl/lumi.v b/umi/lumi/rtl/lumi.v index 9be21be..30e1cd0 100644 --- a/umi/lumi/rtl/lumi.v +++ b/umi/lumi/rtl/lumi.v @@ -141,10 +141,10 @@ module lumi wire [7:0] csr_rxiowidth; wire csr_txcrdt_en; wire [15:0] csr_txcrdt_intrvl; - wire [31:0] csr_req_txcrdt_navail_cycles; - wire [31:0] csr_resp_txcrdt_navail_cycles; - wire [31:0] csr_req_txcrdt_avail_cycles; - wire [31:0] csr_resp_txcrdt_avail_cycles; + wire [31:0] csr_req_txcrdt_stall_cycles; + wire [31:0] csr_resp_txcrdt_stall_cycles; + wire [31:0] csr_req_txcrdt_active_cycles; + wire [31:0] csr_resp_txcrdt_active_cycles; wire csr_txen; wire [7:0] csr_txiowidth; wire [CW-1:0] fifo2cb_cmd; @@ -225,10 +225,10 @@ module lumi .udev_resp_ready (regs2cb_ready), // Templated .phy_linkactive (phy_linkactive), .phy_iow (phy_iow[7:0]), - .csr_req_txcrdt_navail_cycles (csr_req_txcrdt_navail_cycles), - .csr_resp_txcrdt_navail_cycles (csr_resp_txcrdt_navail_cycles), - .csr_req_txcrdt_avail_cycles (csr_req_txcrdt_avail_cycles), - .csr_resp_txcrdt_avail_cycles (csr_resp_txcrdt_avail_cycles)); + .csr_req_txcrdt_stall_cycles (csr_req_txcrdt_stall_cycles), + .csr_resp_txcrdt_stall_cycles (csr_resp_txcrdt_stall_cycles), + .csr_req_txcrdt_active_cycles (csr_req_txcrdt_active_cycles), + .csr_resp_txcrdt_active_cycles (csr_resp_txcrdt_active_cycles)); //########################### // Register Crossbar @@ -468,41 +468,41 @@ module lumi .DW(DW)) lumi_tx(/*AUTOINST*/ // Outputs - .umi_req_in_ready (udev_req_ready), // Templated - .umi_resp_in_ready (uhost_resp_ready), // Templated - .phy_txdata (phy_txdata[IOW-1:0]), - .phy_txvld (phy_txvld), - .csr_req_crdt_navail_cycles (csr_req_txcrdt_navail_cycles), // Templated - .csr_resp_crdt_navail_cycles(csr_resp_txcrdt_navail_cycles), // Templated - .csr_req_crdt_avail_cycles (csr_req_txcrdt_avail_cycles), // Templated - .csr_resp_crdt_avail_cycles (csr_resp_txcrdt_avail_cycles), // Templated + .umi_req_in_ready (udev_req_ready), // Templated + .umi_resp_in_ready (uhost_resp_ready), // Templated + .phy_txdata (phy_txdata[IOW-1:0]), + .phy_txvld (phy_txvld), + .csr_req_crdt_stall_cycles (csr_req_txcrdt_stall_cycles), // Templated + .csr_resp_crdt_stall_cycles (csr_resp_txcrdt_stall_cycles), // Templated + .csr_req_crdt_active_cycles (csr_req_txcrdt_active_cycles), // Templated + .csr_resp_crdt_active_cycles (csr_resp_txcrdt_active_cycles), // Templated // Inputs - .clk (clk), - .nreset (nreset), - .csr_en (csr_txen), // Templated - .csr_crdt_en (csr_txcrdt_en), // Templated - .csr_iowidth (csr_txiowidth[7:0]), // Templated - .vss (vss), - .vdd (vdd), - .umi_req_in_valid (udev_req_valid), // Templated - .umi_req_in_cmd (udev_req_cmd[CW-1:0]), // Templated - .umi_req_in_dstaddr (udev_req_dstaddr[AW-1:0]), // Templated - .umi_req_in_srcaddr (udev_req_srcaddr[AW-1:0]), // Templated - .umi_req_in_data (udev_req_data[DW-1:0]), // Templated - .umi_resp_in_valid (uhost_resp_valid), // Templated - .umi_resp_in_cmd (uhost_resp_cmd[CW-1:0]), // Templated - .umi_resp_in_dstaddr (uhost_resp_dstaddr[AW-1:0]), // Templated - .umi_resp_in_srcaddr (uhost_resp_srcaddr[AW-1:0]), // Templated - .umi_resp_in_data (uhost_resp_data[DW-1:0]), // Templated - .ioclk (txclk), // Templated - .ionreset (txnreset), // Templated - .csr_crdt_intrvl (csr_txcrdt_intrvl[15:0]), // Templated - .rmt_crdt_req (rmt_crdt_req[15:0]), - .rmt_crdt_resp (rmt_crdt_resp[15:0]), - .loc_crdt_req (loc_crdt_req[15:0]), - .loc_crdt_resp (loc_crdt_resp[15:0]), - .loc_crdt_init (loc_crdt_init[1:0]), - .rmt_crdt_init (rmt_crdt_init[1:0])); + .clk (clk), + .nreset (nreset), + .csr_en (csr_txen), // Templated + .csr_crdt_en (csr_txcrdt_en), // Templated + .csr_iowidth (csr_txiowidth[7:0]), // Templated + .vss (vss), + .vdd (vdd), + .umi_req_in_valid (udev_req_valid), // Templated + .umi_req_in_cmd (udev_req_cmd[CW-1:0]), // Templated + .umi_req_in_dstaddr (udev_req_dstaddr[AW-1:0]), // Templated + .umi_req_in_srcaddr (udev_req_srcaddr[AW-1:0]), // Templated + .umi_req_in_data (udev_req_data[DW-1:0]), // Templated + .umi_resp_in_valid (uhost_resp_valid), // Templated + .umi_resp_in_cmd (uhost_resp_cmd[CW-1:0]), // Templated + .umi_resp_in_dstaddr (uhost_resp_dstaddr[AW-1:0]), // Templated + .umi_resp_in_srcaddr (uhost_resp_srcaddr[AW-1:0]), // Templated + .umi_resp_in_data (uhost_resp_data[DW-1:0]), // Templated + .ioclk (txclk), // Templated + .ionreset (txnreset), // Templated + .csr_crdt_intrvl (csr_txcrdt_intrvl[15:0]), // Templated + .rmt_crdt_req (rmt_crdt_req[15:0]), + .rmt_crdt_resp (rmt_crdt_resp[15:0]), + .loc_crdt_req (loc_crdt_req[15:0]), + .loc_crdt_resp (loc_crdt_resp[15:0]), + .loc_crdt_init (loc_crdt_init[1:0]), + .rmt_crdt_init (rmt_crdt_init[1:0])); endmodule // clink // Local Variables: diff --git a/umi/lumi/rtl/lumi_regmap.vh b/umi/lumi/rtl/lumi_regmap.vh index b6b4566..ea94e13 100644 --- a/umi/lumi/rtl/lumi_regmap.vh +++ b/umi/lumi/rtl/lumi_regmap.vh @@ -27,7 +27,7 @@ localparam LUMI_TXMODE = 8'h10; // tx operating mode localparam LUMI_RXMODE = 8'h14; // rx operating mode localparam LUMI_CRDTINIT = 8'h20; // Credit init value localparam LUMI_CRDTINTRVL = 8'h24; // Credir update interval -localparam LUMI_REQCRDTNAVAILCYC = 8'h30; // Cycle count of outstanding request transaction and credits are not available -localparam LUMI_RESPCRDTNAVAILCYC = 8'h34; // Cycle count of outstanding response transaction and credits are not available -localparam LUMI_REQCRDTAVAILCYC = 8'h38; // Cycle count of outstanding request transaction and credits are available -localparam LUMI_RESPCRDTAVAILCYC = 8'h3C; // Cycle count of outstanding response transaction and credits are available +localparam LUMI_REQCRDTSTALLCYC = 8'h30; // Cycle count of outstanding request transaction and credits are not available +localparam LUMI_RESPCRDTSTALLCYC = 8'h34; // Cycle count of outstanding response transaction and credits are not available +localparam LUMI_REQCRDTACTIVECYC = 8'h38; // Cycle count of outstanding request transaction and credits are available +localparam LUMI_RESPCRDTACTIVECYC = 8'h3C; // Cycle count of outstanding response transaction and credits are available diff --git a/umi/lumi/rtl/lumi_regs.v b/umi/lumi/rtl/lumi_regs.v index d554399..dc0a9c3 100644 --- a/umi/lumi/rtl/lumi_regs.v +++ b/umi/lumi/rtl/lumi_regs.v @@ -76,10 +76,10 @@ module lumi_regs // performance counters // cycle counters indicating if credits are available or not for an // outstanding transaction - input [31:0] csr_req_txcrdt_navail_cycles, - input [31:0] csr_resp_txcrdt_navail_cycles, - input [31:0] csr_req_txcrdt_avail_cycles, - input [31:0] csr_resp_txcrdt_avail_cycles + input [31:0] csr_req_txcrdt_stall_cycles, + input [31:0] csr_resp_txcrdt_stall_cycles, + input [31:0] csr_req_txcrdt_active_cycles, + input [31:0] csr_resp_txcrdt_active_cycles ); `include "lumi_regmap.vh" @@ -312,10 +312,10 @@ module lumi_regs LUMI_RXMODE[7:2] : reg_rddata[RW-1:0] <= rxmode_reg[RW-1:0]; LUMI_CRDTINIT[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},rxcrdt_init_reg[31:0]}; LUMI_CRDTINTRVL[7:2] : reg_rddata[RW-1:0] <= {{RW-16{1'b0}},txcrdt_intrvl_reg[15:0]}; - LUMI_REQCRDTNAVAILCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_navail_cycles[31:0]}; - LUMI_RESPCRDTNAVAILCYC[7:2]: reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_navail_cycles[31:0]}; - LUMI_REQCRDTAVAILCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_avail_cycles[31:0]}; - LUMI_RESPCRDTAVAILCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_avail_cycles[31:0]}; + LUMI_REQCRDTSTALLCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_stall_cycles[31:0]}; + LUMI_RESPCRDTSTALLCYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_stall_cycles[31:0]}; + LUMI_REQCRDTACTIVECYC[7:2] : reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_req_txcrdt_active_cycles[31:0]}; + LUMI_RESPCRDTACTIVECYC[7:2]: reg_rddata[RW-1:0] <= {{RW-32{1'b0}},csr_resp_txcrdt_active_cycles[31:0]}; default: reg_rddata[RW-1:0] <= 'b0; endcase diff --git a/umi/lumi/rtl/lumi_tx.v b/umi/lumi/rtl/lumi_tx.v index 76f60e1..c683c65 100644 --- a/umi/lumi/rtl/lumi_tx.v +++ b/umi/lumi/rtl/lumi_tx.v @@ -58,10 +58,10 @@ module lumi_tx // performance counters // cycle counters indicating if credits are available or not for an // outstanding transaction - output reg [31:0] csr_req_crdt_navail_cycles, - output reg [31:0] csr_resp_crdt_navail_cycles, - output reg [31:0] csr_req_crdt_avail_cycles, - output reg [31:0] csr_resp_crdt_avail_cycles, + output reg [31:0] csr_req_crdt_stall_cycles, + output reg [31:0] csr_resp_crdt_stall_cycles, + output reg [31:0] csr_req_crdt_active_cycles, + output reg [31:0] csr_resp_crdt_active_cycles, // Credit interface input [15:0] csr_crdt_intrvl, input [15:0] rmt_crdt_req, @@ -212,32 +212,32 @@ module lumi_tx always @(posedge clk or negedge nreset) if (~nreset) - csr_req_crdt_navail_cycles[31:0] <= 'b0; + csr_req_crdt_stall_cycles[31:0] <= 'b0; else - csr_req_crdt_navail_cycles[31:0] <= csr_req_crdt_navail_cycles[31:0] + - {31'h0, (umi_req_in_valid & phy_txrdy & ~rxready[0] & - ~umi_resp_in_gated)}; + csr_req_crdt_stall_cycles[31:0] <= csr_req_crdt_stall_cycles[31:0] + + {31'h0, (umi_req_in_valid & phy_txrdy & ~rxready[0] & + ~umi_resp_in_gated)}; always @(posedge clk or negedge nreset) if (~nreset) - csr_resp_crdt_navail_cycles[31:0] <= 'b0; + csr_resp_crdt_stall_cycles[31:0] <= 'b0; else - csr_resp_crdt_navail_cycles[31:0] <= csr_resp_crdt_navail_cycles[31:0] + - {31'h0, (umi_resp_in_valid & phy_txrdy & ~rxready[1])}; + csr_resp_crdt_stall_cycles[31:0] <= csr_resp_crdt_stall_cycles[31:0] + + {31'h0, (umi_resp_in_valid & phy_txrdy & ~rxready[1])}; always @(posedge clk or negedge nreset) if (~nreset) - csr_req_crdt_avail_cycles[31:0] <= 'b0; + csr_req_crdt_active_cycles[31:0] <= 'b0; else - csr_req_crdt_avail_cycles[31:0] <= csr_req_crdt_avail_cycles[31:0] + - {31'h0, umi_req_in_ready}; + csr_req_crdt_active_cycles[31:0] <= csr_req_crdt_active_cycles[31:0] + + {31'h0, umi_req_in_ready}; always @(posedge clk or negedge nreset) if (~nreset) - csr_resp_crdt_avail_cycles[31:0] <= 'b0; + csr_resp_crdt_active_cycles[31:0] <= 'b0; else - csr_resp_crdt_avail_cycles[31:0] <= csr_resp_crdt_avail_cycles[31:0] + - {31'h0, umi_resp_in_ready}; + csr_resp_crdt_active_cycles[31:0] <= csr_resp_crdt_active_cycles[31:0] + + {31'h0, umi_resp_in_ready}; //######################################## //# Credit message generation for the remote side From 5fc55b71b6e7ec29115995d11cbfe6da66a694cf Mon Sep 17 00:00:00 2001 From: azaidy Date: Thu, 3 Oct 2024 16:26:42 -0400 Subject: [PATCH 3/3] Minor typo fix --- umi/lumi/rtl/lumi_regmap.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/umi/lumi/rtl/lumi_regmap.vh b/umi/lumi/rtl/lumi_regmap.vh index ea94e13..8c8aa54 100644 --- a/umi/lumi/rtl/lumi_regmap.vh +++ b/umi/lumi/rtl/lumi_regmap.vh @@ -26,7 +26,7 @@ localparam LUMI_STATUS = 8'h04; // device status localparam LUMI_TXMODE = 8'h10; // tx operating mode localparam LUMI_RXMODE = 8'h14; // rx operating mode localparam LUMI_CRDTINIT = 8'h20; // Credit init value -localparam LUMI_CRDTINTRVL = 8'h24; // Credir update interval +localparam LUMI_CRDTINTRVL = 8'h24; // Credit update interval localparam LUMI_REQCRDTSTALLCYC = 8'h30; // Cycle count of outstanding request transaction and credits are not available localparam LUMI_RESPCRDTSTALLCYC = 8'h34; // Cycle count of outstanding response transaction and credits are not available localparam LUMI_REQCRDTACTIVECYC = 8'h38; // Cycle count of outstanding request transaction and credits are available