From 3a7b2ffc1e3c57fc71b258888b41be3ec5755777 Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Fri, 1 Mar 2024 11:08:54 -0500
Subject: [PATCH 1/8] Added AXI4-Lite to UMI converter

---
 utils/rtl/axilite2umi.v             |  315 ++
 utils/testbench/buffer_axilite.memh | 4098 +++++++++++++++++++++++++++
 utils/testbench/build_local.sh      |   15 +-
 utils/testbench/tb_axilite2umi.v    |  363 +++
 4 files changed, 4784 insertions(+), 7 deletions(-)
 create mode 100644 utils/rtl/axilite2umi.v
 create mode 100644 utils/testbench/buffer_axilite.memh
 create mode 100644 utils/testbench/tb_axilite2umi.v

diff --git a/utils/rtl/axilite2umi.v b/utils/rtl/axilite2umi.v
new file mode 100644
index 0000000..fcb2ee7
--- /dev/null
+++ b/utils/rtl/axilite2umi.v
@@ -0,0 +1,315 @@
+/*******************************************************************************
+ * Copyright 2023 Zero ASIC Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----
+ *
+ * Documentation:
+ * - AXI4-Lite to UMI converter
+ *
+ ******************************************************************************/
+
+`default_nettype wire
+
+module axilite2umi #(
+    parameter CW    = 32,   // command width
+    parameter AW    = 64,   // address width
+    parameter DW    = 64,   // umi packet width
+    parameter IDW   = 16    // brick ID width
+)
+(
+    input               clk,
+    input               nreset,
+    input  [IDW-1:0]    chipid,
+    input  [15:0]       local_routing,
+
+    // AXI4Lite Interface
+    input  [AW-1:0]     axi_awaddr,
+    input  [2:0]        axi_awprot,
+    input               axi_awvalid,
+    output              axi_awready,
+
+    input  [DW-1:0]     axi_wdata,
+    input  [(DW/8)-1:0] axi_wstrb,
+    input               axi_wvalid,
+    output              axi_wready,
+
+    output [1:0]        axi_bresp,
+    output              axi_bvalid,
+    input               axi_bready,
+
+    input  [AW-1:0]     axi_araddr,
+    input  [2:0]        axi_arprot,
+    input               axi_arvalid,
+    output              axi_arready,
+
+    output [DW-1:0]     axi_rdata,
+    output [1:0]        axi_rresp,
+    output              axi_rvalid,
+    input               axi_rready,
+
+    // Host port (per clink)
+    output              uhost_req_valid,
+    output [CW-1:0]     uhost_req_cmd,
+    output [AW-1:0]     uhost_req_dstaddr,
+    output [AW-1:0]     uhost_req_srcaddr,
+    output [DW-1:0]     uhost_req_data,
+    input               uhost_req_ready,
+
+    input               uhost_resp_valid,
+    input  [CW-1:0]     uhost_resp_cmd,
+    input  [AW-1:0]     uhost_resp_dstaddr,
+    input  [AW-1:0]     uhost_resp_srcaddr,
+    input  [DW-1:0]     uhost_resp_data,
+    output              uhost_resp_ready
+);
+
+    `include "umi_messages.vh"
+
+    localparam DWLOG = $clog2(DW/8);
+
+    // Additional UMI signals
+    wire [4:0]      umi_req_cmd_opcode;
+    wire [7:0]      umi_req_cmd_len;
+    wire [1:0]      umi_req_cmd_prot;
+
+    wire    reset_done;
+
+    la_drsync la_drsync_i (
+        .clk     (clk),
+        .nreset  (nreset),
+        .in      (1'b1),
+        .out     (reset_done)
+    );
+
+    reg                 write_in_flight;
+    reg                 read_in_flight;
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            write_in_flight <= 1'b0;
+        else if (axi_awvalid & axi_awready)
+            write_in_flight <= 1'b1;
+        else if (axi_bvalid & axi_bready)
+            write_in_flight <= 1'b0;
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            read_in_flight <= 1'b0;
+        else if (axi_arvalid & axi_arready)
+            read_in_flight <= 1'b1;
+        else if (axi_rvalid & axi_rready)
+            read_in_flight <= 1'b0;
+    end
+
+    // Write Address
+    reg  [AW-1:0]       axi_awaddr_r;
+    reg  [2:0]          axi_awprot_r;
+    reg                 axi_awvalid_r;
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset) begin
+            axi_awaddr_r    <= 'b0;
+            axi_awprot_r    <= 'b0;
+        end
+        else if (axi_awvalid & axi_awready) begin
+            axi_awaddr_r    <= axi_awaddr;
+            axi_awprot_r    <= axi_awprot;
+        end
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            axi_awvalid_r   <= 1'b0;
+        else if (axi_awvalid & axi_awready)
+            axi_awvalid_r   <= 1'b1;
+        else if (uhost_req_valid & uhost_req_ready & (umi_req_cmd_opcode == UMI_REQ_WRITE))
+            axi_awvalid_r   <= 1'b0;
+    end
+
+    // Write data prep
+    integer             i;
+    reg  [DWLOG:0]      axi_wstrb_ctr;
+    reg  [(DW/8)-1:0]   axi_wstrb_cml_one;
+    reg  [DWLOG-1:0]    axi_wdata_byte_shift;
+
+    always @* begin
+        axi_wstrb_ctr = {(DWLOG + 1){1'b0}};
+        for (i = 0; i < (DW/8); i = i + 1) begin
+            axi_wstrb_ctr = axi_wstrb_ctr + {{(DWLOG){1'b0}}, axi_wstrb[i]};
+        end
+
+        axi_wstrb_cml_one[0] = axi_wstrb[0];
+        for (i = 1; i < (DW/8); i = i + 1) begin
+            axi_wstrb_cml_one[i] = axi_wstrb[i] | axi_wstrb_cml_one[i-1];
+        end
+
+        axi_wdata_byte_shift = {(DWLOG){1'b0}};
+        for (i = 1; i < (DW/8); i = i + 1) begin
+            if (axi_wstrb[i] & !axi_wstrb_cml_one[i-1])
+                axi_wdata_byte_shift = axi_wdata_byte_shift | i[DWLOG-1:0];
+        end
+    end
+
+    assign axi_awready = !(write_in_flight | read_in_flight) & reset_done;
+
+    // Write data
+    reg  [DW-1:0]       axi_wdata_r;
+    reg  [(DW/8)-1:0]   axi_wstrb_r;
+    reg  [DWLOG:0]      axi_wstrb_ctr_r;
+    reg  [AW-1:0]       axi_addr_offset;
+    reg                 axi_wvalid_r;
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset) begin
+            axi_wdata_r     <= 'b0;
+            axi_wstrb_r     <= 'b0;
+            axi_wstrb_ctr_r <= 'b0;
+            axi_addr_offset <= 'b0;
+        end
+        else if (axi_wvalid & axi_wready) begin
+            axi_wdata_r     <= axi_wdata >> ({3'b000, axi_wdata_byte_shift} << 3);
+            axi_wstrb_r     <= axi_wstrb;
+            axi_wstrb_ctr_r <= axi_wstrb_ctr;
+            axi_addr_offset <= {{(AW-DWLOG){1'b0}}, axi_wdata_byte_shift};
+        end
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            axi_wvalid_r    <= 1'b0;
+        else if (axi_wvalid & axi_wready)
+            axi_wvalid_r    <= 1'b1;
+        else if (uhost_req_valid & uhost_req_ready & (umi_req_cmd_opcode == UMI_REQ_WRITE))
+            axi_wvalid_r    <= 1'b0;
+    end
+
+    assign axi_wready  = axi_awvalid_r & !axi_wvalid_r & reset_done;
+
+    // Read address
+    reg  [AW-1:0]   axi_araddr_r;
+    reg  [2:0]      axi_arprot_r;
+    reg             axi_arvalid_r;
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset) begin
+            axi_araddr_r    <= 'b0;
+            axi_arprot_r    <= 'b0;
+        end
+        else if (axi_arvalid & axi_arready) begin
+            axi_araddr_r    <= axi_araddr;
+            axi_arprot_r    <= axi_arprot;
+        end
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            axi_arvalid_r   <= 1'b0;
+        else if (axi_arvalid & axi_arready)
+            axi_arvalid_r   <= 1'b1;
+        else if (uhost_req_valid & uhost_req_ready & (umi_req_cmd_opcode == UMI_REQ_READ))
+            axi_arvalid_r   <= 1'b0;
+    end
+
+    assign axi_arready = !(write_in_flight | read_in_flight) & reset_done;
+
+    // UMI request
+
+    assign umi_req_cmd_opcode = write_in_flight ?
+                                UMI_REQ_WRITE :
+                                UMI_REQ_READ;
+    assign umi_req_cmd_len    = write_in_flight ?
+                                (axi_wstrb_ctr_r-1) :
+                                ((DW/8)-1);
+    assign umi_req_cmd_prot   = write_in_flight ?
+                                axi_awprot_r[1:0] :
+                                axi_arprot_r[1:0];
+
+    umi_pack #(
+        .CW                 (CW)
+    ) umi_req_pack (
+        .cmd_opcode         (umi_req_cmd_opcode),
+        .cmd_size           (3'b0),
+        .cmd_len            (umi_req_cmd_len),
+        .cmd_atype          (8'b0),
+        .cmd_prot           (umi_req_cmd_prot),
+        .cmd_qos            (4'b0),
+        .cmd_eom            (1'b1),
+        .cmd_eof            (1'b0),
+        .cmd_user           (2'b0),
+        .cmd_err            (2'b00),
+        .cmd_ex             (1'b0),
+        .cmd_hostid         (5'b0),
+        .cmd_user_extended  (24'b0),
+
+        .packet_cmd         (uhost_req_cmd)
+    );
+
+    wire [23:0] chip_address = {{(24-IDW){1'b0}}, chipid};
+
+    assign uhost_req_dstaddr = write_in_flight ?
+                               (axi_awaddr_r + axi_addr_offset) :
+                               axi_araddr_r;
+    assign uhost_req_srcaddr = {chip_address, local_routing, 24'b0};
+    assign uhost_req_data    = axi_wdata_r;
+    assign uhost_req_valid   = write_in_flight ?
+                               (axi_awvalid_r & axi_wvalid_r) :
+                               axi_arvalid_r;
+
+    // UMI response
+    wire [4:0]  umi_resp_cmd_opcode;
+    wire [2:0]  umi_resp_cmd_size;
+    wire [7:0]  umi_resp_cmd_len;
+    wire        umi_resp_cmd_eom;
+    wire [1:0]  umi_resp_cmd_err;
+
+    umi_unpack #(
+        .CW     (CW)
+    ) tl2umi_resp_unpack (
+        // Input CMD
+        .packet_cmd         (uhost_resp_cmd),
+
+        // Output Fields
+        .cmd_opcode         (umi_resp_cmd_opcode),
+        .cmd_size           (umi_resp_cmd_size),
+        .cmd_len            (umi_resp_cmd_len),
+        .cmd_atype          (),
+        .cmd_qos            (),
+        .cmd_prot           (),
+        .cmd_eom            (umi_resp_cmd_eom),
+        .cmd_eof            (),
+        .cmd_ex             (),
+        .cmd_user           (),
+        .cmd_user_extended  (),
+        .cmd_err            (umi_resp_cmd_err),
+        .cmd_hostid         ()
+    );
+
+    assign uhost_resp_ready = write_in_flight ? axi_bready : axi_rready;
+
+    // Read response
+    assign axi_rdata  = uhost_resp_data;
+    assign axi_rresp  = umi_resp_cmd_err;
+    assign axi_rvalid = read_in_flight &
+                        uhost_resp_valid &
+                        (umi_resp_cmd_opcode == UMI_RESP_READ);
+
+    // Write response
+    assign axi_bresp  = umi_resp_cmd_err;
+    assign axi_bvalid = write_in_flight &
+                        uhost_resp_valid &
+                        (umi_resp_cmd_opcode == UMI_RESP_WRITE);
+
+endmodule
diff --git a/utils/testbench/buffer_axilite.memh b/utils/testbench/buffer_axilite.memh
new file mode 100644
index 0000000..874f64c
--- /dev/null
+++ b/utils/testbench/buffer_axilite.memh
@@ -0,0 +1,4098 @@
+@0
+//DAT3_DAT2_DAT1_DAT0
+  0706_0504_0302_0100
+  0F0E_0D0C_0B0A_0908
+  1716_1514_1312_1110
+  1F1E_1D1C_1B1A_1918
+  2726_2524_2322_2120
+  2F2E_2D2C_2B2A_2928
+  3736_3534_3332_3130
+  3F3E_3D3C_3B3A_3938
+  4746_4544_4342_4140
+  4F4E_4D4C_4B4A_4948
+  5756_5554_5352_5150
+  5F5E_5D5C_5B5A_5958
+  6766_6564_6362_6160
+  6F6E_6D6C_6B6A_6968
+  7776_7574_7372_7170
+  7F7E_7D7C_7B7A_7978
+  8786_8584_8382_8180
+  8F8E_8D8C_8B8A_8988
+  9796_9594_9392_9190
+  9F9E_9D9C_9B9A_9998
+  A7A6_A5A4_A3A2_A1A0
+  AFAE_ADAC_ABAA_A9A8
+  B7B6_B5B4_B3B2_B1B0
+  BFBE_BDBC_BBBA_B9B8
+  C7C6_C5C4_C3C2_C1C0
+  CFCE_CDCC_CBCA_C9C8
+  D7D6_D5D4_D3D2_D1D0
+  DFDE_DDDC_DBDA_D9D8
+  E7E6_E5E4_E3E2_E1E0
+  EFEE_EDEC_EBEA_E9E8
+  F7F6_F5F4_F3F2_F1F0
+  FFFE_FDFC_FBFA_F9F8
+  0706_0504_0302_0100
+  0F0E_0D0C_0B0A_0908
+  1716_1514_1312_1110
+  1F1E_1D1C_1B1A_1918
+  2726_2524_2322_2120
+  2F2E_2D2C_2B2A_2928
+  3736_3534_3332_3130
+  3F3E_3D3C_3B3A_3938
+  4746_4544_4342_4140
+  4F4E_4D4C_4B4A_4948
+  5756_5554_5352_5150
+  5F5E_5D5C_5B5A_5958
+  6766_6564_6362_6160
+  6F6E_6D6C_6B6A_6968
+  7776_7574_7372_7170
+  7F7E_7D7C_7B7A_7978
+  8786_8584_8382_8180
+  8F8E_8D8C_8B8A_8988
+  9796_9594_9392_9190
+  9F9E_9D9C_9B9A_9998
+  A7A6_A5A4_A3A2_A1A0
+  AFAE_ADAC_ABAA_A9A8
+  B7B6_B5B4_B3B2_B1B0
+  BFBE_BDBC_BBBA_B9B8
+  C7C6_C5C4_C3C2_C1C0
+  CFCE_CDCC_CBCA_C9C8
+  D7D6_D5D4_D3D2_D1D0
+  DFDE_DDDC_DBDA_D9D8
+  E7E6_E5E4_E3E2_E1E0
+  EFEE_EDEC_EBEA_E9E8
+  F7F6_F5F4_F3F2_F1F0
+  FFFE_FDFC_FBFA_F9F8
+  0706_0504_0302_0100
+  0F0E_0D0C_0B0A_0908
+  1716_1514_1312_1110
+  1F1E_1D1C_1B1A_1918
+  2726_2524_2322_2120
+  2F2E_2D2C_2B2A_2928
+  3736_3534_3332_3130
+  3F3E_3D3C_3B3A_3938
+  4746_4544_4342_4140
+  4F4E_4D4C_4B4A_4948
+  5756_5554_5352_5150
+  5F5E_5D5C_5B5A_5958
+  6766_6564_6362_6160
+  6F6E_6D6C_6B6A_6968
+  7776_7574_7372_7170
+  7F7E_7D7C_7B7A_7978
+  8786_8584_8382_8180
+  8F8E_8D8C_8B8A_8988
+  9796_9594_9392_9190
+  9F9E_9D9C_9B9A_9998
+  A7A6_A5A4_A3A2_A1A0
+  AFAE_ADAC_ABAA_A9A8
+  B7B6_B5B4_B3B2_B1B0
+  BFBE_BDBC_BBBA_B9B8
+  C7C6_C5C4_C3C2_C1C0
+  CFCE_CDCC_CBCA_C9C8
+  D7D6_D5D4_D3D2_D1D0
+  DFDE_DDDC_DBDA_D9D8
+  E7E6_E5E4_E3E2_E1E0
+  EFEE_EDEC_EBEA_E9E8
+  F7F6_F5F4_F3F2_F1F0
+  FFFE_FDFC_FBFA_F9F8
+  0706_0504_0302_0100
+  0F0E_0D0C_0B0A_0908
+  1716_1514_1312_1110
+  1F1E_1D1C_1B1A_1918
+  2726_2524_2322_2120
+  2F2E_2D2C_2B2A_2928
+  3736_3534_3332_3130
+  3F3E_3D3C_3B3A_3938
+  4746_4544_4342_4140
+  4F4E_4D4C_4B4A_4948
+  5756_5554_5352_5150
+  5F5E_5D5C_5B5A_5958
+  6766_6564_6362_6160
+  6F6E_6D6C_6B6A_6968
+  7776_7574_7372_7170
+  7F7E_7D7C_7B7A_7978
+  8786_8584_8382_8180
+  8F8E_8D8C_8B8A_8988
+  9796_9594_9392_9190
+  9F9E_9D9C_9B9A_9998
+  A7A6_A5A4_A3A2_A1A0
+  AFAE_ADAC_ABAA_A9A8
+  B7B6_B5B4_B3B2_B1B0
+  BFBE_BDBC_BBBA_B9B8
+  C7C6_C5C4_C3C2_C1C0
+  CFCE_CDCC_CBCA_C9C8
+  D7D6_D5D4_D3D2_D1D0
+  DFDE_DDDC_DBDA_D9D8
+  E7E6_E5E4_E3E2_E1E0
+  EFEE_EDEC_EBEA_E9E8
+  F7F6_F5F4_F3F2_F1F0
+  FFFE_FDFC_FBFA_F9F8
+  0706_0504_0302_0100
+  0F0E_0D0C_0B0A_0908
+  1716_1514_1312_1110
+  1F1E_1D1C_1B1A_1918
+  2726_2524_2322_2120
+  2F2E_2D2C_2B2A_2928
+  3736_3534_3332_3130
+  3F3E_3D3C_3B3A_3938
+  4746_4544_4342_4140
+  4F4E_4D4C_4B4A_4948
+  5756_5554_5352_5150
+  5F5E_5D5C_5B5A_5958
+  6766_6564_6362_6160
+  6F6E_6D6C_6B6A_6968
+  7776_7574_7372_7170
+  7F7E_7D7C_7B7A_7978
+  8786_8584_8382_8180
+  8F8E_8D8C_8B8A_8988
+  9796_9594_9392_9190
+  9F9E_9D9C_9B9A_9998
+  A7A6_A5A4_A3A2_A1A0
+  AFAE_ADAC_ABAA_A9A8
+  B7B6_B5B4_B3B2_B1B0
+  BFBE_BDBC_BBBA_B9B8
+  C7C6_C5C4_C3C2_C1C0
+  CFCE_CDCC_CBCA_C9C8
+  D7D6_D5D4_D3D2_D1D0
+  DFDE_DDDC_DBDA_D9D8
+  E7E6_E5E4_E3E2_E1E0
+  EFEE_EDEC_EBEA_E9E8
+  F7F6_F5F4_F3F2_F1F0
+  FFFE_FDFC_FBFA_F9F8
+  0706_0504_0302_0100
+  0F0E_0D0C_0B0A_0908
+  1716_1514_1312_1110
+  1F1E_1D1C_1B1A_1918
+  2726_2524_2322_2120
+  2F2E_2D2C_2B2A_2928
+  3736_3534_3332_3130
+  3F3E_3D3C_3B3A_3938
+  4746_4544_4342_4140
+  4F4E_4D4C_4B4A_4948
+  5756_5554_5352_5150
+  5F5E_5D5C_5B5A_5958
+  6766_6564_6362_6160
+  6F6E_6D6C_6B6A_6968
+  7776_7574_7372_7170
+  7F7E_7D7C_7B7A_7978
+  8786_8584_8382_8180
+  8F8E_8D8C_8B8A_8988
+  9796_9594_9392_9190
+  9F9E_9D9C_9B9A_9998
+  A7A6_A5A4_A3A2_A1A0
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+  D7D6_D5D4_D3D2_D1D0
+  DFDE_DDDC_DBDA_D9D8
+  E7E6_E5E4_E3E2_E1E0
+  EFEE_EDEC_EBEA_E9E8
+  F7F6_F5F4_F3F2_F1F0
+  FFFE_FDFC_FBFA_F9F8
diff --git a/utils/testbench/build_local.sh b/utils/testbench/build_local.sh
index 0c3f92c..791bfd2 100755
--- a/utils/testbench/build_local.sh
+++ b/utils/testbench/build_local.sh
@@ -3,19 +3,20 @@
 MAIN_DIR=$(pwd)/../..
 RTL_DIR=$MAIN_DIR/utils/rtl
 
-iverilog tb_tl2umi_np.v \
+iverilog \
     -y . \
     -I . \
     -y $RTL_DIR \
     -I $RTL_DIR \
     -y $MAIN_DIR/umi/rtl \
     -I $MAIN_DIR/umi/rtl \
-    -y $MAIN_DIR/submodules/lambdalib/padring/rtl \
-    -I $MAIN_DIR/submodules/lambdalib/padring/rtl \
-    -y $MAIN_DIR/submodules/lambdalib/stdlib/rtl \
-    -y $MAIN_DIR/submodules/lambdalib/vectorlib/rtl \
-    -y $MAIN_DIR/submodules/lambdalib/ramlib/rtl
+    -y $MAIN_DIR/../lambdalib/lambdalib/padring/rtl \
+    -I $MAIN_DIR/../lambdalib/lambdalib/padring/rtl \
+    -y $MAIN_DIR/../lambdalib/lambdalib/stdlib/rtl \
+    -y $MAIN_DIR/../lambdalib/lambdalib/vectorlib/rtl \
+    -y $MAIN_DIR/../lambdalib/lambdalib/ramlib/rtl \
+    tb_axilite2umi.v
 
 #./a.out
-./a.out +MEMHFILE=./buffer.memh
+./a.out +MEMHFILE=./buffer_axilite.memh
 #./a.out +MEMHFILE=$MAIN_DIR/umi/testbench/buffer.memh
diff --git a/utils/testbench/tb_axilite2umi.v b/utils/testbench/tb_axilite2umi.v
new file mode 100644
index 0000000..4ff3ded
--- /dev/null
+++ b/utils/testbench/tb_axilite2umi.v
@@ -0,0 +1,363 @@
+/*******************************************************************************
+ * Copyright 2023 Zero ASIC Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----
+ *
+ * Documentation:
+ * - AXI4-Lite to UMI converter testbench
+ *
+ ******************************************************************************/
+
+`timescale 1ns / 1ps
+`default_nettype wire
+
+module tb_axilite2umi #(
+    parameter TARGET     = "DEFAULT",   // pass through variable for hard macro
+    parameter TIMEOUT    = 500000,      // timeout value (cycles)
+    parameter PERIOD_CLK = 10           // clock period
+)
+();
+
+    // Local parameters
+    localparam CW        = 32;          // UMI width
+    localparam AW        = 64;          // UMI width
+    localparam DW        = 64;
+    localparam RAMDEPTH  = 4096;  // param specific to testbench
+
+    // Clock
+    reg             clk;
+
+    always
+        #(PERIOD_CLK/2) clk = ~clk;
+
+    // SIM Ctrl signals
+    reg                     nreset;
+    reg [DW*RAMDEPTH-1:0]   memhfile;
+    integer                 r;
+
+    // Reset initialization
+    initial begin
+        #(1)
+        nreset   = 1'b0;
+        clk      = 1'b0;
+        #(PERIOD_CLK * 10)
+        nreset   = 1'b1;
+    end // initial begin
+
+    // AXI4Lite Interface
+    reg  [AW-1:0]       axi_awaddr;
+    reg  [2:0]          axi_awprot;
+    reg                 axi_awvalid;
+    wire                axi_awready;
+
+    reg  [DW-1:0]       axi_wdata;
+    reg  [(DW/8)-1:0]   axi_wstrb;
+    reg                 axi_wvalid;
+    wire                axi_wready;
+
+    wire [1:0]          axi_bresp;
+    wire                axi_bvalid;
+    reg                 axi_bready;
+
+    reg  [AW-1:0]       axi_araddr;
+    reg  [2:0]          axi_arprot;
+    reg                 axi_arvalid;
+    wire                axi_arready;
+
+    wire [DW-1:0]       axi_rdata;
+    wire [1:0]          axi_rresp;
+    wire                axi_rvalid;
+    reg                 axi_rready;
+
+    // Host UMI signals
+    wire            uhost_req_valid;
+    wire [CW-1:0]   uhost_req_cmd;
+    wire [AW-1:0]   uhost_req_dstaddr;
+    wire [AW-1:0]   uhost_req_srcaddr;
+    wire [DW-1:0]   uhost_req_data;
+    wire            uhost_req_ready;
+
+    wire            uhost_resp_valid;
+    wire [CW-1:0]   uhost_resp_cmd;
+    wire [AW-1:0]   uhost_resp_dstaddr;
+    wire [AW-1:0]   uhost_resp_srcaddr;
+    wire [DW-1:0]   uhost_resp_data;
+    wire            uhost_resp_ready;
+
+    axilite2umi #(
+        .CW         (CW),
+        .AW         (AW),
+        .DW         (DW),
+        .IDW        (16)
+    ) dut (
+        .clk                (clk),
+        .nreset             (nreset),
+
+        // FIXME: The bottom 4 bits of chipid are kept 4'b0001.
+        // This hack is to ensure that the memory agent responds on its UMI(0,0)
+        // This needs to be fixed either by using a correct address map or
+        // enabling all 4 ports. Priority is low.
+        .chipid             (16'hAE51),
+        .local_routing      (16'hDEAD),
+
+        // AXI4Lite Interface
+        .axi_awaddr         (axi_awaddr),
+        .axi_awprot         (axi_awprot),
+        .axi_awvalid        (axi_awvalid),
+        .axi_awready        (axi_awready),
+
+        .axi_wdata          (axi_wdata),
+        .axi_wstrb          (axi_wstrb),
+        .axi_wvalid         (axi_wvalid),
+        .axi_wready         (axi_wready),
+
+        .axi_bresp          (axi_bresp),
+        .axi_bvalid         (axi_bvalid),
+        .axi_bready         (axi_bready),
+
+        .axi_araddr         (axi_araddr),
+        .axi_arprot         (axi_arprot),
+        .axi_arvalid        (axi_arvalid),
+        .axi_arready        (axi_arready),
+
+        .axi_rdata          (axi_rdata),
+        .axi_rresp          (axi_rresp),
+        .axi_rvalid         (axi_rvalid),
+        .axi_rready         (axi_rready),
+
+        // Host port (per clink)
+        .uhost_req_valid    (uhost_req_valid),
+        .uhost_req_cmd      (uhost_req_cmd),
+        .uhost_req_dstaddr  (uhost_req_dstaddr),
+        .uhost_req_srcaddr  (uhost_req_srcaddr),
+        .uhost_req_data     (uhost_req_data),
+        .uhost_req_ready    (uhost_req_ready),
+
+        .uhost_resp_valid   (uhost_resp_valid),
+        .uhost_resp_cmd     (uhost_resp_cmd),
+        .uhost_resp_dstaddr (uhost_resp_dstaddr),
+        .uhost_resp_srcaddr (uhost_resp_srcaddr),
+        .uhost_resp_data    (uhost_resp_data),
+        .uhost_resp_ready   (uhost_resp_ready)
+    );
+
+    umi_mem_agent #(
+        .DW         (DW),
+        .AW         (AW),
+        .CW         (CW),
+        .RAMDEPTH   (RAMDEPTH)
+    ) memory_module_ (
+        .clk                (clk),
+        .nreset             (nreset),
+
+        .udev_req_valid     (uhost_req_valid),
+        .udev_req_cmd       (uhost_req_cmd),
+        .udev_req_dstaddr   (uhost_req_dstaddr),
+        .udev_req_srcaddr   (uhost_req_srcaddr),
+        .udev_req_data      (uhost_req_data),
+        .udev_req_ready     (uhost_req_ready),
+
+        .udev_resp_valid    (uhost_resp_valid),
+        .udev_resp_cmd      (uhost_resp_cmd),
+        .udev_resp_dstaddr  (uhost_resp_dstaddr),
+        .udev_resp_srcaddr  (uhost_resp_srcaddr),
+        .udev_resp_data     (uhost_resp_data),
+        .udev_resp_ready    (uhost_resp_ready)
+    );
+
+    // Generate AXI transactions
+    wire [7:0] axi_wstrb_options [0:35];
+    reg  [5:0] axi_wstrb_sel_r;
+    wire [5:0] axi_wstrb_sel;
+
+    assign axi_wstrb_options[0]  = 8'h01;
+    assign axi_wstrb_options[1]  = 8'h02;
+    assign axi_wstrb_options[2]  = 8'h04;
+    assign axi_wstrb_options[3]  = 8'h08;
+    assign axi_wstrb_options[4]  = 8'h10;
+    assign axi_wstrb_options[5]  = 8'h20;
+    assign axi_wstrb_options[6]  = 8'h40;
+    assign axi_wstrb_options[7]  = 8'h80;
+    assign axi_wstrb_options[8]  = 8'h03;
+    assign axi_wstrb_options[9]  = 8'h06;
+    assign axi_wstrb_options[10] = 8'h0C;
+    assign axi_wstrb_options[11] = 8'h18;
+    assign axi_wstrb_options[12] = 8'h30;
+    assign axi_wstrb_options[13] = 8'h60;
+    assign axi_wstrb_options[14] = 8'hC0;
+    assign axi_wstrb_options[15] = 8'h07;
+    assign axi_wstrb_options[16] = 8'h0E;
+    assign axi_wstrb_options[17] = 8'h1C;
+    assign axi_wstrb_options[18] = 8'h38;
+    assign axi_wstrb_options[19] = 8'h70;
+    assign axi_wstrb_options[20] = 8'hE0;
+    assign axi_wstrb_options[21] = 8'h0F;
+    assign axi_wstrb_options[22] = 8'h1E;
+    assign axi_wstrb_options[23] = 8'h3C;
+    assign axi_wstrb_options[24] = 8'h78;
+    assign axi_wstrb_options[25] = 8'hF0;
+    assign axi_wstrb_options[26] = 8'h1F;
+    assign axi_wstrb_options[27] = 8'h3E;
+    assign axi_wstrb_options[28] = 8'h7C;
+    assign axi_wstrb_options[29] = 8'hF8;
+    assign axi_wstrb_options[30] = 8'h3F;
+    assign axi_wstrb_options[31] = 8'h7E;
+    assign axi_wstrb_options[32] = 8'hFC;
+    assign axi_wstrb_options[33] = 8'h7F;
+    assign axi_wstrb_options[34] = 8'hFE;
+    assign axi_wstrb_options[35] = 8'hFF;
+
+    always @(posedge clk) begin
+        axi_awaddr  <= $random & 64'h0000_0000_0000_7FF8; // 64 bit aligned
+        axi_awprot  <= $random;
+        axi_awvalid <= $random;
+        axi_wdata   <= {$random, $random};
+        axi_wstrb   <= axi_wstrb_options[axi_wstrb_sel];
+        axi_wvalid  <= $random;
+        axi_bready  <= $random;
+
+        axi_araddr  <= $random & 64'h0000_0000_0000_7FF8; // 64 bit aligned
+        axi_arprot  <= $random;
+        axi_arvalid <= $random;
+        axi_rready  <= $random;
+
+        axi_wstrb_sel_r <= $random;
+    end
+    assign axi_wstrb_sel = (axi_wstrb_sel_r > 35) ?
+                           (axi_wstrb_sel_r - 36) :
+                           axi_wstrb_sel_r;
+
+    // Scoreboard
+    reg  [DW-1:0]   checker_ram [0:RAMDEPTH-1];
+    reg  [AW-1:0]   write_addr_golden;
+    reg  [AW-1:0]   read_addr_golden;
+    wire [DW-1:0]   read_data_golden;
+
+    genvar i;
+
+    always @(posedge clk) begin
+        if (axi_awvalid & axi_awready)
+            write_addr_golden <= axi_awaddr;
+    end
+
+    for (i = 0; i < (DW/8); i = i + 1) begin
+        always @(posedge clk) begin
+            if (axi_wvalid & axi_wready) begin
+                if (axi_wstrb[i]) begin
+                    checker_ram[write_addr_golden[AW-1:$clog2(DW/8)]][i*8+:8] <= axi_wdata[i*8+:8];
+                end
+            end
+        end
+    end
+
+    always @(posedge clk) begin
+        if (axi_arvalid & axi_arready)
+            read_addr_golden <= axi_araddr;
+    end
+
+    assign read_data_golden = checker_ram[read_addr_golden[AW-1:$clog2(DW/8)]];
+
+    always @(posedge clk) begin
+        if (axi_rvalid & axi_rready) begin
+            if (read_data_golden != axi_rdata) begin
+                $display("Mismatch! Address: 0x%h, Expected: 0x%h, Actual: 0x%h", read_addr_golden, read_data_golden, axi_rdata);
+                $finish;
+            end
+        end
+    end
+
+    //always @(posedge clk) begin
+    //    if (axi_awvalid & axi_awready)
+    //        $display("Writing data to: 0x%h", axi_awaddr);
+    //    if (axi_wvalid & axi_wready)
+    //        $display("Data written: 0x%h, strobe: 0b%b", axi_wdata, axi_wstrb);
+    //    if (axi_arvalid & axi_arready)
+    //        $display("Reading data from: 0x%h", axi_araddr);
+    //end
+
+    // Perf Counters
+    wire        axi_awcommit;
+    wire        axi_wcommit;
+    wire        axi_bcommit;
+    wire        axi_arcommit;
+    wire        axi_rcommit;
+    reg [31:0]  axi_awctr;
+    reg [31:0]  axi_wctr;
+    reg [31:0]  axi_bctr;
+    reg [31:0]  axi_arctr;
+    reg [31:0]  axi_rctr;
+
+    assign axi_awcommit = axi_awready & axi_awvalid;
+    assign axi_wcommit  = axi_wready & axi_wvalid;
+    assign axi_bcommit  = axi_bready & axi_bvalid;
+    assign axi_arcommit = axi_arready & axi_arvalid;
+    assign axi_rcommit  = axi_rready & axi_rvalid;
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset) begin
+            axi_awctr <= 'b0;
+            axi_wctr  <= 'b0;
+            axi_bctr  <= 'b0;
+            axi_arctr <= 'b0;
+            axi_rctr  <= 'b0;
+        end
+        else begin
+            if (axi_awcommit) axi_awctr <= axi_awctr + 1;
+            if (axi_wcommit)  axi_wctr  <= axi_wctr  + 1;
+            if (axi_bcommit)  axi_bctr  <= axi_bctr  + 1;
+            if (axi_arcommit) axi_arctr <= axi_arctr + 1;
+            if (axi_rcommit)  axi_rctr  <= axi_rctr  + 1;
+        end
+    end
+
+    wire        umi_req_commit;
+    wire        umi_resp_commit;
+    reg [31:0]  umi_req_ctr;
+    reg [31:0]  umi_resp_ctr;
+
+    assign umi_req_commit = uhost_req_ready & uhost_req_valid;
+    assign umi_resp_commit = uhost_resp_ready & uhost_resp_valid;
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset) begin
+            umi_req_ctr  <= 'b0;
+            umi_resp_ctr <= 'b0;
+        end
+        else begin
+            if (umi_req_commit) umi_req_ctr  <= umi_req_ctr + 1;
+            if (umi_resp_commit) umi_resp_ctr <= umi_resp_ctr+ 1;
+        end
+    end
+
+    // control block
+    initial begin
+        r = $value$plusargs("MEMHFILE=%s", memhfile);
+        $readmemh(memhfile, memory_module_.la_spram_i.ram);
+        $readmemh(memhfile, checker_ram);
+        $timeformat(-9, 0, " ns", 20);
+        $dumpfile("waveform.vcd");
+        $dumpvars();
+        #(TIMEOUT)
+        $display("AXI Write Address Count: %d", axi_awctr);
+        $display("AXI Write Data Count: %d", axi_wctr);
+        $display("AXI Write Response Count: %d", axi_bctr);
+        $display("AXI Read Address Count: %d", axi_arctr);
+        $display("AXI Read Data Count: %d", axi_rctr);
+        $display("UMI Req Count: %d", umi_req_ctr);
+        $display("UMI Resp Count: %d", umi_resp_ctr);
+        $finish;
+    end
+
+endmodule

From 570bbaad7d2a63822c1acd1bc03b780d1f280f5f Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Fri, 1 Mar 2024 12:43:43 -0500
Subject: [PATCH 2/8] Modify testbench to work with 32 and 64 bit DW

---
 utils/testbench/tb_axilite2umi.v | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/utils/testbench/tb_axilite2umi.v b/utils/testbench/tb_axilite2umi.v
index 4ff3ded..b6bc387 100644
--- a/utils/testbench/tb_axilite2umi.v
+++ b/utils/testbench/tb_axilite2umi.v
@@ -186,28 +186,28 @@ module tb_axilite2umi #(
     assign axi_wstrb_options[1]  = 8'h02;
     assign axi_wstrb_options[2]  = 8'h04;
     assign axi_wstrb_options[3]  = 8'h08;
-    assign axi_wstrb_options[4]  = 8'h10;
-    assign axi_wstrb_options[5]  = 8'h20;
-    assign axi_wstrb_options[6]  = 8'h40;
-    assign axi_wstrb_options[7]  = 8'h80;
+    assign axi_wstrb_options[4]  = (DW == 64) ? 8'h10 : 8'h01;
+    assign axi_wstrb_options[5]  = (DW == 64) ? 8'h20 : 8'h02;
+    assign axi_wstrb_options[6]  = (DW == 64) ? 8'h40 : 8'h04;
+    assign axi_wstrb_options[7]  = (DW == 64) ? 8'h80 : 8'h08;
     assign axi_wstrb_options[8]  = 8'h03;
     assign axi_wstrb_options[9]  = 8'h06;
     assign axi_wstrb_options[10] = 8'h0C;
     assign axi_wstrb_options[11] = 8'h18;
-    assign axi_wstrb_options[12] = 8'h30;
-    assign axi_wstrb_options[13] = 8'h60;
-    assign axi_wstrb_options[14] = 8'hC0;
+    assign axi_wstrb_options[12] = (DW == 64) ? 8'h30 : 8'h03;
+    assign axi_wstrb_options[13] = (DW == 64) ? 8'h60 : 8'h06;
+    assign axi_wstrb_options[14] = (DW == 64) ? 8'hC0 : 8'h0C;
     assign axi_wstrb_options[15] = 8'h07;
     assign axi_wstrb_options[16] = 8'h0E;
     assign axi_wstrb_options[17] = 8'h1C;
     assign axi_wstrb_options[18] = 8'h38;
-    assign axi_wstrb_options[19] = 8'h70;
-    assign axi_wstrb_options[20] = 8'hE0;
+    assign axi_wstrb_options[19] = (DW == 64) ? 8'h70 : 8'h07;
+    assign axi_wstrb_options[20] = (DW == 64) ? 8'hE0 : 8'h0E;
     assign axi_wstrb_options[21] = 8'h0F;
     assign axi_wstrb_options[22] = 8'h1E;
     assign axi_wstrb_options[23] = 8'h3C;
     assign axi_wstrb_options[24] = 8'h78;
-    assign axi_wstrb_options[25] = 8'hF0;
+    assign axi_wstrb_options[25] = (DW == 64) ? 8'hF0 : 8'h0F;
     assign axi_wstrb_options[26] = 8'h1F;
     assign axi_wstrb_options[27] = 8'h3E;
     assign axi_wstrb_options[28] = 8'h7C;
@@ -220,7 +220,7 @@ module tb_axilite2umi #(
     assign axi_wstrb_options[35] = 8'hFF;
 
     always @(posedge clk) begin
-        axi_awaddr  <= $random & 64'h0000_0000_0000_7FF8; // 64 bit aligned
+        axi_awaddr  <= $random & ((RAMDEPTH-1) << $clog2(DW/8)); // 64 bit aligned
         axi_awprot  <= $random;
         axi_awvalid <= $random;
         axi_wdata   <= {$random, $random};
@@ -228,7 +228,7 @@ module tb_axilite2umi #(
         axi_wvalid  <= $random;
         axi_bready  <= $random;
 
-        axi_araddr  <= $random & 64'h0000_0000_0000_7FF8; // 64 bit aligned
+        axi_araddr  <= $random & ((RAMDEPTH-1) << $clog2(DW/8)); // 64 bit aligned
         axi_arprot  <= $random;
         axi_arvalid <= $random;
         axi_rready  <= $random;

From 95486e169293431ab90b4524050b9042792df9d9 Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Mon, 4 Mar 2024 14:38:19 -0500
Subject: [PATCH 3/8] Minor fixes

---
 utils/rtl/axilite2umi.v          | 16 ++++++++++------
 utils/testbench/tb_axilite2umi.v |  2 +-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/utils/rtl/axilite2umi.v b/utils/rtl/axilite2umi.v
index fcb2ee7..33821d7 100644
--- a/utils/rtl/axilite2umi.v
+++ b/utils/rtl/axilite2umi.v
@@ -265,8 +265,8 @@ module axilite2umi #(
     assign uhost_req_srcaddr = {chip_address, local_routing, 24'b0};
     assign uhost_req_data    = axi_wdata_r;
     assign uhost_req_valid   = write_in_flight ?
-                               (axi_awvalid_r & axi_wvalid_r) :
-                               axi_arvalid_r;
+                               (axi_awvalid_r & axi_wvalid_r & reset_done) :
+                               (axi_arvalid_r & reset_done);
 
     // UMI response
     wire [4:0]  umi_resp_cmd_opcode;
@@ -277,7 +277,7 @@ module axilite2umi #(
 
     umi_unpack #(
         .CW     (CW)
-    ) tl2umi_resp_unpack (
+    ) axilite2umi_resp_unpack (
         // Input CMD
         .packet_cmd         (uhost_resp_cmd),
 
@@ -297,19 +297,23 @@ module axilite2umi #(
         .cmd_hostid         ()
     );
 
-    assign uhost_resp_ready = write_in_flight ? axi_bready : axi_rready;
+    assign uhost_resp_ready = write_in_flight ?
+                              (axi_bready & reset_done) :
+                              (axi_rready & reset_done);
 
     // Read response
     assign axi_rdata  = uhost_resp_data;
     assign axi_rresp  = umi_resp_cmd_err;
     assign axi_rvalid = read_in_flight &
                         uhost_resp_valid &
-                        (umi_resp_cmd_opcode == UMI_RESP_READ);
+                        (umi_resp_cmd_opcode == UMI_RESP_READ) &
+                        reset_done;
 
     // Write response
     assign axi_bresp  = umi_resp_cmd_err;
     assign axi_bvalid = write_in_flight &
                         uhost_resp_valid &
-                        (umi_resp_cmd_opcode == UMI_RESP_WRITE);
+                        (umi_resp_cmd_opcode == UMI_RESP_WRITE) &
+                        reset_done;
 
 endmodule
diff --git a/utils/testbench/tb_axilite2umi.v b/utils/testbench/tb_axilite2umi.v
index b6bc387..44f14c9 100644
--- a/utils/testbench/tb_axilite2umi.v
+++ b/utils/testbench/tb_axilite2umi.v
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright 2023 Zero ASIC Corporation
+ * Copyright 2024 Zero ASIC Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.

From 9c3d17b94da7d4bbe779676a6cf5ad4742916ded Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Mon, 4 Mar 2024 14:39:13 -0500
Subject: [PATCH 4/8] Add UMI to AXI4-Lite converter and testbench

---
 utils/rtl/umi2axilite.v                  | 364 +++++++++++++++++++++++
 utils/testbench/test_umi2axilite.py      |  99 ++++++
 utils/testbench/testbench_umi2axilite.sv | 297 ++++++++++++++++++
 3 files changed, 760 insertions(+)
 create mode 100644 utils/rtl/umi2axilite.v
 create mode 100755 utils/testbench/test_umi2axilite.py
 create mode 100644 utils/testbench/testbench_umi2axilite.sv

diff --git a/utils/rtl/umi2axilite.v b/utils/rtl/umi2axilite.v
new file mode 100644
index 0000000..df86a0c
--- /dev/null
+++ b/utils/rtl/umi2axilite.v
@@ -0,0 +1,364 @@
+/*******************************************************************************
+ * Copyright 2023 Zero ASIC Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----
+ *
+ * Documentation:
+ * - UMI to AXI4-Lite converter
+ *
+ ******************************************************************************/
+
+`default_nettype wire
+
+module umi2axilite #(
+    parameter CW    = 32,   // command width
+    parameter AW    = 64,   // address width
+    parameter DW    = 64    // umi packet width
+)
+(
+    input               clk,
+    input               nreset,
+
+    // UMI Device port
+    input               udev_req_valid,
+    input  [CW-1:0]     udev_req_cmd,
+    input  [AW-1:0]     udev_req_dstaddr,
+    input  [AW-1:0]     udev_req_srcaddr,
+    input  [DW-1:0]     udev_req_data,
+    output              udev_req_ready,
+
+    output              udev_resp_valid,
+    output [CW-1:0]     udev_resp_cmd,
+    output [AW-1:0]     udev_resp_dstaddr,
+    output [AW-1:0]     udev_resp_srcaddr,
+    output [DW-1:0]     udev_resp_data,
+    input               udev_resp_ready,
+
+    // AXI4Lite Interface
+    output [AW-1:0]     axi_awaddr,
+    output [2:0]        axi_awprot,
+    output              axi_awvalid,
+    input               axi_awready,
+
+    output [DW-1:0]     axi_wdata,
+    output [(DW/8)-1:0] axi_wstrb,
+    output              axi_wvalid,
+    input               axi_wready,
+
+    input  [1:0]        axi_bresp,
+    input               axi_bvalid,
+    output              axi_bready,
+
+    output [AW-1:0]     axi_araddr,
+    output [2:0]        axi_arprot,
+    output              axi_arvalid,
+    input               axi_arready,
+
+    input  [DW-1:0]     axi_rdata,
+    input  [1:0]        axi_rresp,
+    input               axi_rvalid,
+    output              axi_rready
+);
+
+    `include "umi_messages.vh"
+
+    localparam DWLOG = $clog2(DW/8);
+
+    wire    reset_done;
+
+    la_drsync la_drsync_i (
+        .clk     (clk),
+        .nreset  (nreset),
+        .in      (1'b1),
+        .out     (reset_done)
+    );
+
+    // Split incoming requests
+    wire                ff_out_req_valid;
+    wire [CW-1:0]       ff_out_req_cmd;
+    wire [AW-1:0]       ff_out_req_dstaddr;
+    wire [AW-1:0]       ff_out_req_srcaddr;
+    wire [DW-1:0]       ff_out_req_data;
+    wire                ff_out_req_ready;
+
+    umi_fifo_flex #(
+        .TARGET         ("DEFAULT"),
+        .ASYNC          (0),
+        .SPLIT          (1),
+        .DEPTH          (0),
+        .CW             (CW),
+        .AW             (AW),
+        .IDW            (DW),
+        .ODW            (DW)
+    ) umi2axilite_req_fifo_flex (
+        .bypass         (1'b1),
+        .chaosmode      (1'b0),
+        .fifo_full      (),
+        .fifo_empty     (),
+
+        // Input
+        .umi_in_clk     (clk),
+        .umi_in_nreset  (nreset),
+        .umi_in_valid   (udev_req_valid),
+        .umi_in_cmd     (udev_req_cmd),
+        .umi_in_dstaddr (udev_req_dstaddr),
+        .umi_in_srcaddr (udev_req_srcaddr),
+        .umi_in_data    (udev_req_data),
+        .umi_in_ready   (udev_req_ready),
+
+        // Output
+        .umi_out_clk    (clk),
+        .umi_out_nreset (nreset),
+        .umi_out_valid  (ff_out_req_valid),
+        .umi_out_cmd    (ff_out_req_cmd),
+        .umi_out_dstaddr(ff_out_req_dstaddr),
+        .umi_out_srcaddr(ff_out_req_srcaddr),
+        .umi_out_data   (ff_out_req_data),
+        .umi_out_ready  (ff_out_req_ready),
+
+        // Supplies
+        .vdd            (1'b1),
+        .vss            (1'b0)
+    );
+
+    // UMI request unpack
+    wire [4:0]  ff_out_req_cmd_opcode;
+    wire [2:0]  ff_out_req_cmd_size;
+    wire [7:0]  ff_out_req_cmd_len;
+
+    umi_unpack #(
+        .CW     (CW)
+    ) umi2axilite_ff_req_unpack (
+        // Input CMD
+        .packet_cmd         (ff_out_req_cmd),
+
+        // Output Fields
+        .cmd_opcode         (ff_out_req_cmd_opcode),
+        .cmd_size           (ff_out_req_cmd_size),
+        .cmd_len            (ff_out_req_cmd_len),
+        .cmd_atype          (),
+        .cmd_qos            (),
+        .cmd_prot           (),
+        .cmd_eom            (),
+        .cmd_eof            (),
+        .cmd_ex             (),
+        .cmd_user           (),
+        .cmd_user_extended  (),
+        .cmd_err            (),
+        .cmd_hostid         ()
+    );
+
+    // UMI request (post split) buffering
+    reg  [CW-1:0]       ff_out_req_cmd_r;
+    reg  [AW-1:0]       ff_out_req_dstaddr_r;
+    reg  [AW-1:0]       ff_out_req_srcaddr_r;
+    reg  [DW-1:0]       ff_out_req_data_shifted_r;
+    reg  [(DW/8)-1:0]   ff_out_req_data_strb_r;
+    reg  [DWLOG-1:0]    req_data_shift_r;
+
+    wire [DWLOG-1:0]    req_data_shift;
+    wire [8:0]          ff_out_req_cmd_len_plus_one;
+    wire [15:0]         req_data_bytes;
+    wire [(DW/8)-1:0]   ff_out_req_data_strb_unshifted;
+
+    genvar i;
+
+    assign req_data_shift = ff_out_req_dstaddr[DWLOG-1:0];
+
+    assign ff_out_req_cmd_len_plus_one = (ff_out_req_cmd_len + 1);
+    assign req_data_bytes = {7'b0, ff_out_req_cmd_len_plus_one} << ff_out_req_cmd_size;
+
+    for (i = 0; i < (DW/8); i = i + 1) begin
+        assign ff_out_req_data_strb_unshifted[i] = (i < req_data_bytes) ? 1'b1 : 1'b0;
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset) begin
+            ff_out_req_cmd_r            <= 'b0;
+            ff_out_req_dstaddr_r        <= 'b0;
+            ff_out_req_srcaddr_r        <= 'b0;
+            ff_out_req_data_shifted_r   <= 'b0;
+            ff_out_req_data_strb_r      <= 'b0;
+            req_data_shift_r            <= 'b0;
+        end
+        else if (ff_out_req_valid & ff_out_req_ready) begin
+            ff_out_req_cmd_r            <= ff_out_req_cmd;
+            ff_out_req_dstaddr_r        <= ff_out_req_dstaddr;
+            ff_out_req_srcaddr_r        <= ff_out_req_srcaddr;
+            ff_out_req_data_shifted_r   <= ff_out_req_data << (req_data_shift << 3);
+            ff_out_req_data_strb_r      <= ff_out_req_data_strb_unshifted << req_data_shift;
+            req_data_shift_r            <= req_data_shift;
+        end
+    end
+
+    wire                axi_write_en;
+    wire                axi_read_en;
+    reg                 axi_awvalid_r;
+    reg                 axi_wvalid_r;
+    reg                 axi_arvalid_r;
+
+    assign axi_write_en = ff_out_req_valid &
+                          ff_out_req_ready &
+                          ((ff_out_req_cmd_opcode == UMI_REQ_WRITE) |
+                          (ff_out_req_cmd_opcode == UMI_REQ_POSTED));
+
+    assign axi_read_en  = ff_out_req_valid &
+                          ff_out_req_ready &
+                          (ff_out_req_cmd_opcode == UMI_REQ_READ);
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            axi_awvalid_r <= 1'b0;
+        else if (axi_write_en)
+            axi_awvalid_r <= 1'b1;
+        else if (axi_awvalid & axi_awready)
+            axi_awvalid_r <= 1'b0;
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            axi_wvalid_r <= 1'b0;
+        else if (axi_write_en)
+            axi_wvalid_r <= 1'b1;
+        else if (axi_wvalid & axi_wready)
+            axi_wvalid_r <= 1'b0;
+    end
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            axi_arvalid_r <= 1'b0;
+        else if (axi_read_en)
+            axi_arvalid_r <= 1'b1;
+        else if (axi_arvalid & axi_arready)
+            axi_arvalid_r <= 1'b0;
+    end
+
+    wire [4:0]  ff_out_req_cmd_opcode_r;
+    wire [2:0]  ff_out_req_cmd_size_r;
+    wire [7:0]  ff_out_req_cmd_len_r;
+    wire [7:0]  ff_out_req_cmd_atype_r;
+    wire [3:0]  ff_out_req_cmd_qos_r;
+    wire [1:0]  ff_out_req_cmd_prot_r;
+    wire        ff_out_req_cmd_eom_r;
+    wire        ff_out_req_cmd_eof_r;
+    wire        ff_out_req_cmd_ex_r;
+    wire [1:0]  ff_out_req_cmd_user_r;
+    wire [23:0] ff_out_req_cmd_user_extended_r;
+    wire [1:0]  ff_out_req_cmd_err_r;
+    wire [4:0]  ff_out_req_cmd_hostid_r;
+
+    umi_unpack #(
+        .CW     (CW)
+    ) umi2axilite_ff_req_r_unpack (
+        // Input CMD
+        .packet_cmd         (ff_out_req_cmd_r),
+
+        // Output Fields
+        .cmd_opcode         (ff_out_req_cmd_opcode_r),
+        .cmd_size           (ff_out_req_cmd_size_r),
+        .cmd_len            (ff_out_req_cmd_len_r),
+        .cmd_atype          (ff_out_req_cmd_atype_r),
+        .cmd_qos            (ff_out_req_cmd_qos_r),
+        .cmd_prot           (ff_out_req_cmd_prot_r),
+        .cmd_eom            (ff_out_req_cmd_eom_r),
+        .cmd_eof            (ff_out_req_cmd_eof_r),
+        .cmd_ex             (ff_out_req_cmd_ex_r),
+        .cmd_user           (ff_out_req_cmd_user_r),
+        .cmd_user_extended  (ff_out_req_cmd_user_extended_r),
+        .cmd_err            (ff_out_req_cmd_err_r),
+        .cmd_hostid         (ff_out_req_cmd_hostid_r)
+    );
+
+    // AXI write address bus
+    assign axi_awaddr   = ff_out_req_dstaddr_r;
+    assign axi_awprot   = {1'b0, ff_out_req_cmd_prot_r};
+    assign axi_awvalid  = axi_awvalid_r & reset_done;
+
+    // AXI write data bus
+    assign axi_wdata    = ff_out_req_data_shifted_r;
+    assign axi_wstrb    = ff_out_req_data_strb_r;
+    assign axi_wvalid   = axi_wvalid_r & reset_done;
+
+    // AXI read address bus
+    assign axi_araddr   = ff_out_req_dstaddr_r;
+    assign axi_arprot   = {1'b0, ff_out_req_cmd_prot_r};
+    assign axi_arvalid  = axi_arvalid_r & reset_done;
+
+    // One request at a time
+    reg                 umi_req_in_flight;
+    wire                umi_req_done;
+
+    assign umi_req_done = (ff_out_req_cmd_opcode_r == UMI_REQ_POSTED) ?
+                          (axi_bvalid & axi_bready) :
+                          (udev_resp_valid & udev_resp_ready);
+
+    always @(posedge clk or negedge nreset) begin
+        if (~nreset)
+            umi_req_in_flight <= 1'b0;
+        else if (ff_out_req_valid & ff_out_req_ready)
+            umi_req_in_flight <= 1'b1;
+        else if (umi_req_done)
+            umi_req_in_flight <= 1'b0;
+    end
+
+    assign ff_out_req_ready = !umi_req_in_flight & reset_done;
+
+    // AXI response
+    wire [4:0]  udev_resp_cmd_opcode;
+    wire [1:0]  udev_resp_cmd_err;
+
+    assign udev_resp_cmd_opcode = (ff_out_req_cmd_opcode_r == UMI_REQ_WRITE) ?
+                                  UMI_RESP_WRITE : UMI_RESP_READ;
+
+    assign udev_resp_cmd_err = (ff_out_req_cmd_opcode_r == UMI_REQ_WRITE) ?
+                               axi_bresp : axi_rresp;
+
+    umi_pack #(
+        .CW                 (CW)
+    ) umi_req_pack (
+        .cmd_opcode         (udev_resp_cmd_opcode),
+        .cmd_size           (ff_out_req_cmd_size_r),
+        .cmd_len            (ff_out_req_cmd_len_r),
+        .cmd_atype          (ff_out_req_cmd_atype_r),
+        .cmd_prot           (ff_out_req_cmd_prot_r),
+        .cmd_qos            (ff_out_req_cmd_qos_r),
+        .cmd_eom            (ff_out_req_cmd_eom_r),
+        .cmd_eof            (ff_out_req_cmd_eof_r),
+        .cmd_user           (ff_out_req_cmd_user_r),
+        .cmd_err            (udev_resp_cmd_err),
+        .cmd_ex             (ff_out_req_cmd_ex_r),
+        .cmd_hostid         (ff_out_req_cmd_hostid_r),
+        .cmd_user_extended  (ff_out_req_cmd_user_extended_r),
+
+        .packet_cmd         (udev_resp_cmd)
+    );
+
+    assign udev_resp_dstaddr = ff_out_req_srcaddr_r;
+    assign udev_resp_srcaddr = ff_out_req_dstaddr_r;
+    assign udev_resp_data = axi_rdata >> (req_data_shift_r << 3);
+    assign udev_resp_valid = (ff_out_req_cmd_opcode_r == UMI_REQ_WRITE) ?
+                             axi_bvalid : axi_rvalid;
+
+    // AXI write response ready
+    // Discard response in case of posted writes
+    assign axi_bready = udev_resp_ready &
+                        ((ff_out_req_cmd_opcode_r == UMI_REQ_WRITE) |
+                        (ff_out_req_cmd_opcode_r == UMI_REQ_POSTED));
+
+    // AXI read response ready
+    assign axi_rready = udev_resp_ready &
+                        (ff_out_req_cmd_opcode_r == UMI_REQ_READ);
+
+endmodule
diff --git a/utils/testbench/test_umi2axilite.py b/utils/testbench/test_umi2axilite.py
new file mode 100755
index 0000000..b6a3b99
--- /dev/null
+++ b/utils/testbench/test_umi2axilite.py
@@ -0,0 +1,99 @@
+#!/usr/bin/env python3
+
+# Copyright (C) 2023 Zero ASIC
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+import random
+import numpy as np
+from pathlib import Path
+from argparse import ArgumentParser
+from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
+from lambdalib import lambdalib
+
+THIS_DIR = Path(__file__).resolve().parent
+
+
+def build_testbench():
+    dut = SbDut('testbench', default_main=True)
+
+    EX_DIR = Path('../..')
+    EX_DIR = EX_DIR.resolve()
+
+    # Set up inputs
+    dut.input('testbench_umi2axilite.sv')
+
+    dut.use(lambdalib)
+    dut.add('option', 'ydir', 'lambdalib/ramlib/rtl', package='lambdalib')
+    dut.add('option', 'ydir', 'lambdalib/stdlib/rtl', package='lambdalib')
+    dut.add('option', 'ydir', 'lambdalib/padring/rtl', package='lambdalib')
+    dut.add('option', 'ydir', 'lambdalib/vectorlib/rtl', package='lambdalib')
+
+    for option in ['ydir', 'idir']:
+        dut.add('option', option, EX_DIR / 'umi' / 'rtl')
+        dut.add('option', option, EX_DIR / 'utils' / 'rtl')
+
+    # Verilator configuration
+    vlt_config = EX_DIR / 'utils' / 'testbench' / 'config.vlt'
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', vlt_config)
+    dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')
+#    dut.set('option', 'relax', True)
+#    dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
+#    dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')
+#    dut.add('tool', 'verilator', 'task', 'compile', 'option', '-DVL_DEBUG')
+
+    # Settings - enable tracing
+    dut.set('option', 'trace', True)
+    dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')
+
+    # Build simulator
+    dut.run()
+
+    return dut.find_result('vexe', step='compile')
+
+
+def main(vldmode="2", rdymode="2", host2dut="host2dut_0.q", dut2host="dut2host_0.q"):
+    # clean up old queues if present
+    for q in [host2dut, dut2host]:
+        delete_queue(q)
+
+    verilator_bin = build_testbench()
+
+    # launch the simulation
+    ret_val = verilator_run(verilator_bin, plusargs=['trace', ('valid_mode', vldmode), ('ready_mode', rdymode)])
+
+    # instantiate TX and RX queues.  note that these can be instantiated without
+    # specifying a URI, in which case the URI can be specified later via the
+    # "init" method
+
+    host = UmiTxRx(host2dut, dut2host)
+
+    print("### Statring test ###")
+
+    for count in range(1000):
+        # length should not cross the DW boundary - umi_mem_agent limitation
+        length = np.random.randint(0, 255)
+        dst_addr = 32*random.randrange(2**(10-5)-1)  # sb limitation - should align to bus width
+        src_addr = 32*random.randrange(2**(10-5)-1)
+        data8 = np.random.randint(0, 255, size=length, dtype=np.uint8)
+        print(f"[{count}] umi writing {length} bytes to addr 0x{dst_addr:08x}")
+        host.write(dst_addr, data8, srcaddr=src_addr, max_bytes=8)
+        print(f"[{count}] umi read from addr 0x{dst_addr:08x}")
+        val8 = host.read(dst_addr, length, np.uint8, srcaddr=src_addr, max_bytes=8)
+        if ~((val8 == data8).all()):
+            print(f"ERROR umi read from addr 0x{dst_addr:08x}")
+            print(f"Expected: {data8}")
+            print(f"Actual: {val8}")
+            assert (val8 == data8).all()
+
+    ret_val.wait()
+    print("### TEST PASS ###")
+
+
+if __name__ == '__main__':
+    parser = ArgumentParser()
+    parser.add_argument('--vldmode', default='2')
+    parser.add_argument('--rdymode', default='2')
+    args = parser.parse_args()
+
+    main(vldmode=args.vldmode,
+         rdymode=args.rdymode)
diff --git a/utils/testbench/testbench_umi2axilite.sv b/utils/testbench/testbench_umi2axilite.sv
new file mode 100644
index 0000000..68211a3
--- /dev/null
+++ b/utils/testbench/testbench_umi2axilite.sv
@@ -0,0 +1,297 @@
+/*******************************************************************************
+ * Copyright 2024 Zero ASIC Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----
+ *
+ * Documentation:
+ * - UMI to AXI4-Lite converter testbench
+ *
+ ******************************************************************************/
+
+
+`default_nettype none
+
+module testbench (
+    input clk
+);
+
+    localparam TIMEOUT  = 500000;
+    localparam DW       = 64;
+    localparam AW       = 64;
+    localparam CW       = 32;
+    localparam RAMDEPTH = 4096;  // param specific to testbench
+    localparam CTRLW    = 8;
+
+    wire        nreset;
+    reg [15:0]  nreset_r = 16'hFFFF;
+
+    assign nreset = ~nreset_r[15];
+
+    always @(negedge clk) begin
+        nreset_r <= nreset_r << 1;
+    end
+
+    wire            umi_req_valid;
+    wire [CW-1:0]   umi_req_cmd;
+    wire [AW-1:0]   umi_req_dstaddr;
+    wire [AW-1:0]   umi_req_srcaddr;
+    wire [DW-1:0]   umi_req_data;
+    wire            umi_req_ready;
+
+    // UMI agents
+    umi_rx_sim #(
+       .VALID_MODE_DEFAULT  (2),
+       .DW                  (DW)
+    ) umi_rx_i (
+        .clk                (clk),
+        .valid              (umi_req_valid),
+        .cmd                (umi_req_cmd),
+        .dstaddr            (umi_req_dstaddr),
+        .srcaddr            (umi_req_srcaddr),
+        .data               (umi_req_data),
+        .ready              (umi_req_ready)
+    );
+
+    wire            umi_resp_valid;
+    wire [CW-1:0]   umi_resp_cmd;
+    wire [AW-1:0]   umi_resp_dstaddr;
+    wire [AW-1:0]   umi_resp_srcaddr;
+    wire [DW-1:0]   umi_resp_data;
+    wire            umi_resp_ready;
+
+    umi_tx_sim #(
+        .READY_MODE_DEFAULT (2),
+        .DW                 (DW)
+    ) umi_tx_i (
+        .clk                (clk),
+        .valid              (umi_resp_valid),
+        .cmd                (umi_resp_cmd),
+        .dstaddr            (umi_resp_dstaddr),
+        .srcaddr            (umi_resp_srcaddr),
+        .data               (umi_resp_data),
+        .ready              (umi_resp_ready)
+    );
+
+    // Converters
+    wire [AW-1:0]       axi_awaddr;
+    wire [2:0]          axi_awprot;
+    wire                axi_awvalid;
+    wire                axi_awready;
+
+    wire [DW-1:0]       axi_wdata;
+    wire [(DW/8)-1:0]   axi_wstrb;
+    wire                axi_wvalid;
+    wire                axi_wready;
+
+    wire [1:0]          axi_bresp;
+    wire                axi_bvalid;
+    wire                axi_bready;
+
+    wire [AW-1:0]       axi_araddr;
+    wire [2:0]          axi_arprot;
+    wire                axi_arvalid;
+    wire                axi_arready;
+
+    wire [DW-1:0]       axi_rdata;
+    wire [1:0]          axi_rresp;
+    wire                axi_rvalid;
+    wire                axi_rready;
+
+    wire                umi_mem_req_valid;
+    wire [CW-1:0]       umi_mem_req_cmd;
+    wire [AW-1:0]       umi_mem_req_dstaddr;
+    wire [AW-1:0]       umi_mem_req_srcaddr;
+    wire [DW-1:0]       umi_mem_req_data;
+    wire                umi_mem_req_ready;
+
+    wire                umi_mem_resp_valid;
+    wire [CW-1:0]       umi_mem_resp_cmd;
+    wire [AW-1:0]       umi_mem_resp_dstaddr;
+    wire [AW-1:0]       umi_mem_resp_srcaddr;
+    wire [DW-1:0]       umi_mem_resp_data;
+    wire                umi_mem_resp_ready;
+
+    // UMI to AXI4-Lite
+    umi2axilite #(
+        .CW     (CW),
+        .AW     (AW),
+        .DW     (DW)
+    ) umi2axilite_ (
+        .clk                (clk),
+        .nreset             (nreset),
+
+        // UMI Device port
+        .udev_req_valid     (umi_req_valid),
+        .udev_req_cmd       (umi_req_cmd),
+        .udev_req_dstaddr   (umi_req_dstaddr),
+        .udev_req_srcaddr   (umi_req_srcaddr),
+        .udev_req_data      (umi_req_data),
+        .udev_req_ready     (umi_req_ready),
+
+        .udev_resp_valid    (umi_resp_valid),
+        .udev_resp_cmd      (umi_resp_cmd),
+        .udev_resp_dstaddr  (umi_resp_dstaddr),
+        .udev_resp_srcaddr  (umi_resp_srcaddr),
+        .udev_resp_data     (umi_resp_data),
+        .udev_resp_ready    (umi_resp_ready),
+
+        // AXI4Lite Interface
+        .axi_awaddr         (axi_awaddr),
+        .axi_awprot         (axi_awprot),
+        .axi_awvalid        (axi_awvalid),
+        .axi_awready        (axi_awready),
+
+        .axi_wdata          (axi_wdata),
+        .axi_wstrb          (axi_wstrb),
+        .axi_wvalid         (axi_wvalid),
+        .axi_wready         (axi_wready),
+
+        .axi_bresp          (axi_bresp),
+        .axi_bvalid         (axi_bvalid),
+        .axi_bready         (axi_bready),
+
+        .axi_araddr         (axi_araddr),
+        .axi_arprot         (axi_arprot),
+        .axi_arvalid        (axi_arvalid),
+        .axi_arready        (axi_arready),
+
+        .axi_rdata          (axi_rdata),
+        .axi_rresp          (axi_rresp),
+        .axi_rvalid         (axi_rvalid),
+        .axi_rready         (axi_rready)
+    );
+
+    // UMI to AXI4-Lite
+    axilite2umi #(
+        .CW     (),
+        .AW     (),
+        .DW     (),
+        .IDW    ()
+    ) axilite2umi_ (
+        .clk                (clk),
+        .nreset             (nreset),
+
+        // FIXME: The bottom 4 bits of chipid are kept 4'b0001.
+        // This hack is to ensure that the memory agent responds on its UMI(0,0)
+        // This needs to be fixed either by using a correct address map or
+        // enabling all 4 ports. Priority is low.
+        .chipid             (16'hAE51),
+        .local_routing      (16'hDEAD),
+
+        // AXI4Lite Interface
+        .axi_awaddr         (axi_awaddr),
+        .axi_awprot         (axi_awprot),
+        .axi_awvalid        (axi_awvalid),
+        .axi_awready        (axi_awready),
+
+        .axi_wdata          (axi_wdata),
+        .axi_wstrb          (axi_wstrb),
+        .axi_wvalid         (axi_wvalid),
+        .axi_wready         (axi_wready),
+
+        .axi_bresp          (axi_bresp),
+        .axi_bvalid         (axi_bvalid),
+        .axi_bready         (axi_bready),
+
+        .axi_araddr         (axi_araddr),
+        .axi_arprot         (axi_arprot),
+        .axi_arvalid        (axi_arvalid),
+        .axi_arready        (axi_arready),
+
+        .axi_rdata          (axi_rdata),
+        .axi_rresp          (axi_rresp),
+        .axi_rvalid         (axi_rvalid),
+        .axi_rready         (axi_rready),
+
+        // Host port (per clink)
+        .uhost_req_valid    (umi_mem_req_valid),
+        .uhost_req_cmd      (umi_mem_req_cmd),
+        .uhost_req_dstaddr  (umi_mem_req_dstaddr),
+        .uhost_req_srcaddr  (umi_mem_req_srcaddr),
+        .uhost_req_data     (umi_mem_req_data),
+        .uhost_req_ready    (umi_mem_req_ready),
+
+        .uhost_resp_valid   (umi_mem_resp_valid),
+        .uhost_resp_cmd     (umi_mem_resp_cmd),
+        .uhost_resp_dstaddr (umi_mem_resp_dstaddr),
+        .uhost_resp_srcaddr (umi_mem_resp_srcaddr),
+        .uhost_resp_data    (umi_mem_resp_data),
+        .uhost_resp_ready   (umi_mem_resp_ready)
+    );
+
+    wire [CTRLW-1:0]    sram_ctrl = 8'b0;
+
+    umi_mem_agent #(
+        .DW                 (DW),
+        .AW                 (AW),
+        .CW                 (CW),
+        .CTRLW              (CTRLW),
+        .RAMDEPTH           (RAMDEPTH)
+    ) memory_module_ (
+        .clk                (clk),
+        .nreset             (nreset),
+
+        .sram_ctrl          (sram_ctrl),
+
+        .udev_req_valid     (umi_mem_req_valid),
+        .udev_req_cmd       (umi_mem_req_cmd),
+        .udev_req_dstaddr   (umi_mem_req_dstaddr),
+        .udev_req_srcaddr   (umi_mem_req_srcaddr),
+        .udev_req_data      (umi_mem_req_data),
+        .udev_req_ready     (umi_mem_req_ready),
+
+        .udev_resp_valid    (umi_mem_resp_valid),
+        .udev_resp_cmd      (umi_mem_resp_cmd),
+        .udev_resp_dstaddr  (umi_mem_resp_dstaddr),
+        .udev_resp_srcaddr  (umi_mem_resp_srcaddr),
+        .udev_resp_data     (umi_mem_resp_data),
+        .udev_resp_ready    (umi_mem_resp_ready)
+    );
+
+    // Initialize UMI
+    integer valid_mode, ready_mode;
+
+    initial begin
+        /* verilator lint_off IGNOREDRETURN */
+        if (!$value$plusargs("valid_mode=%d", valid_mode)) begin
+           valid_mode = 2;  // default if not provided as a plusarg
+        end
+
+        if (!$value$plusargs("ready_mode=%d", ready_mode)) begin
+           ready_mode = 2;  // default if not provided as a plusarg
+        end
+
+        umi_rx_i.init("host2dut_0.q");
+        umi_rx_i.set_valid_mode(valid_mode);
+
+        umi_tx_i.init("dut2host_0.q");
+        umi_tx_i.set_ready_mode(ready_mode);
+        /* verilator lint_on IGNOREDRETURN */
+    end
+
+    // VCD
+    initial begin
+        if ($test$plusargs("trace")) begin
+            $dumpfile("testbench.fst");
+            $dumpvars(0, testbench);
+        end
+    end
+
+    // auto-stop
+    auto_stop_sim #(.CYCLES(TIMEOUT)) auto_stop_sim_i (.clk(clk));
+
+endmodule
+
+`default_nettype wire

From da100eeef72ec7fb91fa24087774c666a18e8de9 Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Tue, 12 Mar 2024 12:51:48 -0400
Subject: [PATCH 5/8] Minor Fixes

---
 utils/testbench/testbench_umi2axilite.sv | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/utils/testbench/testbench_umi2axilite.sv b/utils/testbench/testbench_umi2axilite.sv
index 68211a3..55573e4 100644
--- a/utils/testbench/testbench_umi2axilite.sv
+++ b/utils/testbench/testbench_umi2axilite.sv
@@ -173,12 +173,12 @@ module testbench (
         .axi_rready         (axi_rready)
     );
 
-    // UMI to AXI4-Lite
+    // AXI4-Lite to UMI
     axilite2umi #(
-        .CW     (),
-        .AW     (),
-        .DW     (),
-        .IDW    ()
+        .CW     (CW),
+        .AW     (AW),
+        .DW     (DW),
+        .IDW    (16)
     ) axilite2umi_ (
         .clk                (clk),
         .nreset             (nreset),

From a0fa0e0e2890d4891becb5828b31c87eca07ab10 Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Tue, 12 Mar 2024 13:21:51 -0400
Subject: [PATCH 6/8] Update umi2axilite test

---
 umi/utils/testbench/test_umi2axilite.py | 33 ++++++++-----------------
 1 file changed, 10 insertions(+), 23 deletions(-)

diff --git a/umi/utils/testbench/test_umi2axilite.py b/umi/utils/testbench/test_umi2axilite.py
index b6a3b99..223e8c1 100755
--- a/umi/utils/testbench/test_umi2axilite.py
+++ b/umi/utils/testbench/test_umi2axilite.py
@@ -5,41 +5,28 @@
 
 import random
 import numpy as np
-from pathlib import Path
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-from lambdalib import lambdalib
-
-THIS_DIR = Path(__file__).resolve().parent
+import umi
 
 
 def build_testbench():
     dut = SbDut('testbench', default_main=True)
 
-    EX_DIR = Path('../..')
-    EX_DIR = EX_DIR.resolve()
-
     # Set up inputs
-    dut.input('testbench_umi2axilite.sv')
-
-    dut.use(lambdalib)
-    dut.add('option', 'ydir', 'lambdalib/ramlib/rtl', package='lambdalib')
-    dut.add('option', 'ydir', 'lambdalib/stdlib/rtl', package='lambdalib')
-    dut.add('option', 'ydir', 'lambdalib/padring/rtl', package='lambdalib')
-    dut.add('option', 'ydir', 'lambdalib/vectorlib/rtl', package='lambdalib')
+    dut.input('utils/testbench/testbench_umi2axilite.sv', package='umi')
 
-    for option in ['ydir', 'idir']:
-        dut.add('option', option, EX_DIR / 'umi' / 'rtl')
-        dut.add('option', option, EX_DIR / 'utils' / 'rtl')
+    dut.use(umi)
+    dut.add('option', 'library', 'umi')
+    dut.add('option', 'library', 'lambdalib_ramlib')
+    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration
-    vlt_config = EX_DIR / 'utils' / 'testbench' / 'config.vlt'
-    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', vlt_config)
+    dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config',
+            'utils/testbench/config.vlt',
+            package='umi')
     dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')
-#    dut.set('option', 'relax', True)
-#    dut.add('tool', 'verilator', 'task', 'compile', 'option', '--prof-cfuncs')
-#    dut.add('tool', 'verilator', 'task', 'compile', 'option', '-CFLAGS')
-#    dut.add('tool', 'verilator', 'task', 'compile', 'option', '-DVL_DEBUG')
 
     # Settings - enable tracing
     dut.set('option', 'trace', True)

From 1e315a791190a63cb32984149d968a6390e31e1c Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Tue, 12 Mar 2024 13:54:43 -0400
Subject: [PATCH 7/8] Fix testbench

---
 umi/utils/testbench/tb_axilite2umi.v | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/umi/utils/testbench/tb_axilite2umi.v b/umi/utils/testbench/tb_axilite2umi.v
index 44f14c9..8e1cc21 100644
--- a/umi/utils/testbench/tb_axilite2umi.v
+++ b/umi/utils/testbench/tb_axilite2umi.v
@@ -278,15 +278,6 @@ module tb_axilite2umi #(
         end
     end
 
-    //always @(posedge clk) begin
-    //    if (axi_awvalid & axi_awready)
-    //        $display("Writing data to: 0x%h", axi_awaddr);
-    //    if (axi_wvalid & axi_wready)
-    //        $display("Data written: 0x%h, strobe: 0b%b", axi_wdata, axi_wstrb);
-    //    if (axi_arvalid & axi_arready)
-    //        $display("Reading data from: 0x%h", axi_araddr);
-    //end
-
     // Perf Counters
     wire        axi_awcommit;
     wire        axi_wcommit;

From 2162b2f56818fd88c2bfbcf8d5e9253da7f82ea2 Mon Sep 17 00:00:00 2001
From: azaidy <zaidy.ali@gmail.com>
Date: Tue, 12 Mar 2024 14:18:04 -0400
Subject: [PATCH 8/8] ID name update

---
 umi/utils/rtl/axilite2umi.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/umi/utils/rtl/axilite2umi.v b/umi/utils/rtl/axilite2umi.v
index 33821d7..3f4c38b 100644
--- a/umi/utils/rtl/axilite2umi.v
+++ b/umi/utils/rtl/axilite2umi.v
@@ -26,7 +26,7 @@ module axilite2umi #(
     parameter CW    = 32,   // command width
     parameter AW    = 64,   // address width
     parameter DW    = 64,   // umi packet width
-    parameter IDW   = 16    // brick ID width
+    parameter IDW   = 16    // chip ID width
 )
 (
     input               clk,