From 8567be11c3aba12977390839b08198ca7df42e97 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 15 Feb 2024 22:22:55 -0500 Subject: [PATCH 1/5] add basic CI test to run lumi testbenches --- .github/dependabot.yml | 11 +++++++++++ .github/workflows/ci.yml | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 .github/dependabot.yml create mode 100644 .github/workflows/ci.yml diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 0000000..6c4b369 --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,11 @@ +version: 2 +updates: + # Maintain dependencies for GitHub Actions + - package-ecosystem: "github-actions" + directory: "/" + schedule: + interval: "weekly" + groups: + actions: + patterns: + - "*" diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 0000000..43e7ed1 --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,38 @@ +name: Testbench CI +on: + push: + # Runs on all PRs + pull_request: + # Manual Dispatch + workflow_dispatch: + +jobs: + testbench: + strategy: + fail-fast: false + matrix: + testbench: [lumi/testbench/test_lumi.py, lumi/testbench/test_lumi_rnd.py] + + timeout-minutes: 30 + runs-on: ubuntu-latest + container: + image: ghcr.io/zeroasiccorp/sbtest:latest + + steps: + - name: Check out UMI + uses: actions/checkout@v4 + with: + submodules: recursive + + - name: Install requirements + run: | + python3 -m venv .venv + . .venv/bin/activate + python3 -m pip install --upgrade pip + python3 -m pip install switchboard-hw + + - name: Run ${{ matrix.testbench }} + run: | + . .venv/bin/activate + cd $(dirname "${{ matrix.testbench }}") + ./$(basename "${{ matrix.testbench }}") From 2896edddb877d80facba1868aa46c3a15b784b93 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 15 Feb 2024 22:36:00 -0500 Subject: [PATCH 2/5] add all testbenches and fix lambdalib paths --- .github/workflows/ci.yml | 4 ++-- lumi/testbench/test_lumi_rnd.py | 3 +-- umi/testbench/test_crossbar.py | 6 +++--- umi/testbench/test_fifo.py | 6 +++--- umi/testbench/test_fifo_flex.py | 6 +++--- umi/testbench/test_mem_agent.py | 6 +++--- umi/testbench/test_regif.py | 6 +++--- utils/testbench/test_umi2tl_np.py | 8 ++++---- utils/testbench/test_umi_address_remap.py | 8 ++++---- utils/testbench/test_umi_packet_merge_greedy.py | 8 ++++---- 10 files changed, 30 insertions(+), 31 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 43e7ed1..7530f0f 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -11,9 +11,9 @@ jobs: strategy: fail-fast: false matrix: - testbench: [lumi/testbench/test_lumi.py, lumi/testbench/test_lumi_rnd.py] + testbench: [lumi/testbench/test_lumi.py, lumi/testbench/test_lumi_rnd.py, umi/testbench/test_crossbar.py, umi/testbench/test_fifo_flex.py, umi/testbench/test_fifo.py, umi/testbench/test_mem_agent.py, umi/testbench/test_regif.py, utils/testbench/test_umi_address_remap.py, utils/testbench/test_umi_packet_merge_greedy.py, utils/testbench/test_umi2tl_np.py] - timeout-minutes: 30 + timeout-minutes: 10 runs-on: ubuntu-latest container: image: ghcr.io/zeroasiccorp/sbtest:latest diff --git a/lumi/testbench/test_lumi_rnd.py b/lumi/testbench/test_lumi_rnd.py index b873725..79d55b1 100755 --- a/lumi/testbench/test_lumi_rnd.py +++ b/lumi/testbench/test_lumi_rnd.py @@ -67,8 +67,7 @@ def main(topo="2d", vldmode="2", rdymode="2", trace=False, host2dut="host2dut_0. ('hostdly', hostdly), ('devdly', devdly) ], - trace=trace, - args=['+verilator+seed+0'] + trace=trace ) # instantiate TX and RX queues. note that these can be instantiated without diff --git a/umi/testbench/test_crossbar.py b/umi/testbench/test_crossbar.py index 7a30d70..2c41224 100755 --- a/umi/testbench/test_crossbar.py +++ b/umi/testbench/test_crossbar.py @@ -26,9 +26,9 @@ def build_testbench(): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration vlt_config = EX_DIR / 'testbench' / 'config.vlt' diff --git a/umi/testbench/test_fifo.py b/umi/testbench/test_fifo.py index 4a8b7f0..46ae18f 100755 --- a/umi/testbench/test_fifo.py +++ b/umi/testbench/test_fifo.py @@ -25,9 +25,9 @@ def build_testbench(): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration vlt_config = EX_DIR / 'testbench' / 'config.vlt' diff --git a/umi/testbench/test_fifo_flex.py b/umi/testbench/test_fifo_flex.py index cb2c57e..a15b21f 100755 --- a/umi/testbench/test_fifo_flex.py +++ b/umi/testbench/test_fifo_flex.py @@ -25,9 +25,9 @@ def build_testbench(): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration vlt_config = EX_DIR / 'testbench' / 'config.vlt' diff --git a/umi/testbench/test_mem_agent.py b/umi/testbench/test_mem_agent.py index 0022c4f..bc61572 100755 --- a/umi/testbench/test_mem_agent.py +++ b/umi/testbench/test_mem_agent.py @@ -25,9 +25,9 @@ def build_testbench(): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration vlt_config = EX_DIR / 'testbench' / 'config.vlt' diff --git a/umi/testbench/test_regif.py b/umi/testbench/test_regif.py index b2dee2b..9c209cb 100755 --- a/umi/testbench/test_regif.py +++ b/umi/testbench/test_regif.py @@ -25,9 +25,9 @@ def build_testbench(): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration vlt_config = EX_DIR / 'testbench' / 'config.vlt' diff --git a/utils/testbench/test_umi2tl_np.py b/utils/testbench/test_umi2tl_np.py index 3c4d555..c4936a4 100644 --- a/utils/testbench/test_umi2tl_np.py +++ b/utils/testbench/test_umi2tl_np.py @@ -32,10 +32,10 @@ def build_testbench(topo="2d"): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'umi' / 'rtl') dut.add('option', option, EX_DIR / 'utils' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'padring' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'padring' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration dut.add('tool', 'verilator', 'task', 'compile', 'option', '--coverage') diff --git a/utils/testbench/test_umi_address_remap.py b/utils/testbench/test_umi_address_remap.py index 7144aa7..d98a016 100644 --- a/utils/testbench/test_umi_address_remap.py +++ b/utils/testbench/test_umi_address_remap.py @@ -30,10 +30,10 @@ def build_testbench(topo="2d"): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'umi' / 'rtl') dut.add('option', option, EX_DIR / 'utils' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'padring' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'padring' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration vlt_config = EX_DIR / 'utils' / 'testbench' / 'config.vlt' diff --git a/utils/testbench/test_umi_packet_merge_greedy.py b/utils/testbench/test_umi_packet_merge_greedy.py index 367bcda..0474f7a 100644 --- a/utils/testbench/test_umi_packet_merge_greedy.py +++ b/utils/testbench/test_umi_packet_merge_greedy.py @@ -30,10 +30,10 @@ def build_testbench(topo="2d"): for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'umi' / 'rtl') dut.add('option', option, EX_DIR / 'utils' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'ramlib' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'stdlib' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'padring' / 'rtl') - dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'vectorlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'padring' / 'rtl') + dut.add('option', option, EX_DIR / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') # Verilator configuration vlt_config = EX_DIR / 'utils' / 'testbench' / 'config.vlt' From ff5974555b5ec85687c2beb20d6974a01c27cba2 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 15 Feb 2024 22:38:30 -0500 Subject: [PATCH 3/5] fix permissions on testbenches --- utils/testbench/test_umi2tl_np.py | 0 utils/testbench/test_umi_address_remap.py | 0 utils/testbench/test_umi_packet_merge_greedy.py | 0 3 files changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 utils/testbench/test_umi2tl_np.py mode change 100644 => 100755 utils/testbench/test_umi_address_remap.py mode change 100644 => 100755 utils/testbench/test_umi_packet_merge_greedy.py diff --git a/utils/testbench/test_umi2tl_np.py b/utils/testbench/test_umi2tl_np.py old mode 100644 new mode 100755 diff --git a/utils/testbench/test_umi_address_remap.py b/utils/testbench/test_umi_address_remap.py old mode 100644 new mode 100755 diff --git a/utils/testbench/test_umi_packet_merge_greedy.py b/utils/testbench/test_umi_packet_merge_greedy.py old mode 100644 new mode 100755 From 99ba57319e0a1331a032643990add86667b2d32d Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 15 Feb 2024 22:51:27 -0500 Subject: [PATCH 4/5] automatically collect tests --- .github/workflows/bin/collect_tests.py | 16 ++++++++++++++++ .github/workflows/ci.yml | 25 +++++++++++++++++++++---- 2 files changed, 37 insertions(+), 4 deletions(-) create mode 100644 .github/workflows/bin/collect_tests.py diff --git a/.github/workflows/bin/collect_tests.py b/.github/workflows/bin/collect_tests.py new file mode 100644 index 0000000..74946cc --- /dev/null +++ b/.github/workflows/bin/collect_tests.py @@ -0,0 +1,16 @@ +import json +import os + + +if __name__ == "__main__": + script_dir = os.path.dirname(os.path.abspath(__file__)) + repo_dir = os.path.abspath(os.path.join(script_dir, '..', '..', '..')) + tests = [] + for dirpath, dirnames, filenames in os.walk(repo_dir): + for f in filenames: + if f.startswith("test_"): + tests.append(os.path.join(dirpath, f)) + + tests_rel = [os.path.relpath(p, repo_dir) for p in tests] + + print(json.dumps({"testbench": tests_rel})) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 7530f0f..daaf5fc 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,12 +7,29 @@ on: workflow_dispatch: jobs: + get_testbenches: + name: 'Get testbenches' + + runs-on: ubuntu-latest + + outputs: + testbenches: ${{ steps.tests.outputs.tests }} + + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Collect testbenches + id: tests + run: | + echo "tests=$(python3 .github/workflows/bin/collect_tests.py)" >> $GITHUB_OUTPUT + testbench: + needs: get_testbenches strategy: fail-fast: false - matrix: - testbench: [lumi/testbench/test_lumi.py, lumi/testbench/test_lumi_rnd.py, umi/testbench/test_crossbar.py, umi/testbench/test_fifo_flex.py, umi/testbench/test_fifo.py, umi/testbench/test_mem_agent.py, umi/testbench/test_regif.py, utils/testbench/test_umi_address_remap.py, utils/testbench/test_umi_packet_merge_greedy.py, utils/testbench/test_umi2tl_np.py] - + matrix: ${{ fromJson(needs.get_testbenches.outputs.testbenches) }} + timeout-minutes: 10 runs-on: ubuntu-latest container: @@ -23,7 +40,7 @@ jobs: uses: actions/checkout@v4 with: submodules: recursive - + - name: Install requirements run: | python3 -m venv .venv From f620ef2079059655fd5d4426b044f7a08ad8583c Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 15 Feb 2024 22:54:07 -0500 Subject: [PATCH 5/5] remove on push --- .github/workflows/ci.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index daaf5fc..13882e9 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,6 +1,5 @@ name: Testbench CI on: - push: # Runs on all PRs pull_request: # Manual Dispatch