From 709b4cf50d7f09dc026d4693d17bc41da30f0e4d Mon Sep 17 00:00:00 2001
From: Yi Zhang <zhangyiant@hotmail.com>
Date: Tue, 27 Jul 2021 21:07:15 +0800
Subject: [PATCH 1/2] Add RWP access type.

---
 excels/block1.xlsx                            | Bin 11940 -> 12004 bytes
 register_printer/constants/__init__.py        |   2 +-
 .../generators/rtl_generator/print_rtl.py     |   4 ++
 register_printer/templates/reg_model.sv       |   4 ++
 register_printer/templates/reg_rtl.sv         |  54 ++++++++++--------
 5 files changed, 40 insertions(+), 24 deletions(-)

diff --git a/excels/block1.xlsx b/excels/block1.xlsx
index 078d91da15c2fbe8eeb2a4e153a99ff03ead12b9..5d62659eb30a12789b2dc9694f13f47bd1a47b2f 100644
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diff --git a/register_printer/constants/__init__.py b/register_printer/constants/__init__.py
index 523a8b2..dc511d3 100644
--- a/register_printer/constants/__init__.py
+++ b/register_printer/constants/__init__.py
@@ -1,4 +1,4 @@
-RW_TYPES = ['RW', 'RO', 'WO', 'RS', 'W1C', "W0C", 'RC', 'WRC', 'WRS', 'WSC', 'WC', '-']
+RW_TYPES = ['RW', 'RWP', 'RO', 'WO', 'RS', 'W1C', "W0C", 'RC', 'WRC', 'WRS', 'WSC', 'WC', '-']
 
 __all__ = [
     RW_TYPES
diff --git a/register_printer/generators/rtl_generator/print_rtl.py b/register_printer/generators/rtl_generator/print_rtl.py
index 606fe3e..c911f6c 100644
--- a/register_printer/generators/rtl_generator/print_rtl.py
+++ b/register_printer/generators/rtl_generator/print_rtl.py
@@ -26,6 +26,7 @@ def print_rtl_block(block, out_path):
         tmp_register["name"] = reg.name
         tmp_register["fields"] = []
         rw_flds = []
+        rwp_flds = []
         ro_flds = []
         rc_flds = []
         rs_flds = []
@@ -40,6 +41,8 @@ def print_rtl_block(block, out_path):
             tmp_register["fields"].append(fld)
             if fld.access == "RW":
                 rw_flds.append(fld)
+            elif fld.access == "RWP":
+                rwp_flds.append(fld)
             elif fld.access == "RC":
                 rc_flds.append(fld)
             elif fld.access == "RO":
@@ -61,6 +64,7 @@ def print_rtl_block(block, out_path):
             elif fld.access == "-":
                 ro_flds.append(fld)
         tmp_register["rw_flds"] = rw_flds
+        tmp_register["rwp_flds"] = rwp_flds
         tmp_register["ro_flds"] = ro_flds
         tmp_register["rc_flds"] = rc_flds
         tmp_register["rs_flds"] = rs_flds
diff --git a/register_printer/templates/reg_model.sv b/register_printer/templates/reg_model.sv
index 4762d6e..1db95e5 100644
--- a/register_printer/templates/reg_model.sv
+++ b/register_printer/templates/reg_model.sv
@@ -21,8 +21,12 @@ class {{ uvm_reg_type }} extends uvm_reg;
     {% if field.name != "-" %}
     {% set field_size = field.msb - field.lsb + 1 %}
     {{ field.name | lower }} = uvm_reg_field::type_id::create("{{ field.name | lower }}");
+    {% if field.access == "RWP" %}
+    {{ field.name | lower }}.configure(this, {{ field_size }}, {{ field.lsb }}, "RW", 0, {{ field_size }}'h{{ '%x' | format(field.default) }}, 1, 1, 1);
+    {% else %}
     {{ field.name | lower }}.configure(this, {{ field_size }}, {{ field.lsb }}, "{{ field.access }}", 0, {{ field_size }}'h{{ '%x' | format(field.default) }}, 1, 1, 1);
     {% endif %}
+    {% endif %}
   {% endfor %}
   endfunction: build
 
diff --git a/register_printer/templates/reg_rtl.sv b/register_printer/templates/reg_rtl.sv
index e82bcfe..5aa17d9 100644
--- a/register_printer/templates/reg_rtl.sv
+++ b/register_printer/templates/reg_rtl.sv
@@ -5,11 +5,14 @@ module {{ block.block_type }}_reg
 (
     input     reg_clk                                                       ,
     input     reg_rstn                                                      ,
+    input     wp_dis                                                        ,
 {% for register in block.registers %}
   {% for field in register.fields %}
     {% set field_bits = field.msb - field.lsb %}
     {% if field.access == "RW" %}
     output logic[{{ '%2s' | format(field_bits) }}: 0]     {{ "%-48s" | format(field.name) }},
+    {% elif field.access == "RWP" %}
+    output logic[{{ '%2s' | format(field_bits) }}: 0]     {{ "%-48s" | format(field.name) }},
     {% elif field.access == "RC" %}
     input       [{{ '%2s' | format(field_bits) }}: 0]     {{ "%-48s" | format(field.name) }},
     {% elif field.access == "RO" %}
@@ -54,7 +57,7 @@ localparam int {{ (register.name + "_addr") | upper }} = 'h{{ "%x" | format(regi
 {% endfor %}
 
 {% for register in registers %}
-{% if (register.rw_flds | length ) + (register.rc_flds | length) + (register.rs_flds | length) + (register.w1c_flds | length) + (register.w0c_flds | length) + (register.wc_flds | length) + (register.wo_flds | length) + (register.wrc_flds | length) + (register.wrs_flds | length)  > 0 %}
+{% if (register.rw_flds | length ) + (register.rwp_flds | length ) + (register.rc_flds | length) + (register.rs_flds | length) + (register.w1c_flds | length) + (register.w0c_flds | length) + (register.wc_flds | length) + (register.wo_flds | length) + (register.wrc_flds | length) + (register.wrs_flds | length)  > 0 %}
 always @(posedge reg_clk or negedge reg_rstn) begin
     if(~reg_rstn) begin
     {% for field in register.fields %}
@@ -74,7 +77,7 @@ always @(posedge reg_clk or negedge reg_rstn) begin
       {% endfor %}
     end
     {% endif %}
-    {% if (register.rw_flds | length) + (register.wo_flds | length) + (register.wrc_flds | length) + (register.wrs_flds | length) + (register.rc_flds | length) + (register.rs_flds | length) + (register.w1c_flds | length) + (register.w0c_flds | length) + (register.wc_flds | length) > 0 %}
+    {% if (register.rw_flds | length) + (register.rwp_flds | length) + (register.wo_flds | length) + (register.wrc_flds | length) + (register.wrs_flds | length) + (register.rc_flds | length) + (register.rs_flds | length) + (register.w1c_flds | length) + (register.w0c_flds | length) + (register.wc_flds | length) > 0 %}
     else begin
       {% for field in (register.rc_flds + register.rs_flds) %}
         {{ register.name }}[{{ field.msb }}:{{ field.lsb }}] <= {{ field.name }}
@@ -91,7 +94,7 @@ always @(posedge reg_clk or negedge reg_rstn) begin
       {% set pos = (field.msb / 8) | int %}
         {{ register.name }}[{{ field.msb }}] <= {{ field.name | lower }}_set ? 1'b1 : ((reg_wr && reg_addr=={{ (register.name + "_addr") | upper }} && reg_we[{{ pos }}]) ? 1'b0 : {{ register.name }}[{{ field.msb }}]);
       {% endfor %}
-      {% for field in (register.rw_flds + register.wrc_flds + register.wrs_flds + register.wo_flds) %}
+      {% for field in (register.rw_flds + register.rwp_flds + register.wrc_flds + register.wrs_flds + register.wo_flds) %}
       {% set msb = field.msb %}
       {% set lsb = field.lsb %}
       {% set reg_name = register.name %}
@@ -135,41 +138,46 @@ always @(posedge reg_clk or negedge reg_rstn) begin
             {% endif %}
           {% endif %}
         {% else %}
+          {% if field.access == "RWP" %}
+            {% set RWP_CONTENT = " && wp_dis" %}
+          {% else %}
+            {% set RWP_CONTENT = "" %}
+          {% endif %}
           {% if msb < 8 %}
-        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
           {% elif msb < 16 %}
             {% if lsb < 8 %}
-        {{ reg_name }}[{{ msb }}:8] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]) ? reg_wdat[{{ msb }}:8] : {{ reg_name }}[{{ msb }}:8];
-        {{ reg_name }}[7:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]) ? reg_wdat[7:{{ lsb }}] : {{ reg_name }}[7:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:8] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:8] : {{ reg_name }}[{{ msb }}:8];
+        {{ reg_name }}[7:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]{{ RWP_CONTENT }}) ? reg_wdat[7:{{ lsb }}] : {{ reg_name }}[7:{{ lsb }}];
             {% else %}
-        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
             {% endif %}
           {% elif msb < 24 %}
             {% if lsb < 8 %}
-        {{ reg_name }}[{{ msb }}:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]) ? reg_wdat[{{ msb }}:16] : {{ reg_name }}[{{ msb }}:16];
+        {{ reg_name }}[{{ msb }}:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:16] : {{ reg_name }}[{{ msb }}:16];
         {{ reg_name }}[15:8] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]) ? reg_wdat[15:8] : {{ reg_name }}[15:8];
-        {{ reg_name }}[7:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]) ? reg_wdat[7:{{ lsb }}] : {{ reg_name }}[7:{{ lsb }}];
+        {{ reg_name }}[7:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]{{ RWP_CONTENT }}) ? reg_wdat[7:{{ lsb }}] : {{ reg_name }}[7:{{ lsb }}];
             {% elif lsb < 16 %}
-        {{ reg_name }}[{{ msb }}:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]) ? reg_wdat[{{ msb }}:16] : {{ reg_name }}[{{ msb }}:16];
-        {{ reg_name }}[15:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]) ? reg_wdat[15:{{ lsb }}] : {{ reg_name }}[15:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:16] : {{ reg_name }}[{{ msb }}:16];
+        {{ reg_name }}[15:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]{{ RWP_CONTENT }}) ? reg_wdat[15:{{ lsb }}] : {{ reg_name }}[15:{{ lsb }}];
             {% else %}
-        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
             {% endif %}
           {% else %}
             {% if lsb < 8 %}
-        {{ reg_name }}[{{ msb }}:24] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]) ? reg_wdat[{{ msb }}:24] : {{ reg_name }}[{{ msb }}:24];
-        {{ reg_name }}[23:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]) ? reg_wdat[23:16] : {{ reg_name }}[23:16];
-        {{ reg_name }}[15:8] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]) ? reg_wdat[15:8] : {{ reg_name }}[15:8];
-        {{ reg_name }}[7:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]) ? reg_wdat[7:{{ lsb }}] : {{ reg_name }}[7:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:24] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:24] : {{ reg_name }}[{{ msb }}:24];
+        {{ reg_name }}[23:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]{{ RWP_CONTENT }}) ? reg_wdat[23:16] : {{ reg_name }}[23:16];
+        {{ reg_name }}[15:8] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]{{ RWP_CONTENT }}) ? reg_wdat[15:8] : {{ reg_name }}[15:8];
+        {{ reg_name }}[7:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[0]{{ RWP_CONTENT }}) ? reg_wdat[7:{{ lsb }}] : {{ reg_name }}[7:{{ lsb }}];
             {% elif lsb < 16 %}
-        {{ reg_name }}[{{ msb }}:24] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]) ? reg_wdat[{{ msb }}:24] : {{ reg_name }}[{{ msb }}:24];
-        {{ reg_name }}[23:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]) ? reg_wdat[23:16] : {{ reg_name }}[23:16];
-        {{ reg_name }}[15:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]) ? reg_wdat[15:{{ lsb }}] : {{ reg_name }}[15:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:24] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:24] : {{ reg_name }}[{{ msb }}:24];
+        {{ reg_name }}[23:16] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]{{ RWP_CONTENT }}) ? reg_wdat[23:16] : {{ reg_name }}[23:16];
+        {{ reg_name }}[15:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[1]{{ RWP_CONTENT }}) ? reg_wdat[15:{{ lsb }}] : {{ reg_name }}[15:{{ lsb }}];
             {% elif lsb < 24 %}
-        {{ reg_name }}[{{ msb }}:24] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]) ? reg_wdat[{{ msb }}:24] : {{ reg_name }}[{{ msb }}:24];
-        {{ reg_name }}[23:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]) ? reg_wdat[23:{{ lsb }}] : {{ reg_name }}[23:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:24] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:24] : {{ reg_name }}[{{ msb }}:24];
+        {{ reg_name }}[23:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[2]{{ RWP_CONTENT }}) ? reg_wdat[23:{{ lsb }}] : {{ reg_name }}[23:{{ lsb }}];
             {% else %}
-        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
+        {{ reg_name }}[{{ msb }}:{{ lsb }}] <= (reg_wr && reg_addr == {{ reg_offset }} && reg_we[3]{{ RWP_CONTENT }}) ? reg_wdat[{{ msb }}:{{ lsb }}] : {{ reg_name }}[{{ msb }}:{{ lsb }}];
             {% endif %}
           {% endif %}
         {% endif %}
@@ -178,7 +186,7 @@ always @(posedge reg_clk or negedge reg_rstn) begin
     end
 end
 {% endif %}
-{% for field in (register.rw_flds + register.w1c_flds + register.w0c_flds + register.wc_flds + register.wo_flds + register.wrc_flds + register.wrs_flds) %}
+{% for field in (register.rw_flds + register.rwp_flds + register.w1c_flds + register.w0c_flds + register.wc_flds + register.wo_flds + register.wrc_flds + register.wrs_flds) %}
 assign {{ field.name }} = {{ register.name }}[{{ field.msb }}:{{ field.lsb }}];
 {% endfor %}
 {% for field in register.ro_flds %}

From 79eb918410d15151f3e19baf5b31a9f652934026 Mon Sep 17 00:00:00 2001
From: Yi Zhang <zhangyiant@hotmail.com>
Date: Tue, 27 Jul 2021 21:08:00 +0800
Subject: [PATCH 2/2] Update version to 1.0.35

---
 register_printer/VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/register_printer/VERSION b/register_printer/VERSION
index 64a736b..fff1fac 100644
--- a/register_printer/VERSION
+++ b/register_printer/VERSION
@@ -1 +1 @@
-1.0.34
\ No newline at end of file
+1.0.35
\ No newline at end of file