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Build a CPU out of logic gate in TypeScript

It's romantic (meaning waste of time).

How to play with it

pnpm install
cd packages/playground
pnpm exec vite

Then open the console.

Use tick() to create a clock cycle.

Description

  • 16-bits CPU. It's working.
  • Up to 64KB RAM.
  • 4 general purpose register. (can expand the number of them easily).
  • Variable instruction cycle. (from 2 to ...)
  • Variable machine code length. (from 2 to ...)

Instructions

Current it can do:

  • Copy data between immediate/register/memery
  • Add/Substract
  • Halt and do nothing
  • Jump, w/ condition
  • Stack (push,pop)
  • Call/return

Layout

  • 2*n bytes
  • 1st byte : instruction
    • 1st bit: 8 bit mode (for instructions involving immediate/memory address)
  • 2nd byte : register address
    • 1st 4-bits is destination, followed by 4-bits source.
    • Reg A: 0b0001
    • Reg B: 0b0010
  • others: immediate

Some instructions don't require register information (like JMP), so 2nd byte is not needed (directly followed by imm.)

References

  • HALT

    0b00001111
  • NOP

    0b00011011
  • MOV reg imm (from imm. to register)

    0b00001000,<register-addr>,<immediate-l>,<immediate-h>
    0b10001000,<register-addr>,<immediate-l>
  • MOV dst src (from register to register)

    0b00001001,<register-addr>
    0b10001001,<register-addr>
  • MOV reg mem

    0b00001010,<register-addr>,<addr-l>,<addr-h>
    0b10001010,<register-addr>,<addr-l>,<addr-h>
  • MOV mem reg

    0b00001011,<register-addr>,<addr-l>,<addr-h>
    0b10001011,<register-addr>,<addr-l>,<addr-h>
  • ADD dst src : add accumulator (A register) with [source] (register) and store the result in [dest] (register)

    0b00000100,<register-addr>
    0b10000100,<register-addr>
  • SUB dst src : substract: similar to add.

    0b00000101,<register-addr>
    0b10000101,<register-addr>
  • INC dst src

    0b00001100,<register-addr>
  • DEC dst src

    0b00001101,<register-addr>
  • JMP : unconditional jump

    0b00010100,<addr-l>,<addr-h>
  • JZ : jump if zero

    0b00010110,<addr-l>,<addr-h>

    Flag zero: Avaliable after ADD/SUB/INC/DEC

  • JNZ : jump if not zero

    0b00010111,<addr-l>,<addr-h>
  • CALL reg

    0b00011000,<0000|source-register-addr>
  • RET

    0b00011001
  • PUSH reg

    0b00001101,<0000|source-register-addr>
    0b10001101,<0000|source-register-addr>
  • POP reg

    0b00001101,<dest-register-addr|0000>
    0b10001101,<dest-register-addr|0000>

CALL/RET

TODO

  • More instructions
    • ALU related
  • Interrupt
    • Keyboard
    • Timer
  • A display (that's why I'm testing in browser)

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