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Aditya892001/README.md
  • 👋 Hi, I’m Aditya Remella
  • 👀 I’m interested in VLSI Design and Verification
  • 🌱 I’m currently learning Verilog HDL, SystemVerilog, UVM, FPGA, CMOS
  • 💞️ I’m looking to collaborate on RTL Coding, Testbench and Testcase creation
  • 📫 How to reach me https://www.linkedin.com/in/aditya-remella-188875198/

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  1. Aditya892001 Aditya892001 Public

    Config files for my GitHub profile.