Skip to content
View AhmedAmrAbdellatif1's full-sized avatar
🏠
Working from home
🏠
Working from home
3 followers · 3 following

Block or report AhmedAmrAbdellatif1

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
AhmedAmrAbdellatif1/README.md

Hi 👋, I'm Ahmed Amr Abdellatif

Passionate About FPGA and ASIC Design & Digital Verification

Processor

ahmedamrabdellatif1

  • 💬 Ask me about Digital Design and Verification

  • 📫 How to reach me [email protected]

  • 📄 Know about my experiences from my CV

Connect with me:

ahmed-amr-abdellatif jubaskii

ahmedamrabdellatif1

Pinned Loading

  1. Multi-Clock-Domain-System Multi-Clock-Domain-System Public

    Design & Implementation of Multi Clock Domain System using Verilog HDL

    Verilog 9