Add TestRIG and Direct Instruction Injection support #1

This commit adds some barebones files to try to add support for TestRIG as well as its required additions (Direct Instruction Injection). This includes a new simulation file, and also adds SocketPacketUtils from https://github.com/CTSRD-CHERI/SocketPacketUtils (SocketPacketUtils is not vendored in correctly at the moment, this will be changed in a later commit)

The bus does not currently set the error signal when a request is out of ranges, so this commit adds a very simple error detection in the toplevel. At the moment writes are not cancelled.

The SRAM block provided by the shared libraries does not handle reset, so memory is instead implemented in C++ so that it can be reset.

The in_count and out_count variables might have strange values when we encounter exceptions and jumps, so remove these as a factor when extracting RVFI data.

Previously, all our verilator "logic" happened while the clock cycle was low (apart from setting gnt_i signals which happened after it when high). Now, all our logic happens while the clock is high, then we evaluate the core so it can update, and then we set the clock low and evaluate. This commit also makes some tracing dependent on the verbosity - the next commit makes more printing and tracing dependent on verbosity.

If there is no real instruction to insert (ie we have run out of instructions, or for some reason our received, in_count or out_count variables got messed up), then insert NOPs instead. This should prevent the core from locking up if we run out of instructions, and should help in debugging.

When control flow changes occur in the core, the simulation environment needs to replay some instructions (since the instructions that have been inserted were flushed out of the pipeline). This commit adds that logic and also explains it.

This is used to track when a MRET or DRET instruction occurs, so that the simulation environment can correctly replay instructions.

When an xRET or exception is encountered, the controller goes into the FLUSH state. RVFI data is read while the controller is in the FLUSH state, but the PC is only available the next cycle, so for RVFI we need to set the PC WData again once it is available.

In typical uses, MTVEC can be set after the core fetches the first instruction and we can use the boot_addr_i signal to set it. However, when using TestRIG it is possible that the first instruction causes an exception, and in this case there is not enough time to set MTVEC before the exception is handled, so the exception vector will be whatever was in boot_addr_i on boot. This is incompatible with TestRIG, so MTVEC is set to 0 on boot rather than using boot_addr_i.

With the changes so far, Ibex reports the same results in RVFI as the Sail-RISCV model modulo the caveats mentioned in the README.

This was done using the vendor script from the OpenTitan repository. The SocketPacketUtils repository is pinned at the latest commit that successfully built; later commits seem to break compilation.

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Add TestRIG and Direct Instruction Injection support #1

Add TestRIG and Direct Instruction Injection support #1

Commits on Sep 14, 2022

Add TestRIG and Direct Instruction Injection support #1

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Add TestRIG and Direct Instruction Injection support #1

Commits on Sep 14, 2022