Skip to content

Commit

Permalink
mudado comportamento do botão enter
Browse files Browse the repository at this point in the history
  • Loading branch information
AndrewCampos committed Nov 25, 2020
1 parent 3c2eefd commit a5dc879
Show file tree
Hide file tree
Showing 67 changed files with 141,847 additions and 143,464 deletions.
11 changes: 4 additions & 7 deletions Verilog/ctrl_undd.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -405,12 +405,8 @@ module ctrl_undd(opcode,
SelMuxUlaB <= 2'b00;
SelMuxIn <= 1'b1;

if(enter == 1'b1) begin
if(!ok) ok = 1'b1;

end else if(enter == 1'b0) begin
if(ok) prox_estado = ESTADO15;
end
if(enter)
prox_estado <= ESTADO15;
end

ESTADO13: begin // finaliza jmp, sw e lw
Expand Down Expand Up @@ -477,7 +473,8 @@ module ctrl_undd(opcode,
SelMuxUlaA <= 1'b0;
SelMuxUlaB <= 2'b00;
SelMuxIn <= 1'b1;
prox_estado <= ESTADO0;
if(opcode != in || enter == 1'b0)
prox_estado <= ESTADO0;
end
endcase
end //fim always
Expand Down
441 changes: 220 additions & 221 deletions Verilog/db/prev_cmp_teste.qmsg
View file

Large diffs are not rendered by default.

Binary file modified Verilog/db/teste.(15).cnf.cdb
View file
Binary file not shown.
Binary file modified Verilog/db/teste.(15).cnf.hdb
View file
Binary file not shown.
14 changes: 7 additions & 7 deletions Verilog/db/teste.asm.qmsg
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1606337521769 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1606337521770 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 25 17:52:01 2020 " "Processing started: Wed Nov 25 17:52:01 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1606337521770 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1606337521770 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off teste -c teste " "Command: quartus_asm --read_settings_files=off --write_settings_files=off teste -c teste" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1606337521770 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1606337522161 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1606337524447 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1606337524524 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1606337525534 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 25 17:52:05 2020 " "Processing ended: Wed Nov 25 17:52:05 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1606337525534 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1606337525534 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1606337525534 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1606337525534 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1606339236066 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1606339236067 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 25 18:20:35 2020 " "Processing started: Wed Nov 25 18:20:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1606339236067 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1606339236067 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off teste -c teste " "Command: quartus_asm --read_settings_files=off --write_settings_files=off teste -c teste" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1606339236067 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1606339236466 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1606339238724 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1606339238806 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "380 " "Peak virtual memory: 380 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1606339239800 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 25 18:20:39 2020 " "Processing ended: Wed Nov 25 18:20:39 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1606339239800 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1606339239800 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1606339239800 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1606339239800 ""}
Binary file modified Verilog/db/teste.asm.rdb
View file
Binary file not shown.
Binary file modified Verilog/db/teste.asm_labs.ddb
View file
Binary file not shown.
Binary file modified Verilog/db/teste.cmp.bpm
View file
Binary file not shown.
Binary file modified Verilog/db/teste.cmp.cdb
View file
Binary file not shown.
Binary file modified Verilog/db/teste.cmp.hdb
View file
Binary file not shown.
Binary file modified Verilog/db/teste.cmp.idb
View file
Binary file not shown.
Binary file modified Verilog/db/teste.cmp.rdb
View file
Binary file not shown.
14 changes: 7 additions & 7 deletions Verilog/db/teste.eda.qmsg
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1606337540335 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1606337540336 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 25 17:52:20 2020 " "Processing started: Wed Nov 25 17:52:20 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1606337540336 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1606337540336 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off teste -c teste " "Command: quartus_eda --read_settings_files=off --write_settings_files=off teste -c teste" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1606337540336 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1606337540812 ""}
{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." { } { } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1606337540924 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "teste.vo /home/andrew/Documentos/Unifesp/Processador-AOC/Verilog/simulation/modelsim/ simulation " "Generated file teste.vo in folder \"/home/andrew/Documentos/Unifesp/Processador-AOC/Verilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1606337542873 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "697 " "Peak virtual memory: 697 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1606337542986 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 25 17:52:22 2020 " "Processing ended: Wed Nov 25 17:52:22 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1606337542986 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1606337542986 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1606337542986 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1606337542986 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1606339254378 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1606339254379 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 25 18:20:54 2020 " "Processing started: Wed Nov 25 18:20:54 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1606339254379 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1606339254379 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off teste -c teste " "Command: quartus_eda --read_settings_files=off --write_settings_files=off teste -c teste" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1606339254379 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1606339254896 ""}
{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." { } { } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1606339255019 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "teste.vo /home/andrew/Documentos/Unifesp/Processador-AOC/Verilog/simulation/modelsim/ simulation " "Generated file teste.vo in folder \"/home/andrew/Documentos/Unifesp/Processador-AOC/Verilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1606339256978 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "694 " "Peak virtual memory: 694 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1606339257114 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 25 18:20:57 2020 " "Processing ended: Wed Nov 25 18:20:57 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1606339257114 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1606339257114 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1606339257114 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1606339257114 ""}
Loading

0 comments on commit a5dc879

Please sign in to comment.