sim/xgmii_ethernet: switch internal bus representation to 32 bits

The xgmii_ethernet module used to represent internal XGMII interface
signals using 64-bit signals. While this is not incorrect per se, it
makes a standards-compliant implementation of the XGMII significantly
harder in the long run. This is because XGMII fundamentally is defined
as a 32-bit bus, and thus has constraints in relation to that bus
width. For example, it is specified that packets may only ever start
on the XGMII lane 0, that is the first octet of a 32-bit XGMII bus
word. Hence, to properly handle a XGMII start of frame control
character using a 64-bit bus representation, the first and fifth octet
would need to be respected, along with shifting data depending on the
start octet.

Hence this change causes the internal XGMII interface to be
represented as a 32-bit bus. Because it is common for FPGAs to
implement the XGMII as a 64-bit bus given the fact that a DDR bus
cannot be represented in an FPGA and 32 bits without DDR would require
a clock frequency of 312.5MHz, it still permits 64-bit operation. This
is implemented by always transmitting two 32-bit bus words back to
back.

Signed-off-by: Leon Schuermann <[email protected]>