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πŸ’‘
Writing Bugs
πŸ’‘
Writing Bugs

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@SEU-MSLab

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AtaraxiaZ/README.md

πŸ’« About Me:

πŸ”­ I’m currently working on FPGA hardware and software co-design
πŸ‘― I’m looking to collaborate on anything about FPGA
🌱 I’m currently learning Linux, Chisel, SystemVerilog
πŸ’¬ Ask me about anything related to FPGA

πŸ’» Tech Stack:

Python C++ Scala PyTorch NumPy Pandas LINUX Trello

πŸ“Š GitHub Stats:




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  1. SEU-MSLab/MP SEU-MSLab/MP Public

    The software and hardware implementation of Memory Polynomial algorithm

    SystemVerilog 4

  2. SEU-MSLab/PRVTDNN SEU-MSLab/PRVTDNN Public

    The Chisel design of Polyphase Real-Value Time-Delay Neural Network (PRVTDNN).

    Scala 1 1