fix: clippy issues

AtoVproject · Apr 1, 2024 · d6e80da · d6e80da
1 parent 29f21bf
commit d6e80da
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/src/config.rs b/src/config.rs
@@ -17,7 +17,7 @@ pub const REG_DAC_DATA: u8 = 0x60;
 /// Available Ports
 #[repr(u8)]
 #[derive(Clone, Copy)]
-pub(crate) enum Port {
+pub enum Port {
     /// Port 0
     P0,
     /// Port 1

diff --git a/src/port.rs b/src/port.rs
@@ -1,3 +1,4 @@
+use core::future::Future;
 use embedded_hal::digital::OutputPin;
 use embedded_hal_async::spi::SpiBus;
 use seq_macro::seq;
@@ -25,10 +26,10 @@ where
 }
 
 pub trait IntoConfiguredPort<'a, CONFIG, SPI: 'a, EN: 'a, S, P> {
-    async fn into_configured_port(
+    fn into_configured_port(
         self,
         config: CONFIG,
-    ) -> Result<MaxPort<'a, CONFIG, SPI, EN>, Error<S, P>>;
+    ) -> impl Future<Output = Result<MaxPort<'a, CONFIG, SPI, EN>, Error<S, P>>>;
 }
 
 seq!(N in 0..=12 {
@@ -60,7 +61,10 @@ pub struct MaxPort<'a, CONFIG, SPI, EN> {
 }
 
 pub trait IntoMode<'a, CONFIG, SPI: 'a, EN: 'a, S, P> {
-    async fn into_mode(self, config: CONFIG) -> Result<MaxPort<'a, CONFIG, SPI, EN>, Error<S, P>>;
+    fn into_mode(
+        self,
+        config: CONFIG,
+    ) -> impl Future<Output = Result<MaxPort<'a, CONFIG, SPI, EN>, Error<S, P>>>;
 }
 
 seq!(N in 0..=12 {