Advanced Physical Design using OpenLANE/Sky130 Workshop is a five day workshop conducted by VSD-IAT.
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Day-2 Understand importance of good floorplan vs bad floorplan and introduction to library cells
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Day-3 Design and characterize one library cell using Magic Layout tool and ngspice
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Day-4 Pre-layout timing analysis and importance of good clock tree
Here we can see an Arduino board which you might have bought from the market and even worked on it. This a typical electronic circuit. But here the field we are talking about is inside the circled part that is the chip.
This image is the block diagram of the above arduino board image and the circled part in the previous image is shown in this figure as a Processor/SOC.
When we open up the IC from Arduino Board we will be seeing as the above image. We will be calling this as a package and it's named as QFN 48 (Quad Flat No-leads)
The image shown below shows where our chip will be located and how it's connected to the package.
This image shows the inside part of the chip which has pads, cores and dies. Pad is an component through which signal can be sent inside the chip. From the marked parts we see core which in the middle of the chip where all our digital logic circuits sits and logic circuits can be any basic gates, MUX's or can be any different kind of logics. Die is the size of the entire chip.
This image is the example or sample of RISCV inside a chip.
This image depicts which are the components present in the above image are foundry related IPs like dac adc0, adc1, pll and SRAM.
A mobile phone for example depends on the foundry. Foundry is like a factory with alot of machines where chips are manufactured.Then sir had shared his experience on working in a foundry of IIT Bombay where he and his team worked in lithography domain. As VLSI engineers our job is to continuously communicate with foundry.
Here we see about RISCV Instruction Set Architecture (ISA) which is a language of the computer and this is the way we are going to talk to a computer.
From the above image we want to pass this C program to a hardware of the above layout in a certain way or in a certain flow. This is done by firstly compiling C in its assembly language program ie RISCV assembly language program then this assembly language is converted to machine language which is basically the binary 1s and 0s understood by the hardware of the computer.
The above image also shows the output in hexadecimal format which is converted to binary format and finally these bits gets executed in the above layout of the hardware and we receive the required output.
There is another interface required between RISCV Architecture and the layout of the hardware ie hardware description language which can be Verilog or VHDL or System verilog. We are implementing RISCV Architecture using some RTL but here we take an example of picorv32 cpu core which takes RISCV Architecture as specifications and implements in hardware description language and finally from the RTL to layout which is nothing but a standard PnR or a standard RTL to GDS fLow.
The above image shows the Apps or Application Softwares used in our PC. These apps run in the computer hardware shown in the below image.
The Below Figure shows a block diagram consisting of Application Software, System Software and Hardware blocks.
This lecture was given by Mohamed Shalan who talked about OpenLane and its features.
Designing digital application specific integrated circuits (ASIC) require certain elements like RTL IP's (which is a hardware description model or functions), EDA tools and Process Design Kits (PDKS). The same is shown in the image given below.
Some of the best websites to acquire RTL Designs include:
librecores.org opencores.org github.com
EDA Software tools include Qflow, OpenROAD and OpenLane.
PDK is the interface between FAB and the designers. It includes collection of files used to model a fabrication process for EDA tools used to design an IC such as:
- Process Design Rules: DRC, LVS, PEX
- Device Models
- Digital Standard Libraries
- I/O Libraries
On June 30, 2020 Google on collaboration with skywater technology released the first open source pdk ie 130nm process skywater to the masses.
The above image demonstrates various steps involved in EDA Tools
This images shows the Simplified flow from RTL design to GDSII
-Conversion of RTL design to a circuit out of components from Standard cell library (SCL). We have a small sample code of always block as shown below:
always @ (posedge clk)
if(c) q<=a;
else q<=b;
Standard Cells have regular layout. Each have different views/models
-Electrical, HDL, SPICE, -Layout (Abstracted and Detailed)
Chip Floorplanning - Partitioning the chip die between different system blocks and placing the I/O pads
The above image describes the Chip Floorplanning
Macro Floorplanning - We define the macro dimensions, pin locations and row definitions.
Power Planning - Power network is constructed typically by multiple VDD and GND pins. the Power pins are all connected through power rings, vertical and horizontal metal straps.
Power rings- Power ring is designed around the core. Power rings contains both VDD and VSS rings. After the ring is placed a power is designed such that power reaches all the cells easily.
This diagram shows the power planning components.
These parallel structures reduce resistance. To address electromagnetism the power distribution network uses upper metal layers as they are thicker than lower metal layers
Placing the cell on the floorplan rows aligned with sites. Connected cells should be placed close to each other to reduce the interconnect delay. It is done in two steps ie Global and Detailed Placement. In global placement , the approximate locations for cells is decided by placing cells in global bins. In detailed placement, cells are Placed without over lapping.
Creating a clock distribution network :
-Delivering clock to all sequential elements.
- With Minimum skew
- In Good shape
- A tree (H,X etc)
Implements interconnects using available metal layers. Metal tracks form a routing grid. Routing uses Divide and Conquer method.
There are two types of Routing ie -Global routing: Generates routing guides -Detailed routing: Uses routing guides to implement actual wiring.
-Physical Verifications
-> Design Rules Checking (DRC) -> Layout vs Scchematic (LVS)
-Timing Verification
-> Static Timing Analysis (STA)
Open source ASIC flow tools we need to worry about:
-Tools Qualification -Tools Calibration -Missing Tools
Efabless decided to create Open source ASIC implementation and flow called as OpenLane which has a public repo in github and is having Apache Version 2.0 license. This OpenLane started as Open-Source Tape Out experiment.
Strive- a family of open everything SOCs ie Open PDK, Open EDA and Open RTL.
This image shows the features of Strive SOCS and its features.
The main goal of OpenLane was to produce a clean GDSII without human interventions. So that means, No LVS Violations! NO DRC Violations! or Timing Issues.
OpenLane was tuned for the Skywater 130nm Open PDK. OpenLane is containerized for making it functional out of the box and for building instruction and running natively. Can be used to harden macros and Chips.
It has two modes of operations ie:
-Autonomous -> It is a push button flow where we configure the design and run the design and obtain the final GDSII along with reports for this flow.
-Interactive -> We run individual commands and steps one by one in an ordered fashion without skipping any step so we can do experimentation and get the idea of how our result will look like.
It has the feature of Design Space Exploration where we can find the best set of flow configurations.It has larger number of design examples which is around 43 designs with best configurations and some more on the way.
This image shows the OpenLane Detailed ASIC Flow
This Flow is based on OpenROAD, Klayout, Yosys, Magic, Qflow, Fault and ABC etc.
The above image is for Yosys. Yosys takes RTL code and .lib files as input and netlist as output.
This image shows the design exploration details such as design name,total runtime for the design flow, cell counts and other details which is tabulated for users to understand the design explorations.
We can do regression testing for these designs as well.
This step is optional in OpenLane which includes scan insertions, ATPGS, Test pattern compaction, fault coverge and fault simulation.
This check is used to formally confirm that the function did not change after modifying the netlist.
This step is done to deal with antenna violations caused during reaction ion etching which causes charge to accumlate metal wires which in turn damages the transition gates.
OpenLane is a flow rather than a tool which comprises of many open source EDA tools.
$ cd Desktop/work/tools
$ ls -ltr
$ cd openlane_working_dir
$ ls -ltr
$ cd pdks
$ ls -ltr
$ cd sky130A
$ ls -ltr
$ ls -ltr
$ cd libs.ref
$ ls -ltr
$ cd ../
$ cd libs.tech
$ ls -ltr
$ cd ../libs.ref
$ cd sky130_fd_sc_hd
$ ls -ltr
$ ls -ltr
$ cd lib
$ ls -ltr
Interactive flow of OpenLane
$ cd../../
$ cd../../../
$ cd openlane_working_dir
$ cd openlane
$make mount
bash-4.2$ pwd
bash-4.2$ ls -ltr
bash-4.2$ ./flow.tcl -interactive
The below images shows the designs in the OpenLane design folder
$ cd designs
$ ls -ltr
Picorv32a is the design and its contents are shown in the below images.
$ cd picorv32a
$ ls -ltr
$ cd src
$ ls -ltr
config.tcl file for picorv32a
$ less config.tcl
sky130_fd_sc_hd_config.tcl for picorv32a
Preparation of design
% package require openlane 0.9
% prep -design picorv32a
$ ls -ltr
$ cd runs
$ ls -ltr
$ cd 30-06_17-25
$ ls -ltr
The below images shows all the runs of the design specific to date the design was run under run folder from picorv32a design.
merge.lef contents
config.tcl in reports directory
$ cd reports
$ ls -ltr
Utilization report
DFF Utilization report
DFF Ratio
Open STA Timing report
https://github.com/The-OpenROAD-Project/OpenLane
This is the link of the OpenLane with the latest version 0.21.
OpenROAD has 37 repos and OpenLane is one of them.
This project has a well documented installation procedures and how to work post OpenLane and PDKs installations.
We have a lot of options and commands for Github like forking, cloning or download a particular repo in .zip format etc.
Core is the section of the chip where the fundamental logic of the design are placed
Die which consist of core is a small semiconductor material specimen on which the fundamental circuit is fabricated.
-Netlist occupies the core area leading to 100% utilization.
Utilization Factor = Area occupied by the Netlist/ Total Area of the core
-Whenever the Utilization Factor=1, the core is fully occupied and we are not allowed to ad any extra cells in our design and the core will take square shaped structure.
Aspect Ratio= Height/ Width
-Whenever the Aspect Ratio = 1, it signifies that the chip is square shaped. But whenever the Aspect Ratio or Utilization Factor is not 1, then the chip will take rectangular shaped structure.
-The arrangement of IP's in a chip is called Floorplanning.
-These IP's/blocks have user defined locations and so these are placed in chip before automated placement and routing and are called as pre-placed cells.
-Automated placement and routing tools places the remaining logic cells in the design onto the chip.
Configuration folder of OpenLane
$ cd configuration
$ pwd
$ ls -ltr
README.md File
floorplan.tcl file
picorv32a Folder contents
$ cd designs/picorv32a
$ pwd
$ ls -ltr
So the precendence is lowest prioriy is system defaults ie all the tcl files for configuration in OpenLane. The next priority is for config.tcl and the last priority is sky130A_sky130_fd_sc_hd_config.tcl.
Config.tcl for picorv32a
Running Floorplanning
% run_floorplan
Viewing Floorplanning files
$ cd picorv32a
$ less config.tcl
$ cd runs
$ ls -ltr
$ cd 30-06_17-25
$ ls -ltr
$ less config.tcl
$ cd logs/floorplan/
$ ls -ltr
Config file in the picorv32a runs folder
Picorv32a def file
$ cd 30-06_17-25
$ ls -ltr
$ less picorv32a.floorplan.def
Opening floorplan using Magic
$ magic -T /home/john/Desktop/work/tools.openlane_working_dir/openlane/pdks/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &
Libraries are like shelves which can be divided into two sub libraries like one library will have shapes and sizes informations and the other might have delay related informations.
Steps in Placement is as below
-Binding netlist with physical cell
The image below shows different flavors for same flipflop, gates and other netlists which can differ in sizes, shapes or delay relatedninformations.
-Placement
-Optimize Placement
This is the stage where we estimate the wire length and capacitances so based on that we insert repeaters. As shown below:
This image shows the common things across all the steps in OpenLane flow.
% run_placement
Viewing def file of placement in picorv32a design
$ cd results/placement
$ ls
Magic Layout after Placement of picorv32a
$ magic -T /home/john/Desktop/work/tools.openlane_working_dir/openlane/pdks/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
The above image shows what are the components in the Cell flow
The below images talk about DRC and LVS rules in a brief way
The below image explains about SPICE models and shows the formulated equation for Threshold Voltage Equation and for linear and saturated regions of operation for the models.
The below images show an example of SPICE Models From Tanner EDA Tool for 0.18nm technology
-Circuit Design
In circuit design Step
We take user defined specifications like cell height, supply voltage, metal layers and pin locations in this design step for cell flow
The above image is an example of circuit design step where we use Euler's path concept to construct paths for the layout design.
Thhe equation for the circuit is Fn= ((B+D) +(A+C) + E.F)'
The above circuit show the equation for Wp/Lp / Wn/Ln ratio to set Vm which is the threshold voltage of the above circuit.
-Layout Design
In layout design as we have mentioned in circuit design that we are using Euler's path concept to construct layout.
So below image is the example of the paths.
The below image explains the euler's path clearly.
-Characterization Flow
This schematic is for a buffer which has inverters connected back to back and this is drawn in GUNA Tool.
The below two images shows the netlist for the main circuit and subcircuit for the buffer we have taken in previous image. The third and fourth images are a model parameter file for this SPICE model.
This GUNA softwares Takes all the files shown in this sections as inputs and generates outputs as Timing, Noise and Power .libs.
Low depicts the values which are close to 0 power supply.
Here in the below concepts we used red line to show inputs and blue for outputs in the graphs.
slew_low_rise_thr- defines the point over the lower side of your power supply which is 0V. Typical value of slew_low_rise_thr is about 20% or can be 30% of bottom power supply.
The above image depicts the slew_low_rise_thr definition.
slew_high_rise_thr- defines the point over the higher side of power supply. Typical value of slew_high_rise_thr is about 20% or can be 30% of top power supply.
The above image depicts the slew_high_rise_thr definition.
slew_low_fall_thr
This images explains slew_low_fall_thr concept.
slew_high_fall _thr
This images explains slew_high_fall _thr concept.
in_rise_thr-
This image explains in_rise_thr concept.
in_fall_thr
This image explains in_faLL_thr concept.
out_rise_thr
This image explains out_rise_thr concept.
out_fall_thr
This image explains out_fall_thr concept.
The above table summarizes the concepts learn in this section all the % is taken from the VDD. in the above Table we see slew_low_rise_thr is 20% of VDD so similarly other % are taken from VDD.
The above image shows the ngspice simulator which we are going to use in this lab.
The above image indicates the location from where we are trying to read picorv32a.floorplan.def to understand about IO placers in the design in floorplan step.
From the above image we see that by default pins are placed equidistantly from each other.
This is the zoomed version of the previous image to show that the pin are placed equidistantly from each other.
Here in the image we see FP_IO_MODE is set to 1, 0 for matching mode and 1 for random equidistant pins.
Here we are setting FP_IO_MODE to 2 in the above image.
This is the layout we will be getting where pins are not equidistant from each other but pins are stacked upon one another.
-SPICE Deck is nothing but the connectivity information about the netlist.
This has the connectivity information, inputs to be provided to the simulator, tap points at which we will take the outputs etc.
We are going to create SPICE Deck for the circuit in the above image.
- Defining component value ie values of PMOS and the NMOS.
Here we have taken W/L ratio for PMOS (M1) and NMOS (M2) to be 0.375u/0.25u and Cload as 10 fF
Here the above image is extended circuit of the just previous circuit which has input gate voltage as 2.5V and VDD as 2.5V based on technology used so here we use 0.25u 0r 250nm technology. cvxz -Identifying the nodes in the circuit
This image shows the nodes indicated by blue dotted lines.
-Naming the nodes
From the identifying nodes image we are naming the nodes as in which is between Vin and VSS, out for the node which is connected to Cload of 10fF and vdd as node connecting VDD and Vss and is shown as below
SPICE Deck is written as shown below:
** Model Descriptions **
** Netlist Descriptions **
M1 out in vdd vdd pmos W=0.375u L=0.25u
M2 out in 0 0 nmos W=0.375u L=0.25u
cload out 0 10f
Vdd vdd 0 2.5
Vin in 0 2.5
*** Simulation Commands ***
.op
.dc Vin 0 2.5 0.05
*** .include tsmc _025um_model.mod ***
.LIB "tsmc _025um_model.mod" CMOS_MODELS
.end
The above image is the ngspice window.
The above image shows the technology file of 0.25um technology
The location of the technology file is passed as command in the above image.
Then we give
ngspice2 -> cmosVTC_PMOSwidth_NMOSwidth.cir
Executing the circuit
ngspice3 -> run
ngspice4 -> setplot
This image tells us as to what has happened after passing setplot command. So dc1 is for dc characteristics, op1 for operating point and const for constant values.
ngspice5 -> dc1
ngspice5 -> display --->displays nodes in the circuit
ngspice6 -> out vs in ---> plotting input node vs output node
This is the Voltage characteristics of the given CMOS inverters
This image compares two different devices having different W/L ratios. Even though the switching occurs at different places the waveforms are the same. this shows the robustness of CMOS inverters interms of its apllications
Vm is the point where vin=vout
From the image 1st graph had Vm around 0.98V and 2nd one had Vm as 1.25V approximately.
$ pwd -Your present working directory should be openlane directory
$ git clone https://github.com/nickson-jose/vsdstdcelldesign.git
$ ls -ltr
$ cd vsdstdcelldesign
$ ls -ltr
Copying sky130A.tech
$ cd ../../ -->cding to openlane_working_dir
$ pdks/sky130A/libs.tech/magic
$ ls -ltr
$ cp sky130A.tech /home/john/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign
The below image made use of the above commands for copying sky130.tech
$ cd /openlane/vsdstdcelldesign
$ ls -ltr
$ magic -T sky130A.tech sky130_inv.mag &
Viewing sky130_inv.mag in Magic Layout tool
We take a 16-mask CMOS process
-Selecting a substrate
Here we go for P type substrate with high resistivity, doping level as 10^15 cm^-3 and orientation as 100
-Creating active region for transistors
Here we are creating small pockets or buckets as active region on the ptype substrate where we will create pmos and nmos transistors
-> Grow Silicon on Silicon dioxide which acts as an insulator. -> Deposit a layer silicon nitride. -> Deposit a layer of photoresist. -> Then we create mask1 and UV light is passed through the layer. -> Washing out photoresist. -> Removing the mask. -> Etching the silicon nitride. -> Etching the resist from the layer. -> Placed in oxidation furnace. -> Growing field oxide. This process is called LOCOS. -> Etching the remaining silicon nitride using phosphoric acid.
- N well and P well formation
For P well formation -> Deposit a layer of photoresist. -> Then we create mask2 and UV light is passed through the layer -> Washing out photoresist. -> Removing the mask. -> Creating P well using Boron by ion implantation.
For N well formation
-> Deposit a layer of photoresist. -> Then we create mask3 and UV light is passed through the layer -> Washing out photoresist. -> Removing the mask. -> Creating N well using Phosphorus by ion implantation.
-> Placing the layer consisting of P well and N well in high temperature furnace. -> diffuse the boron and the phosphorus atoms ->This forms a twin tub.
- Formation of gate terminal
Controlling doping concentration can be done by:
For N well gate formation
-> Deposit a layer of photoresist. -> Then we create mask2 and UV light is passed through the layer. -> Washing out photoresist. -> Removing the mask. -> Introducing boron with lower energy by ion implantation which inturn controls the threshold voltage.
For P well gate formation
-> Deposit a layer of photoresist. -> Then we create mask2 and UV light is passed through the layer. -> Washing out photoresist. -> Removing the mask. -> Introducing arsenic with lower energy by ion implantation which inturn controls the threshold voltage. -> Original oxide is removed/stripped using hydrofluoric acid. -> Regrowing oxide again to provide high quality oxide. -> Deposit a polysilicon layer. -> N type ion implants for low gate resistance. -> Deposit a layer of photoresist. -> Then we create mask6. -> Etching the resist from the layer. -> Removing the mask. ->Remaining polysilicon layer outside the photoresist can be etched away. -> Removing the remaining resist.
-Lightly doped drain formation(LDD)
-> For this we need doping profiles like P+,P- and N along N well and N+, N- and P along P well side. -> Reasons for these profiles: Hot electron effect and short channel effect.
For N well
-> Deposit a layer of photoresist. -> Then we create mask7 -> Washing out photoresist. -> Introducing phosphorus by ion implantation. -> Removing phtoresist from n well and apply photoresist and mask8 on pwell. -> Removing mask from p well. -> Introducing boron by ion implantation. -> We add spacers by depositing a thick SiO2 or Si3N4 layer on the complete structure and then we apply plasma anisotropic etching.
- Source and drain formation
-> Thin screen oxide is added to avoid channeling during implants. -> Deposit a layer of photoresist. -> Then we create mask9 in Nwell side. -> Removing mask from nwell after it's exposed to other implants -> introducing Arsenic byion implantation.
We apply the same process to P well side but now the mask used will be mask10. Then we introduce a p type impurity like boron. We apply high temperature furnace to the structure.
Here in the imageswe highlighted a sub layer and we used the command as below:
% what
Difference between layout and LEF
The above image is the layout the inverter.
The layout will have all the informations from metal layers,vias and all the logical and other informations.
The above image was taken from Nickson Jose's vsdstdcell design repo.
But LEF reveals only the metal layers without exposing any logical part of the design. For Pnr of the cell we don't need any logic of the cell and all we need to know where are the Pr boundaries.
This image shows DRC errors in the layout if we move layers intentionally and unintentionally.
$extract all
This image shows the command for extracting netlist from an inverter layout using tkcon command window.
$ ls -ltr ---> under vsdstdcelldesign directory
This image shows that the previous command extract all has created a file called sky130_inv.ext in vsdstdcelldesign directory.
$ ext2spice cthesh 0 rthresh 0
$ ext2spice
This image shows that the above commands for extracting spice from an inverter layout using tkcon command window.
$ ls -ltr ---> under vsdstdcelldesign directory
This image shows that the previous command extract 2 spice commands extracts inverter layout to spice format in vsdstdcelldesign directory.
The below images shows the contents of sky130_inv.spice
$ vim sky130_inv.spice
The above image is the initial SPICE Deck netlist
The below image shows where pshort.lib and n.short.lib is located
$ cd libs
$ ls -ltr
The above image shows the final SPICE DECK netlist.
These below images shows the ngspice window with timing analysis and commands to plot the required parameters.
This below image shows the waveform in accordance with the SPICE Deck netlist
These below images show the zoomed version of the waveform for rise_transition time
The below image shows the coordinates when expanded for rise_transition time along with calculation
The track info file
Grid info to track info
% grid 0.46um 0.34um 0.23um 0.17um --based on the track info from sky130_fd_sc_hd library
As an example editing of input A layer is as shown below.
Saving the layout according to user's way is as shown below in the below image
Re-running magic to check whether the mag file was sucessfully saved and in working condition
Creating lef file from magic layout created in previous image
$ lef write
$ ls -ltr
$ less sky130_vsdin.lef
These are the images for the contents in sky130_vsdin.lef
The below image shows the copying sky130_vsdin.lef into picorv32a design's src dirctory
Contents in sky130_fd_sc_hd__typical.lib
Contents in sky130_fd_sc_hd__slow.lib
The below image shows the copying sky130_fd_sc_hd__* files into picorv32a design's src dirctory
Here this image shows that sky130_fd_sc_hd__* files successfully copied into picorv32a design's src dirctory
Here is the screenshot of modified picorv32a config.tcl file which includes sky130_fd_sc_hd__* files and sky130_vsdin.lef
Now we are running the openlane flow from preparation till placement for picorv32a with sky130_fd_sc_hd__* files and sky130_vsdin.lef files
Preparing the design
Setting and adding lef files
Performing Synthesis
README.md file for applying synthesis strategy
Setting SYNTH_STRATEGY
When we set this value as 1 where the area would would increase but the delay will decrease significantly.
These are the Strategies to be set to reduce delay in the design as in the below images
Changing synth.tcl and reducing tns and wns
Observations:
-2 levels of buffering. -At every level, each node driving same load. -Identical buffer at same level.
The example circuit is as shown below
This image shows our assumptions for the above circuit
Delay table example is as shown below
Delay table for CBUF 1
Delay table for CBUF 2
Based on assumption in the below image
We round the values meeting 60ff at node A for CBUF 1
We round the values meeting 50ff at node B for CBUF 2
We round the values meeting 50ff at node B for CBUF 2 for a different input condition
Specifications:
Clock Frequency(F)= 1GHZ Clock Period(T)= 1/F =1/1GHZ =1ns
The setup timing analysis says that if for this particular circuit to work, the combination delay (θ) ie internal delay of the launch flop and the combinational delay in the above circuit must be less than the time period given in the specifications.
θ < T
For the capture flop to settle with the received data we have to tweak θ < T so, the condition will look like
θ < (T-S)
where S is the setup time of Capture Flipflop
Clock Jitter: temporary variation of clock period.
For modeling this jitter we take one more parameter called uncertainty
After we introduce this concept, θ < (T-S) is again changed based on setup uncertainty(SU) so the condition becomes
θ < (T-S-SU)
H Tree Algorithm takes a particular clock route and it claculates the distance from a particular point to all its end points and tries to comment on the midpoint and builds a tree from that midpoint.
Performing initial floorplan
% init_floorplan
IO placement
% place_io
Running placement on processed Design
% global_placement_or
Improved Slack after running placement on processed Design
Running placement using RePlace
% global_placement
Tap decap using OpenRoad app
% tap_decap_or
Detailed placement using OpenRoad app
% detailed_placement_or
Detailed placement using OpenDP
% detailed_placement
Detailed placement after Tap_decap
% detailed_placement
Layout of Detailed placement after Tap_decap
% gen_pdn
% run_routing
Some images from Detailed Routing iteration
Here in the below image we can see a significant reduction in violations compared to previous image.
In the below image by 41 st iteration all the violations are resolved
The below image shows the last iteration for detailed routing ie 57th iterations
Final total wire lengths after detailed routing
Layout of Routing
$ magic -T /home/john/Desktop/work/tools/openlane_working_dir/pdks/sky130libs.tech lef read ../../tmp/merged.lef def read picorv32a.def
-Running magic command
% run_magic
-Magic DRC Check
% run_magic_drc
-MAGIC SPICE EXPORT
% run_magic_spice_export
-MAGIC Antenna Check
% run_magic_antenna_check
So by this we come to the end of day five where I've understand the Openlane flow, various commands in the flow, how to add a customized standard cell design to already existing picorv32a design and performing the Openlane flow using this cell's lib files and lef files and understanding the challenges in using an external cell design and ways to solve the issues with the customized cell design and finally we extracted layouts for each of the process in OpenLane flow.
- Kunal Ghosh - Co-founder(VSD Corp. Pvt. Ltd)
- Nickson Jose - VSD Teaching Assistant
- Mili Anand - VSD Teaching Assistant
- Mansi Mohapatra - VSD Teaching Assistant