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Merge branch 'cabal_update_ndk' into 'devel'
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Big NDK-FPGA update

See merge request ndk/ndk-fpga!126
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@jakubcabal
jakubcabal committed Dec 16, 2024
2 parents 74fc4b8 + 9aa4e01 commit f4456f2
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Showing 19 changed files with 48 additions and 120 deletions.
9 changes: 0 additions & 9 deletions apps/minimal/build/agi-fh400g/jenkins/100g4.jenkinsfile
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Expand Up @@ -11,12 +11,3 @@ stagesFirmware(
artifacts: 'agi-fh400g-minimal-100g4',
lastBuilds: 2,
)

stagesNdkTest(
card: '400g1',
mode: '100g4',
project: 'app-minimal',
fw_name: 'agi-fh400g-minimal-100g4.nfw',
testbranch: 'friedl-feat-400g1'
)

9 changes: 0 additions & 9 deletions apps/minimal/build/agi-fh400g/jenkins/10g8.jenkinsfile
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Expand Up @@ -11,12 +11,3 @@ stagesFirmware(
artifacts: 'agi-fh400g-minimal-10g8',
lastBuilds: 2,
)

stagesNdkTest(
card: '400g1',
mode: '10g8',
project: 'app-minimal',
fw_name: 'agi-fh400g-minimal-10g8.nfw',
testbranch: 'friedl-feat-400g1'
)

9 changes: 0 additions & 9 deletions apps/minimal/build/agi-fh400g/jenkins/200g2.jenkinsfile
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Expand Up @@ -11,12 +11,3 @@ stagesFirmware(
artifacts: 'agi-fh400g-minimal-200g2',
lastBuilds: 2,
)

stagesNdkTest(
card: '400g1',
mode: '200g2',
project: 'app-minimal',
fw_name: 'agi-fh400g-minimal-200g2.nfw',
testbranch: 'friedl-feat-400g1'
)

9 changes: 0 additions & 9 deletions apps/minimal/build/agi-fh400g/jenkins/25g8.jenkinsfile
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Expand Up @@ -11,12 +11,3 @@ stagesFirmware(
artifacts: 'agi-fh400g-minimal-25g8',
lastBuilds: 2,
)

stagesNdkTest(
card: '400g1',
mode: '25g8',
project: 'app-minimal',
fw_name: 'agi-fh400g-minimal-25g8.nfw',
testbranch: 'friedl-feat-400g1'
)

9 changes: 0 additions & 9 deletions apps/minimal/build/agi-fh400g/jenkins/400g1.jenkinsfile
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Expand Up @@ -11,12 +11,3 @@ stagesFirmware(
artifacts: 'agi-fh400g-minimal-400g1',
lastBuilds: 2,
)

stagesNdkTest(
card: '400g1',
mode: '400g1',
project: 'app-minimal',
fw_name: 'agi-fh400g-minimal-400g1.nfw',
testbranch: 'friedl-feat-400g1'
)

9 changes: 0 additions & 9 deletions apps/minimal/build/agi-fh400g/jenkins/50g8.jenkinsfile
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Expand Up @@ -11,12 +11,3 @@ stagesFirmware(
artifacts: 'agi-fh400g-minimal-50g8',
lastBuilds: 2,
)

stagesNdkTest(
card: '400g1',
mode: '50g8',
project: 'app-minimal',
fw_name: 'agi-fh400g-minimal-50g8.nfw',
testbranch: 'friedl-feat-400g1'
)

8 changes: 0 additions & 8 deletions apps/minimal/build/fb2cghh/jenkins/100g2.jenkinsfile
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Expand Up @@ -10,11 +10,3 @@ stagesFirmware(
artifacts: 'fb2cghh-minimal-100g2',
lastBuilds: 2,
)

stagesNdkTest(
card: 'tivoli',
mode: '100g2',
project: 'minimal',
fw_name: 'fb2cghh-minimal-100g2.nfw',
testbranch: 'friedl-feat-ndk_app_minimal'
)
9 changes: 0 additions & 9 deletions apps/minimal/build/ia-420f/jenkins/100g2.jenkinsfile
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Expand Up @@ -11,12 +11,3 @@ stagesFirmware(
artifacts: 'ia-420f-minimal-100g2',
lastBuilds: 2,
)

stagesNdkTest(
card: 'ia-420f',
mode: '100g2',
project: 'minimal',
fw_name: 'ia-420f-minimal-100g2.nfw',
testbranch: 'friedl-feat-ndk_app_minimal'
)

8 changes: 0 additions & 8 deletions apps/minimal/build/n6010/jenkins/100g2.jenkinsfile
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Expand Up @@ -11,11 +11,3 @@ stagesFirmware(
artifacts: 'n6010-minimal-100g2',
lastBuilds: 2,
)

stagesNdkTest(
card: 'n6010',
mode: '100g2',
project: 'minimal',
fw_name: 'n6010-minimal-100g2.nfw',
testbranch: 'friedl-feat-ndk_app_minimal'
)
8 changes: 0 additions & 8 deletions apps/minimal/build/n6010/jenkins/10g8.jenkinsfile
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Expand Up @@ -11,11 +11,3 @@ stagesFirmware(
artifacts: 'n6010-minimal-10g8',
lastBuilds: 2,
)

stagesNdkTest(
card: 'n6010',
mode: '10g8',
project: 'minimal',
fw_name: 'n6010-minimal-10g8.nfw',
testbranch: 'friedl-feat-ndk_app_minimal'
)
8 changes: 0 additions & 8 deletions apps/minimal/build/n6010/jenkins/25g8.jenkinsfile
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Expand Up @@ -11,11 +11,3 @@ stagesFirmware(
artifacts: 'n6010-minimal-25g8',
lastBuilds: 2,
)

stagesNdkTest(
card: 'n6010',
mode: '25g8',
project: 'minimal',
fw_name: 'n6010-minimal-25g8.nfw',
testbranch: 'friedl-feat-ndk_app_minimal'
)
8 changes: 0 additions & 8 deletions apps/minimal/build/nfb-200g2ql/jenkins/100g2.jenkinsfile
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Expand Up @@ -10,11 +10,3 @@ stagesFirmware(
artifacts: 'nfb-200g2ql-minimal-100g2',
lastBuilds: 2,
)

stagesNdkTest(
card: '200g2ql',
mode: '100g2',
project: 'nic',
fw_name: 'nfb-200g2ql-minimal-100g2.nfw',
testbranch: 'friedl-feat-ndk_app_minimal'
)
2 changes: 2 additions & 0 deletions comp/nic/mac_lite/tx_mac_lite/Modules.tcl
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Expand Up @@ -11,6 +11,7 @@ set MFB_PD_ASFIFO_BASE "$OFM_PATH/comp/mfb_tools/storage/pd_asfifo"
set MFB_FRAME_LNG_BASE "$OFM_PATH/comp/mfb_tools/logic/frame_lng"
set MFB_RECONFIG_BASE "$OFM_PATH/comp/mfb_tools/flow/reconfigurator"
set MFB_CX_STREAM_BASE "$OFM_PATH/comp/mfb_tools/logic/crossbarx_stream"
set ASYNC_RESET_BASE "$OFM_PATH/comp/base/async/reset"
set LCOMP_BASE "$ENTITY_BASE/comp"

set PACKAGES "$PACKAGES $PKG_BASE/math_pack.vhd"
Expand All @@ -27,6 +28,7 @@ set COMPONENTS [list \
[list "SPACER" $MFB_CX_STREAM_BASE "FULL" ] \
[list "STAT_UNIT" "$LCOMP_BASE/stat_unit" "FULL" ] \
[list "ADDR_DEC" "$LCOMP_BASE/addr_dec" "FULL" ] \
[list "ASYNC_RESET" $ASYNC_RESET_BASE "FULL" ] \
]

# Source files for implemented component
Expand Down
19 changes: 12 additions & 7 deletions comp/nic/mac_lite/tx_mac_lite/comp/addr_dec/addr_dec.vhd
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Expand Up @@ -41,7 +41,8 @@ entity TX_MAC_LITE_ADDR_DEC is
-- CONTROL OUTPUT INTERFACE (CLK)
CTRL_STROBE_CNT : out std_logic;
CTRL_RESET_CNT : out std_logic;
CTRL_OBUF_EN : out std_logic
CTRL_OBUF_EN : out std_logic;
CTRL_LD_DISCARD_DIS : out std_logic
);
end entity;

Expand Down Expand Up @@ -96,6 +97,7 @@ architecture FULL of TX_MAC_LITE_ADDR_DEC is
signal cmd_reset_cnt : std_logic;
signal cmd_reset_cnt_reg : std_logic;
signal obuf_en_reg : std_logic;
signal ld_discard_dis_reg : std_logic;
signal obuf_en_reg_32 : std_logic_vector(31 downto 0);
signal status_disable_crc : std_logic;
signal status_reg : std_logic_vector(6 downto 0) := "1010000";
Expand Down Expand Up @@ -172,7 +174,7 @@ begin

status_disable_crc <= '1' when (CRC_INSERTION_EN = False) else '0';

obuf_en_reg_32 <= (31 downto 1 => '0') & obuf_en_reg;
obuf_en_reg_32 <= (31 downto 9 => '0') & ld_discard_dis_reg & "0000000" & obuf_en_reg;
status_reg_32 <= (31 downto 7 => '0') & ETH_SPEED_CODE & "00" & status_disable_crc & obuf_en_reg;

mi_s_drd_mux_p : process(all)
Expand Down Expand Up @@ -261,9 +263,11 @@ begin
begin
if (rising_edge(CLK)) then
if (RESET = '1') then
obuf_en_reg <= '0';
obuf_en_reg <= '0';
ld_discard_dis_reg <= '0'; -- link down discard is enabled by default
elsif (obuf_en_reg_we = '1') then
obuf_en_reg <= mi_s_dwr(0);
obuf_en_reg <= mi_s_dwr(0);
ld_discard_dis_reg <= mi_s_dwr(8);
end if;
end if;
end process;
Expand All @@ -272,8 +276,9 @@ begin
-- OUTPUTS ASSIGMENTS
-- =========================================================================

CTRL_STROBE_CNT <= cmd_strobe_cnt_reg;
CTRL_RESET_CNT <= cmd_reset_cnt_reg;
CTRL_OBUF_EN <= obuf_en_reg;
CTRL_STROBE_CNT <= cmd_strobe_cnt_reg;
CTRL_RESET_CNT <= cmd_reset_cnt_reg;
CTRL_OBUF_EN <= obuf_en_reg;
CTRL_LD_DISCARD_DIS <= ld_discard_dis_reg;

end architecture;
37 changes: 30 additions & 7 deletions comp/nic/mac_lite/tx_mac_lite/tx_mac_lite.vhd
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Expand Up @@ -155,9 +155,10 @@ entity TX_MAC_LITE is
TX_MFB_DST_RDY : in std_logic;

-- =====================================================================
-- OUTPUT LINK STATUS INTERFACE (TX_CLK)
-- CONTROL/STATUS INTERFACE
-- =====================================================================

-- ETH link UP status (ASYNC)
ETH_LINK_UP : in std_logic := '1';
-- Links status (TX_CLK): Active during frame transmission
OUTGOING_FRAME : out std_logic
);
Expand Down Expand Up @@ -200,6 +201,10 @@ architecture FULL of TX_MAC_LITE is
constant CRC_ASFIFO_RAM_TYPE : string := "AUTO";
constant CRC_ASFIFO_AFULL_TH : natural := fce_crcfifo_afull_threshold(MD_REGION_SIZE,MD_BLOCK_SIZE,CRC_END_IMPL);

signal eth_link_down_sync : std_logic;
signal ctrl_ld_discard_dis : std_logic;
signal ctrl_ld_discard : std_logic;

signal rx_mfb_sof_pos_fix : std_logic_vector(RX_REGIONS*max(1,log2(RX_REGION_SIZE))-1 downto 0);

signal rc_mfb_data : std_logic_vector(MD_REGIONS*MD_REGION_SIZE*MD_BLOCK_SIZE*MD_ITEM_WIDTH-1 downto 0);
Expand All @@ -225,6 +230,7 @@ architecture FULL of TX_MAC_LITE is
signal fl_mfb_frame_len_arr : slv_array_t(MD_REGIONS-1 downto 0)(LEN_WIDTH-1 downto 0);
signal fl_mfb_undersize : std_logic_vector(MD_REGIONS-1 downto 0);
signal fl_mfb_discard : std_logic_vector(MD_REGIONS-1 downto 0);
signal fl_mfb_discard_vld : std_logic_vector(MD_REGIONS-1 downto 0);

signal crc_mfb_src_rdy : std_logic;
signal crc_mfb_dst_rdy : std_logic;
Expand Down Expand Up @@ -300,6 +306,21 @@ architecture FULL of TX_MAC_LITE is

begin

eth_link_up_sync_i : entity work.ASYNC_RESET
generic map (
TWO_REG => false,
OUT_REG => true,
REPLICAS => 1
)
port map (
CLK => RX_CLK,
ASYNC_RST => (not ETH_LINK_UP),
OUT_RST(0) => eth_link_down_sync
);

-- when ETH link is down, discard all packets by default
ctrl_ld_discard <= eth_link_down_sync and not ctrl_ld_discard_dis;

-- =========================================================================
-- MFB RECONFIGURATOR
-- =========================================================================
Expand Down Expand Up @@ -392,8 +413,9 @@ begin
fl_mfb_frame_len_arr <= slv_array_deser(fl_mfb_frame_len,MD_REGIONS,LEN_WIDTH);

fl_mfb_discard_g : for r in 0 to MD_REGIONS-1 generate
fl_mfb_undersize(r) <= '1' when (unsigned(fl_mfb_frame_len_arr(r)) < FRAME_LEN_MIN) else '0';
fl_mfb_discard(r) <= fl_mfb_undersize(r) and fl_mfb_eof(r) and fl_mfb_src_rdy;
fl_mfb_undersize(r) <= '1' when (unsigned(fl_mfb_frame_len_arr(r)) < FRAME_LEN_MIN) else '0';
fl_mfb_discard(r) <= fl_mfb_undersize(r) or ctrl_ld_discard;
fl_mfb_discard_vld(r) <= fl_mfb_discard(r) and fl_mfb_eof(r) and fl_mfb_src_rdy;
end generate;

fl_mfb_dst_rdy <= fd_mfb_dst_rdy and crc_mfb_dst_rdy;
Expand All @@ -408,7 +430,7 @@ begin
fd_mfb_sof_pos <= fl_mfb_sof_pos;
fd_mfb_eof_pos <= fl_mfb_eof_pos;
fd_mfb_frame_len <= fl_mfb_frame_len;
fd_mfb_discard <= fl_mfb_discard;
fd_mfb_discard <= fl_mfb_discard_vld;
end if;
end if;
end process;
Expand Down Expand Up @@ -461,7 +483,7 @@ begin
-- ---------------------------------------------------------------------

cd_fifo_wr <= (or fl_mfb_eof) and crc_mfb_src_rdy;
cd_fifo_di <= fl_mfb_eof and not fl_mfb_undersize;
cd_fifo_di <= fl_mfb_eof and not fl_mfb_discard;

process (RX_CLK)
begin
Expand Down Expand Up @@ -872,7 +894,8 @@ begin

CTRL_STROBE_CNT => ctrl_strobe_cnt,
CTRL_RESET_CNT => ctrl_reset_cnt,
CTRL_OBUF_EN => ctrl_obuf_en
CTRL_OBUF_EN => ctrl_obuf_en,
CTRL_LD_DISCARD_DIS => ctrl_ld_discard_dis
);

end architecture;
1 change: 1 addition & 0 deletions core/comp/eth/network_mod/comp/network_mod_logic/network_mod_logic.vhd
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Expand Up @@ -407,6 +407,7 @@ begin
TX_MFB_SRC_RDY => TX_CORE_MFB_SRC_RDY(ch),
TX_MFB_DST_RDY => TX_CORE_MFB_DST_RDY(ch),

ETH_LINK_UP => RX_LINK_UP(ch),
OUTGOING_FRAME => ACTIVITY_TX(ch)
);
else generate
Expand Down
2 changes: 1 addition & 1 deletion extra/dma-medusa
Submodule dma-medusa updated from 3ce185 to 472d80
2 changes: 1 addition & 1 deletion extra/nfb-200g2ql
Submodule nfb-200g2ql updated from bdcebd to 0c4ad0
2 changes: 1 addition & 1 deletion tests/jenkins/ver_dma_medusa_new.jenkins
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Expand Up @@ -9,7 +9,7 @@
// FORMAT:
// [ 'name' , 'path_to_ver' , 'fdo_file.fdo' , 'test_pkg.sv/.vhd' , 'settings.py' ]
def COMPONENTS = [\
['Basic Tests' , 'extra/dma-medusa/ver' , 'top_level.fdo' , 'tbench/test_pkg.sv' , 'ver_setings_new.py' ],\
['Basic Tests' , 'extra/dma-medusa/ver' , 'top_level.fdo' , 'tbench/test_pkg.sv' , 'ver_settings_new.py' ],\
]
// /////////////////////////////////////////////////////////////////////////////

Expand Down

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