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Bump sail-riscv to point at version with enable-misaligned on by defa…
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…ult in the sail simulator.

This is the correct baseline for CHERIoT.
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@rmn30
rmn30 committed Dec 26, 2024
1 parent 2015e1c commit e7b24f2
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion sail-riscv
Submodule sail-riscv updated 2 files
+1 −1 c_emulator/riscv_platform_impl.c
+6 −0 c_emulator/riscv_sim.c

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