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Bump sail-riscv to point at version with enable-misaligned on by default in the sail simulator #93

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@rmn30 rmn30 commented Dec 26, 2024

This is the correct baseline for CHERIoT. Fixes #92 .

…ult in the sail simulator.

This is the correct baseline for CHERIoT.
@rmn30 rmn30 requested a review from nwf December 26, 2024 08:35
@rmn30 rmn30 unassigned nwf Dec 26, 2024
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Should misaligned non-cap memory accesses by enabled by default?
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