Skip to content

Issues: CTSRD-CHERI/cheri-specification

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

36 Open 7 Closed
36 Open 7 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Change CSetBounds* behavior
#121 opened Oct 16, 2023 by andresag01
1
Saving instruction encoding space in CHERI RISC-V
#120 opened Oct 16, 2023 by andresag01
Tag cleared for sealed caps written with CSpecialRW
#119 opened Oct 16, 2023 by andresag01
1
Xtval capability index on ASR exception for RISC-V
#118 opened Oct 5, 2023 by andresag01
1
Address zero-length capability issues.
#117 opened Oct 4, 2023 by PeterRugg
7
x86: Support capability-wide MSRs
#116 opened Oct 3, 2023 by bsdjhb
x86: Consider swapping REX.W and 06 in capability mode
#115 opened Oct 3, 2023 by bsdjhb
CHERI and Pointer Masking
#114 opened Sep 5, 2023 by tariqkurd-repo
4
CW and CD bits in PTE
#113 opened Aug 31, 2023 by andresag01
2
Consider making Zba: sh1add, sh2add, sh3add capability based in cap mode
#112 opened Aug 24, 2023 by tariqkurd-repo
Fixing the address-wrapping RISC-V compatibility issue
#111 opened Aug 24, 2023 by tariqkurd-repo
5
Vectored xTVEC/xTCC mode address may need checking
#110 opened Aug 21, 2023 by tariqkurd-repo
4
CHERI when RISC-V XLEN changes
#109 opened Aug 15, 2023 by andresag01
4
double-width load/store for performance
#108 opened Aug 15, 2023 by tariqkurd-repo
6
CHERI Specification for RISC-V Hypervisor Extension
#104 opened Aug 14, 2023 by andresag01
CHERI Specification for RISC-V Vector Extension
#103 opened Aug 14, 2023 by andresag01
1
Should MRET/SRET check for PCC.ASR?
#96 opened Aug 8, 2023 by tariqkurd-repo
3
misaligned load/store capabilities can't be emulated
#91 opened Aug 7, 2023 by tariqkurd-repo
3
Invalid virtual addresses in CHERI-RISC-V
#84 opened Aug 3, 2023 by andresag01
8
move store capability to tag clearing if the store cap permission isn't set
#73 opened Jul 17, 2023 by tariqkurd-repo
1
Debug specification for CHERI-RISC-V
#71 opened Jul 14, 2023 by andresag01
1
CHERI privilege level enable
#70 opened Jul 14, 2023 by tariqkurd-repo
5
CHERI global enable/disable
#69 opened Jul 14, 2023 by tariqkurd-repo
5
Define instruction outputs for non-derivable capability inputs
#68 opened Jul 14, 2023 by andresag01
14
Interconnect support for RISC-V AMOSWAP.C
#67 opened Jul 14, 2023 by andresag01
2
ProTip! Updated in the last three days: updated:>2024-11-10.