Support for full interrupts virtualization #257
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
CharlyCst
force-pushed
the
push-xrwkmynnvkst
branch
from
7e39285
to
f5665b7
Compare
|
Current status:
To be done:
Both of which requires a virtual CLINT device, which is being developped as part of #199. |
The mip.SEIE bit is in fact composed of two different bits, a hardware-writeable one and another software-writable one. The behavior of CSR set and clear operations is modified for the particular case of this bit. To emulate it properly we would need to special case all of the CSR set and clear functions to ignore the hardware-writeable bit. Instead of duplicating the whole logic, this commit simply omit the hardware-writeable bit, making it invisible to the virtualized firmware. In practice this is not really an issue as we force the external supervisor interrupts to be delegated, so the firmware should not be in charge of devices generating such interrupts (because we don't want to emulate them). This commit fixes the hangs with the Linux shell payload when the Sstc exension is not present. This can be tested with the following config parameters on a sufficiently modern QEMU: ``` [qemu] machine = "virt" cpu = "sifive-u54,sstc=false" ```
CharlyCst
force-pushed
the
push-xrwkmynnvkst
branch
3 times, most recently
from
05cd128
to
5bad60e
Compare
This PR implements proper MTI virtualization. For that purpose it lays out the foundations of full interrupt virtualization, i.e. it lets Miralis manage the `mip` bits and inject interrupts rather than relying on the hardware physical interrupts. For now all physical M-mode timer interrupts are still assumed to be caused by the firmware and update the virtual `mip.MTIP` bit. If we need out-of-band MTI we should implement a mechanism for distinguishing the cause of a timer interrupt, most likely simply checking if the virtual `mtimecmp` deadline passed or not.
This commit implements proper MSI virtualization. For that purpose it virtualizes the list of pending MSI in the virtual CLINT. When a vCPU sends an MSI to another core the virtual CLINT triggers a physical MSI to signal the core that a virtual interrupt should be injected. If a vCPU triggers an MSI on the current core then a virtual interrupt is injected directly without causing a physical interrupt. This is an important first step toward allowing out-of-band (host) MSI, which are required by some security policies for cross-caches flushes.
This commit adds three integration tests to exercise the new machine timer (MTI) and software (MSI) interrupts. The tests exercise: 1. (clint_interrupt) the MTI, including proper reset and multiple interrupts delivery. 2. (clint_interrupt_multihart) the MSI across cores. 3. (clint_interrupt_priority) the relative priority of interrupts delivery between MSI and MTI. Co-authored-by: Sofia <[email protected]>
Update the documentation to clarify that only M-mode interrupts are virtualized, and that S-mode interrupts are explicitly out-of-scope. Also removes some white-spaces in the doc ASCII art of the relevant section, as those can cause rendering issue on the website.
The new crate can be extended in the future to hold more test helpers, such as macros to generate proper interrupt handlers. For now it is limited to clint functionalities and assumes the QEMU virt platform (it is not meant to be a general-purpose library).
CharlyCst
force-pushed
the
push-xrwkmynnvkst
branch
from
9c541dc
to
c6efea4
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR implements proper full M-mode interrupts virtualization, as outlined in #186.
Full interrupt virtualization changes the way interrupts are handled: instead of re-injecting physical interrupts into the vCPU (like we use to do until this PR) Miralis maintains the state of the virtual
mipbits for the virtualized interrupts itself and checks if an interrupt should be injected before each re-entry.This is an important change because: