CIM processor: system dataflow implementation using verilog

Architecture

[1] PIMCA [2] ISSCC2020

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
pattern		pattern
.gitignore		.gitignore
Activation_sram_32x768.v		Activation_sram_32x768.v
Add.v		Add.v
Add_tb.v		Add_tb.v
Adder_Tree.v		Adder_Tree.v
Adder_Tree_tb.v		Adder_Tree_tb.v
Aggregator.v		Aggregator.v
Aggregator_tb.v		Aggregator_tb.v
CIM_Unit.v		CIM_Unit.v
CIM_Unit_tb.v		CIM_Unit_tb.v
Core.v		Core.v
Core_tb.v		Core_tb.v
Instruction_sram_32x32.v		Instruction_sram_32x32.v
Macro.v		Macro.v
Macro_Array.v		Macro_Array.v
Macro_Array_tb.v		Macro_Array_tb.v
Macro_tb.v		Macro_tb.v
NMC.v		NMC.v
PE.v		PE.v
PE_tb.v		PE_tb.v
README.md		README.md
ReLU.v		ReLU.v
ReLU_tb.v		ReLU_tb.v
Top.v		Top.v
Weight_sram_32x2304.v		Weight_sram_32x2304.v
tb_template.v		tb_template.v
weight_sram_wrapper_32X30.v		weight_sram_wrapper_32X30.v