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RISC-V: Tweak generic vector COST model
Notice current generic vector cost model make PR112387 failed to vectorize. Adapt it same as ARM SVE generic vector cost model which can fix it. Committed as it is obvious fix. PR target/112387 gcc/ChangeLog: * config/riscv/riscv.cc: Adapt generic cost model same ARM SVE. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr112387.c: Moved to... * gcc.dg/vect/costmodel/riscv/rvv/pr112387-1.c: ...here. * gcc.dg/vect/costmodel/riscv/rvv/pr112387-2.c: New test.
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gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr112387-2.c
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/* { dg-do compile } */ | ||
/* { dg-options "-march=rv64gcv -mabi=lp64d -mtune=generic-ooo -O3 -ftree-vectorize -fdump-tree-vect-details" } */ | ||
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#include <stdint-gcc.h> | ||
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void | ||
f2 (uint64_t *__restrict y, uint64_t *__restrict x, | ||
uint64_t *__restrict indices, uint64_t n) | ||
{ | ||
for (int64_t i = 0; i < n; ++i) | ||
{ | ||
y[i * 2] = x[indices[i * 2]] + 1; | ||
y[i * 2 + 1] = x[indices[i * 2 + 1]] + 2; | ||
} | ||
} | ||
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/* { dg-final { scan-tree-dump "Loop contains only SLP stmts" vect } } */ | ||
/* { dg-final { scan-assembler-not "vlseg" } } */ | ||
/* { dg-final { scan-assembler-not "vsseg" } } */ |