ref(riscv): centralize check for sstc extension

Signed-off-by: Jose Martins <[email protected]>

src/arch/riscv/vm.c

@@ -43,10 +43,7 @@ void vcpu_arch_reset(struct vcpu* vcpu, vaddr_t entry)
     vcpu->regs.a1 = 0; // according to sbi it should be the dtb load address
 
     if (CPU_HAS_EXTENSION(CPU_EXT_SSTC)) {
-        CSRW(CSR_STIMECMP, -1);
-        CSRS(CSR_HENVCFG, HENVCFG_STCE);
-    } else {
-        CSRC(CSR_HENVCFG, HENVCFG_STCE);
+        CSRW(CSR_VSTIMECMP, -1);
     }
     CSRW(CSR_HCOUNTEREN, HCOUNTEREN_TM);
     CSRW(CSR_HTIMEDELTA, 0);

src/arch/riscv/vmm.c

@@ -21,6 +21,24 @@ void vmm_arch_init()
     CSRW(CSR_HIDELEG, HIDELEG_VSSI | HIDELEG_VSTI | HIDELEG_VSEI);
     CSRW(CSR_HEDELEG, HEDELEG_ECU | HEDELEG_IPF | HEDELEG_LPF | HEDELEG_SPF);
 
+    /**
+     * Enable and sanity check presence of Sstc extension if the hypervisor was
+     * configured to use it (via the CPU_EXT_SSTC macro). Otherwise, make sure
+     * it is disabled.
+     */
+    if (CPU_HAS_EXTENSION(CPU_EXT_SSTC)) {
+        CSRS(CSR_HENVCFG, HENVCFG_STCE);
+        bool sstc_present = (CSRR(CSR_HENVCFG) & HENVCFG_STCE) != 0;
+        if (cpu_is_master() && !sstc_present) {
+            ERROR("Platform configured to use Sstc extension, but extension not present.");
+        }
+        // Set stimecmp to infinity in case we enable the stimer interrupt somewhere else
+        // and fail to set the timer to a point in the future.
+        CSRS(CSR_STIMECMP, -1);
+    } else {
+        CSRC(CSR_HENVCFG, HENVCFG_STCE);
+    }
+
     /**
      * TODO: consider delegating other exceptions e.g. breakpoint or ins misaligned
      */