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Merge pull request #2 from DASICS-ICT/update-master
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Update master for configs and options merging
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@Gwins7
Gwins7 authored Sep 29, 2024
2 parents 6004d19 + d2015ca commit 2eeed40
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Showing 5 changed files with 179 additions and 39 deletions.
4 changes: 2 additions & 2 deletions .github/workflows/emu.yml
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Expand Up @@ -3,9 +3,9 @@ name: EMU Test

on:
push:
branches: [ master, nanhu ]
branches: [ ]
pull_request:
branches: [ master, nanhu ]
branches: [ ]

jobs:
generate-verilog:
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128 changes: 128 additions & 0 deletions src/main/scala/top/Configs.scala
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Expand Up @@ -56,6 +56,7 @@ class MinimalConfig(n: Int = 1) extends Config(
case XSTileKey => up(XSTileKey).map(
_.copy(
HasNExtension = true,
HasDasics = true,
DecodeWidth = 2,
RenameWidth = 2,
FetchWidth = 4,
Expand Down Expand Up @@ -317,3 +318,130 @@ class DefaultConfig(n: Int = 1) extends Config(
++ new WithNKBL1D(64)
++ new BaseConfig(n)
)

/*** Nanhu General Config ( Nanhu-G Config) ***/
// XSCore Config:
// * Including Frontend/Backend/MMU/MemBlock
// * Including DebugOptions
// * Not Including L1D/L2/L3 Cache
class NanHuGCoreConfig(n: Int = 1) extends Config(
new BaseConfig(n).alter((site, here, up) => {
case XSTileKey => up(XSTileKey).map(
_.copy(
HasNExtension = true,
HasDasics = true,
DecodeWidth = 4,
RenameWidth = 4,
FetchWidth = 8,
IssQueSize = 8,
NRPhyRegs = 64,
LoadQueueSize = 32,
LoadQueueNWriteBanks = 4,
StoreQueueSize = 24,
StoreQueueNWriteBanks = 4,
RobSize = 96,
FtqSize = 16,
IBufSize = 32,
StoreBufferSize = 4,
StoreBufferThreshold = 3,
dpParams = DispatchParameters(
IntDqSize = 12,
FpDqSize = 12,
LsDqSize = 12,
IntDqDeqWidth = 4,
FpDqDeqWidth = 4,
LsDqDeqWidth = 4
),
exuParameters = ExuParameters(
JmpCnt = 1,
AluCnt = 2,
MulCnt = 0,
MduCnt = 1,
FmacCnt = 1,
FmiscCnt = 1,
FmiscDivSqrtCnt = 0,
LduCnt = 2,
StuCnt = 2
),
//prefetcher = None,
EnableSC = false,
EnableLoop = false,
FtbSize = 1024,
UbtbSize = 128,
// 4-way 16KB DCache
icacheParameters = ICacheParameters(
nSets = 64,
nWays = 4,
tagECC = None,
dataECC = None,
replacer = Some("setplru"),
nMissEntries = 2,
nReleaseEntries = 1,
nProbeEntries = 2,
nPrefetchEntries = 2,
hasPrefetch = false
),
itlbParameters = TLBParameters(
name = "itlb",
fetchi = true,
useDmode = false,
sameCycle = false,
missSameCycle = true,
normalReplacer = Some("plru"),
superReplacer = Some("plru"),
normalNWays = 4,
normalNSets = 1,
superNWays = 2,
shouldBlock = true
),
ldtlbParameters = TLBParameters(
name = "ldtlb",
normalNSets = 16, // 6when da or sa
normalNWays = 1, // when fa or sa
normalAssociative = "sa",
normalReplacer = Some("setplru"),
superNWays = 4,
normalAsVictim = true,
partialStaticPMP = true,
outReplace = false
),
sttlbParameters = TLBParameters(
name = "sttlb",
normalNSets = 16, // when da or sa
normalNWays = 1, // when fa or sa
normalAssociative = "sa",
normalReplacer = Some("setplru"),
normalAsVictim = true,
superNWays = 4,
partialStaticPMP = true,
outReplace = false
),
btlbParameters = TLBParameters(
name = "btlb",
normalNSets = 1,
normalNWays = 8,
superNWays = 2
),
l2tlbParameters = L2TLBParameters(
l1Size = 4,
l2nSets = 4,
l2nWays = 4,
l3nSets = 4,
l3nWays = 8,
spSize = 2,
)
)
)
})
)
// Cache Hierarchy Config:
// * Including L1D/L2/L3 Cache
class NanHuGCacheConfig extends Config(
new WithNKBL3(6 * 256, inclusive = false, banks = 4, ways = 6)
++ new WithNKBL2(256,inclusive = false, banks = 4, alwaysReleaseData = true)
++ new WithNKBL1D(32)
)
// XSSoC Config:
class NanHuGConfig(n: Int = 1) extends Config(
new NanHuGCacheConfig ++ new NanHuGCoreConfig(n)
)
33 changes: 20 additions & 13 deletions src/main/scala/xiangshan/backend/MemBlock.scala
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Expand Up @@ -251,23 +251,30 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
dtlb_st.foreach(_.ptw.resp.valid := ptw_resp_v && Cat(ptw_resp_next.vector.drop(ld_tlb_ports)).orR)
}

// dasics memory access check
val dasics = Module(new MemDasics())
dasics.io.distribute_csr <> csrCtrl.distribute_csr

val dasics_checkers = VecInit(Seq.fill(exuParameters.LduCnt + exuParameters.StuCnt)(
Module(new DasicsMemChecker()).io
)) //TODO: general Dasics check port config

val memDasicsReq = storeUnits.map(_.io.dasicsReq) ++ loadUnits.map(_.io.dasicsReq)
val memDasicsResp = storeUnits.map(_.io.dasicsResp) ++ loadUnits.map(_.io.dasicsResp)

for( (dchecker,index) <- dasics_checkers.zipWithIndex){
dchecker.mode := csrCtrl.mode
dchecker.resource := dasics.io.entries
dchecker.mainCfg := dasics.io.mainCfg
dchecker.req := memDasicsReq(index)
memDasicsResp(index) := dchecker.resp
memDasicsResp.map{resp =>
resp.dasics_fault := DasicsCheckFault.noDasicsFault
}

if(HasDasics){
// dasics memory access check
val dasics = Module(new MemDasics())
dasics.io.distribute_csr <> csrCtrl.distribute_csr

val dasics_checkers = VecInit(Seq.fill(exuParameters.LduCnt + exuParameters.StuCnt)(
Module(new DasicsMemChecker()).io
)) //TODO: general Dasics check port config

for( (dchecker,index) <- dasics_checkers.zipWithIndex){
dchecker.mode := csrCtrl.mode
dchecker.resource := dasics.io.entries
dchecker.mainCfg := dasics.io.mainCfg
dchecker.req := memDasicsReq(index)
memDasicsResp(index) := dchecker.resp
}
}

// pmp
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16 changes: 8 additions & 8 deletions src/main/scala/xiangshan/backend/fu/CSR.scala
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Expand Up @@ -1002,8 +1002,8 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
csrExceptionVec(ecallS) := priviledgeMode === ModeS && io.in.valid && isEcall && (!isUntrusted || isUntrusted && dasics_main_cfg.closeSEcallFault)
csrExceptionVec(ecallU) := priviledgeMode === ModeU && io.in.valid && isEcall && (!isUntrusted || isUntrusted && dasics_main_cfg.closeUEcallFault)

csrExceptionVec(dasicsUEcallAccessFault) := priviledgeMode === ModeU && io.in.valid && isEcall && isUntrusted && !dasics_main_cfg.closeUEcallFault
csrExceptionVec(dasicsSEcallAccessFault) := priviledgeMode === ModeS && io.in.valid && isEcall && isUntrusted && !dasics_main_cfg.closeSEcallFault
csrExceptionVec(dasicsUEcallAccessFault) := HasDasics.B && priviledgeMode === ModeU && io.in.valid && isEcall && isUntrusted && !dasics_main_cfg.closeUEcallFault
csrExceptionVec(dasicsSEcallAccessFault) := HasDasics.B && priviledgeMode === ModeS && io.in.valid && isEcall && isUntrusted && !dasics_main_cfg.closeSEcallFault

// Trigger an illegal instr exception when:
// * unimplemented csr is being read/written
Expand Down Expand Up @@ -1088,12 +1088,12 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
val hasPKSLoadPageFault = hasException && exceptionVecFromRob(pksLoadPageFault)
val hasPKSStorePageFault = hasException && exceptionVecFromRob(pksStorePageFault)
val hasBreakPoint = hasException && exceptionVecFromRob(breakPoint)
val hasDasicsULoadFault = hasException && exceptionVecFromRob(dasicsULoadAccessFault)
val hasDasicsSLoadFault = hasException && exceptionVecFromRob(dasicsSLoadAccessFault)
val hasDasicsUStoreFault = hasException && exceptionVecFromRob(dasicsUStoreAccessFault)
val hasDasicsSStoreFault = hasException && exceptionVecFromRob(dasicsSStoreAccessFault)
val hasDasicsUFetchFault = hasException && exceptionVecFromRob(dasicsUIntrAccessFault)
val hasDasicsSFetchFault = hasException && exceptionVecFromRob(dasicsSIntrAccessFault)
val hasDasicsULoadFault = HasDasics.B && hasException && exceptionVecFromRob(dasicsULoadAccessFault)
val hasDasicsSLoadFault = HasDasics.B && hasException && exceptionVecFromRob(dasicsSLoadAccessFault)
val hasDasicsUStoreFault = HasDasics.B && hasException && exceptionVecFromRob(dasicsUStoreAccessFault)
val hasDasicsSStoreFault = HasDasics.B && hasException && exceptionVecFromRob(dasicsSStoreAccessFault)
val hasDasicsUFetchFault = HasDasics.B && hasException && exceptionVecFromRob(dasicsUIntrAccessFault)
val hasDasicsSFetchFault = HasDasics.B && hasException && exceptionVecFromRob(dasicsSIntrAccessFault)
// interrupt and dasics fetch both occurs
val hasDasicsFetchIntr =
hasIntr && (exceptionVecFromRob(dasicsUIntrAccessFault) || exceptionVecFromRob(dasicsSIntrAccessFault))
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37 changes: 21 additions & 16 deletions src/main/scala/xiangshan/frontend/Frontend.scala
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Expand Up @@ -21,7 +21,7 @@ import chisel3.util._
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import utils._
import xiangshan._
import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle, DasicsTagger, DasicsBranchChecker}
import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle, DasicsTagger, DasicsBranchChecker, DasicsCheckFault}
import xiangshan.cache.mmu._
import xiangshan.frontend.icache._

Expand Down Expand Up @@ -95,21 +95,26 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
icache.io.pmp(2).resp <> pmp_check(2).resp
ifu.io.pmp.resp <> pmp_check(3).resp

// dasicsTagger
val dasicsTagger: DasicsTagger = Module(new DasicsTagger())
dasicsTagger.io.distribute_csr := csrCtrl.distribute_csr
dasicsTagger.io.privMode := tlbCsr.priv.imode
dasicsTagger.io.addr := ifu.io.dasics.startAddr
ifu.io.dasics.notTrusted := dasicsTagger.io.notTrusted

// dasics branch checker
val dasicsBrChecker: DasicsBranchChecker = Module(new DasicsBranchChecker())
dasicsBrChecker.io.distribute_csr := csrCtrl.distribute_csr
dasicsBrChecker.io.mode := tlbCsr.priv.imode
dasicsBrChecker.io.valid := ifu.io.dasics.lastBranch.valid
dasicsBrChecker.io.lastBranch := ifu.io.dasics.lastBranch.bits
dasicsBrChecker.io.target := ifu.io.dasics.startAddr
ifu.io.dasics.brResp := dasicsBrChecker.io.resp.dasics_fault
require(!(HasDasics ^ HasNExtension), s"Only support using N-Extension for DASICS")
ifu.io.dasics.brResp := DasicsCheckFault.noDasicsFault
ifu.io.dasics.notTrusted := VecInit(Seq.fill(FetchWidth * 2){ false.B })
if(HasDasics){
// dasicsTagger
val dasicsTagger: DasicsTagger = Module(new DasicsTagger())
dasicsTagger.io.distribute_csr := csrCtrl.distribute_csr
dasicsTagger.io.privMode := tlbCsr.priv.imode
dasicsTagger.io.addr := ifu.io.dasics.startAddr
ifu.io.dasics.notTrusted := dasicsTagger.io.notTrusted

// dasics branch checker
val dasicsBrChecker: DasicsBranchChecker = Module(new DasicsBranchChecker())
dasicsBrChecker.io.distribute_csr := csrCtrl.distribute_csr
dasicsBrChecker.io.mode := tlbCsr.priv.imode
dasicsBrChecker.io.valid := ifu.io.dasics.lastBranch.valid
dasicsBrChecker.io.lastBranch := ifu.io.dasics.lastBranch.bits
dasicsBrChecker.io.target := ifu.io.dasics.startAddr
ifu.io.dasics.brResp := dasicsBrChecker.io.resp.dasics_fault
}

// val tlb_req_arb = Module(new Arbiter(new TlbReq, 2))
// tlb_req_arb.io.in(0) <> ifu.io.iTLBInter.req
Expand Down

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