Merge branch 'master' into sync-v5-isa

DASICS-ICT · Sep 29, 2024 · c24f203 · c24f203
2 parents 166b8b6 + 41634d9
commit c24f203
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diff --git a/.github/workflows/emu.yml b/.github/workflows/emu.yml
@@ -3,147 +3,6 @@ name: EMU Test
 
 on:
   push:
-    branches: [ master, nanhu ]
+    branches: [ none ]
   pull_request:
-    branches: [ master, nanhu ]
-
-jobs:
-  generate-verilog:
-    runs-on: bosc
-    continue-on-error: false
-    name: Generate Verilog
-    steps:
-      - uses: actions/checkout@v2
-        with:
-          submodules: 'recursive'
-      - name: set env
-        run: |
-          export HEAD_SHA=${{ github.run_number }}
-          echo "RELEASE_SHA=${GITHUB_SHA::7}" >> $GITHUB_ENV
-          echo "NEMU_HOME=/nfs/home/share/ci-workloads/NEMU" >> $GITHUB_ENV
-          echo "WAVE_HOME=/nfs/home/ci-runner/xs-wave/${HEAD_SHA}" >> $GITHUB_ENV
-          echo "RELEASE_HOME=/nfs/home/share/nanhu_release" >> $GITHUB_ENV
-          echo "XSTOP_RELEASE_HOME=/nfs/home/share/nanhu_XSTop_release" >> $GITHUB_ENV
-          mkdir -p /nfs/home/ci-runner/xs-wave/${HEAD_SHA}
-      - name: clean up
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
-      - name: check top wiring
-        run:
-          bash .github/workflows/check-usage.sh "BoringUtils" $GITHUB_WORKSPACE
-      - name: generate verilog file
-        run:
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --generate --num-cores 2
-      - name: check verilog
-        run:
-          python3 $GITHUB_WORKSPACE/.github/workflows/check_verilog.py build/XSTop.v
-      - name: release
-        run: |
-          rsync -av /nfs-nvme/home/share/debug/nanhu .
-          mv nanhu nanhu_release
-          python3 $GITHUB_WORKSPACE/scripts/parser.py --xs-home $GITHUB_WORKSPACE
-          cp build/XSTop.graphml rtl/XSTop.graphml
-          cp build/build/XSTop.v.conf rtl/XSTop.v.conf
-          python3 $GITHUB_WORKSPACE/scripts/get_flist_rtl.py nanhu_release
-          mv rtl nanhu_release/rtl
-          tar -czf $XSTOP_RELEASE_HOME/nanhu_release-${RELEASE_SHA}.tar.gz nanhu_release
-          rm -rf nanhu_release
-
-  emu-basics:
-    runs-on: bosc
-    continue-on-error: false
-    timeout-minutes: 900
-    name: EMU - Basics
-    steps:
-      - uses: actions/checkout@v2
-        with:
-          submodules: 'recursive'
-      - name: set env
-        run: |
-          export HEAD_SHA=${{ github.run_number }}
-          echo "NEMU_HOME=/nfs/home/share/ci-workloads/NEMU" >> $GITHUB_ENV
-          echo "AM_HOME=/nfs/home/share/ci-workloads/nexus-am" >> $GITHUB_ENV
-          echo "PERF_HOME=/nfs/home/ci-runner/xs-perf/${HEAD_SHA}" >> $GITHUB_ENV
-          echo "WAVE_HOME=/nfs/home/ci-runner/xs-wave/${HEAD_SHA}" >> $GITHUB_ENV
-          mkdir -p /nfs/home/ci-runner/xs-perf/${HEAD_SHA}
-          mkdir -p /nfs/home/ci-runner/xs-wave/${HEAD_SHA}
-      - name: clean up
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
-      - name: Build EMU
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --build --threads 8
-      - name: Basic Test - cputest
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --ci cputest 2> /dev/zero
-      - name: Basic Test - riscv-tests
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --rvtest /nfs/home/share/ci-workloads/riscv-tests --ci riscv-tests 2> /dev/zero
-      - name: Basic Test - privilege-tests
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --ci privilege 2> /dev/null  
-      - name: Basic Test - misc-tests
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci misc-tests 2> /dev/zero
-      - name: Basic Test - nodiff-tests
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --no-diff --ci nodiff-tests 2> /dev/zero
-      - name: Random SPEC 0
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci random --timeout 3600 2> perf.log
-          cat perf.log | sort | tee $PERF_HOME/random_0.log
-      - name: Random SPEC 1
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci random --timeout 3600 2> perf.log
-          cat perf.log | sort | tee $PERF_HOME/random_1.log
-      - name: Random SPEC 2
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci random --timeout 3600 2> perf.log
-          cat perf.log | sort | tee $PERF_HOME/random_2.log
-      - name: Random SPEC 3
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 8 --numa --ci random --timeout 3600 2> perf.log
-          cat perf.log | sort | tee $PERF_HOME/random_3.log
-      - name: Uncache Fetch Test - copy and run
-        run: |
-          $GITHUB_WORKSPACE/build/emu  -F $GITHUB_WORKSPACE/ready-to-run/copy_and_run.bin -i $GITHUB_WORKSPACE/ready-to-run/microbench.bin --diff $GITHUB_WORKSPACE/ready-to-run/riscv64-nemu-interpreter-so --enable-fork 2> perf.log
-          cat perf.log | sort | tee $PERF_HOME/copy_and_run.log
-      - name: Uncache Fetch Test - recursion
-        run: |
-          $GITHUB_WORKSPACE/build/emu  -F $GITHUB_WORKSPACE/ready-to-run/flash_recursion_test.bin -i $GITHUB_WORKSPACE/ready-to-run/microbench.bin --diff $GITHUB_WORKSPACE/ready-to-run/riscv64-nemu-interpreter-so --enable-fork 2> perf.log
-          cat perf.log | sort | tee $PERF_HOME/flash_recursion.log
-
-  emu-mc:
-    runs-on: bosc
-    continue-on-error: false
-    timeout-minutes: 900
-    name: EMU - MC
-    steps:
-      - uses: actions/checkout@v2
-        with:
-          submodules: 'recursive'
-      - name: set env
-        run: |
-          export HEAD_SHA=${{ github.run_number }}
-          echo "NEMU_HOME=/nfs/home/share/ci-workloads/NEMU" >> $GITHUB_ENV
-          echo "AM_HOME=/nfs/home/share/ci-workloads/nexus-am" >> $GITHUB_ENV
-          echo "PERF_HOME=/nfs/home/ci-runner/xs-perf/${HEAD_SHA}" >> $GITHUB_ENV
-          echo "WAVE_HOME=/nfs/home/ci-runner/xs-wave/${HEAD_SHA}" >> $GITHUB_ENV
-          mkdir -p /nfs/home/ci-runner/xs-perf/${HEAD_SHA}
-          mkdir -p /nfs/home/ci-runner/xs-wave/${HEAD_SHA}
-      - name: clean up
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --clean
-      - name: Build MC EMU
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --build \
-            --num-cores 2 \
-            --dramsim3 /nfs/home/share/ci-workloads/DRAMsim3 \
-            --with-dramsim3 --threads 16
-      - name: MC Test
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --numa --diff ./ready-to-run/riscv64-nemu-interpreter-dual-so --ci mc-tests 2> /dev/zero
-      - name: SMP Linux
-        run: |
-          python3 $GITHUB_WORKSPACE/scripts/xiangshan.py --wave-dump $WAVE_HOME --threads 16 --numa --diff ./ready-to-run/riscv64-nemu-interpreter-dual-so --ci linux-hello-smp 2> /dev/zero
-
+    branches: [ none ]
diff --git a/src/main/scala/top/Configs.scala b/src/main/scala/top/Configs.scala
@@ -56,6 +56,7 @@ class MinimalConfig(n: Int = 1) extends Config(
     case XSTileKey => up(XSTileKey).map(
       _.copy(
         HasNExtension = true,
+        HasDasics = true,
         DecodeWidth = 2,
         RenameWidth = 2,
         FetchWidth = 4,
@@ -317,3 +318,130 @@ class DefaultConfig(n: Int = 1) extends Config(
     ++ new WithNKBL1D(64)
     ++ new BaseConfig(n)
 )
+
+/*** Nanhu General Config ( Nanhu-G Config) ***/
+// XSCore Config: 
+// * Including Frontend/Backend/MMU/MemBlock
+// * Including DebugOptions
+// * Not Including L1D/L2/L3 Cache
+class NanHuGCoreConfig(n: Int = 1) extends Config(
+  new BaseConfig(n).alter((site, here, up) => {
+    case XSTileKey => up(XSTileKey).map(
+      _.copy(
+        HasNExtension = true,
+        HasDasics = true,
+        DecodeWidth = 4,
+        RenameWidth = 4,
+        FetchWidth = 8,
+        IssQueSize = 8,
+        NRPhyRegs = 64,
+        LoadQueueSize = 32,
+        LoadQueueNWriteBanks = 4,
+        StoreQueueSize = 24,
+        StoreQueueNWriteBanks = 4,
+        RobSize = 96,
+        FtqSize = 16,
+        IBufSize = 32,
+        StoreBufferSize = 4,
+        StoreBufferThreshold = 3,
+        dpParams = DispatchParameters(
+          IntDqSize = 12,
+          FpDqSize = 12,
+          LsDqSize = 12,
+          IntDqDeqWidth = 4,
+          FpDqDeqWidth = 4,
+          LsDqDeqWidth = 4
+        ),
+        exuParameters = ExuParameters(
+          JmpCnt = 1,
+          AluCnt = 2,
+          MulCnt = 0,
+          MduCnt = 1,
+          FmacCnt = 1,
+          FmiscCnt = 1,
+          FmiscDivSqrtCnt = 0,
+          LduCnt = 2,
+          StuCnt = 2
+        ),
+        //prefetcher = None,
+        EnableSC = false,
+        EnableLoop = false,
+        FtbSize = 1024,
+        UbtbSize = 128,
+        // 4-way 16KB DCache        
+        icacheParameters = ICacheParameters(
+          nSets = 64, 
+          nWays = 4,
+          tagECC = None,
+          dataECC = None,
+          replacer = Some("setplru"),
+          nMissEntries = 2,
+          nReleaseEntries = 1,
+          nProbeEntries = 2,
+          nPrefetchEntries = 2,
+          hasPrefetch = false
+        ),
+        itlbParameters = TLBParameters(
+          name = "itlb",
+          fetchi = true,
+          useDmode = false,
+          sameCycle = false,
+          missSameCycle = true,
+          normalReplacer = Some("plru"),
+          superReplacer = Some("plru"),
+          normalNWays = 4,
+          normalNSets = 1,
+          superNWays = 2,
+          shouldBlock = true
+        ),
+        ldtlbParameters = TLBParameters(
+          name = "ldtlb",
+          normalNSets = 16, // 6when da or sa
+          normalNWays = 1, // when fa or sa
+          normalAssociative = "sa",
+          normalReplacer = Some("setplru"),
+          superNWays = 4,
+          normalAsVictim = true,
+          partialStaticPMP = true,
+          outReplace = false
+        ),
+        sttlbParameters = TLBParameters(
+          name = "sttlb",
+          normalNSets = 16, // when da or sa
+          normalNWays = 1, // when fa or sa
+          normalAssociative = "sa",
+          normalReplacer = Some("setplru"),
+          normalAsVictim = true,
+          superNWays = 4,
+          partialStaticPMP = true,
+          outReplace = false
+        ),
+        btlbParameters = TLBParameters(
+          name = "btlb",
+          normalNSets = 1,
+          normalNWays = 8,
+          superNWays = 2
+        ),
+        l2tlbParameters = L2TLBParameters(
+          l1Size = 4,
+          l2nSets = 4,
+          l2nWays = 4,
+          l3nSets = 4,
+          l3nWays = 8,
+          spSize = 2,
+        )
+      )
+    )
+  })
+)
+// Cache Hierarchy Config: 
+// * Including L1D/L2/L3 Cache
+class NanHuGCacheConfig extends Config(
+  new WithNKBL3(6 * 256, inclusive = false, banks = 4, ways = 6)
+  ++ new WithNKBL2(256,inclusive = false, banks = 4, alwaysReleaseData = true) 
+  ++ new WithNKBL1D(32) 
+)
+// XSSoC Config:
+class NanHuGConfig(n: Int = 1) extends Config(
+  new NanHuGCacheConfig ++ new NanHuGCoreConfig(n)
+)
diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala
@@ -251,22 +251,30 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     dtlb_st.foreach(_.ptw.resp.valid := ptw_resp_v && Cat(ptw_resp_next.vector.drop(ld_tlb_ports)).orR)
   }
 
-  // dasics memory access check
-  val dasics = Module(new MemDasics())
-  dasics.io.distribute_csr <> csrCtrl.distribute_csr
-
-  private val dasicsCheckers = Seq.fill(exuParameters.LduCnt + exuParameters.StuCnt)(Module(new DasicsMemChecker()))
-  private val dasicsCheckersIOs = dasicsCheckers.map(_.io)
-
   val memDasicsReq  = storeUnits.map(_.io.dasicsReq) ++ loadUnits.map(_.io.dasicsReq)
   val memDasicsResp = storeUnits.map(_.io.dasicsResp) ++ loadUnits.map(_.io.dasicsResp)
 
-  for( (dchecker,index) <- dasicsCheckersIOs.zipWithIndex){
-     dchecker.mode := csrCtrl.mode
-     dchecker.mainCfg := dasics.io.mainCfg
-     dchecker.resource := dasics.io.entries
-     dchecker.req := memDasicsReq(index)
-     memDasicsResp(index) := dchecker.resp
+  memDasicsResp.map{resp =>
+    resp.mode := csrCtrl.mode
+    resp.dasics_fault := DasicsFaultReason.noDasicsFault
+  }
+
+  if(HasDasics){
+    // dasics memory access check
+    val dasics = Module(new MemDasics())
+    dasics.io.distribute_csr <> csrCtrl.distribute_csr
+
+    val dasics_checkers = VecInit(Seq.fill(exuParameters.LduCnt + exuParameters.StuCnt)(
+      Module(new DasicsMemChecker()).io
+    )) //TODO: general Dasics check port config
+
+    for( (dchecker,index) <- dasics_checkers.zipWithIndex){
+      dchecker.mode := csrCtrl.mode
+      dchecker.resource := dasics.io.entries
+      dchecker.mainCfg  := dasics.io.mainCfg
+      dchecker.req := memDasicsReq(index)
+      memDasicsResp(index) := dchecker.resp
+    }
   }
 
   // pmp