Merge pull request #1 from ajblane/iota-fpga-sockit

Arrow SoCKit Evaluation Board Enablement

README.md

@@ -22,6 +22,37 @@ PoC parameters:
 
 [Download](https://github.com/LampaLab/iota_fpga/releases/tag/v0.1) Linux sd-card image for IOTA hardware accelerator on DE10-nano board and [latest](https://github.com/LampaLab/iota_fpga/releases/tag/v0.3) rbf file
 
+## Arrow SoCKit board
+Build instructions mentioned RBF file for Arrow SoCKit board. For the sake of consistency, we host FPGA related repository under DLTcollab umbrella.
+
+### Generate the RBF file
+* Install Intel Quartus Prime Lite Edition 17.1 and run synthesizing
+* Transform SOF file to RBF file
+```
+ ~/intelFPGA_lite/17.1/quartus/bin/quartus_cpf -c curl_fpga.sof soc_system.rbf
+```
+
+### Quickly start from scratch
+* [Download](https://github.com/LampaLab/iota_fpga/releases/tag/v0.1) Linux sd-card image for Cyclone V
+* The RBF file for Arrow SocKit board
+* Creating an SD Card using a Linux Host
+```
+$ sudo dd if=DE10_iota_fpga_Linux.img of=/dev/sdb bs=2048
+$ sudo sync
+```
+* Overwrite the RBF file in the SD card
+```
+$ sudo mkdir sdcard
+$ sudo mount /dev/sdb1 sdcard/
+$ sudo cp soc_system.rbf sdcard/
+$ sudo umount sdcard
+```
+
+* Connect to remote shell (account/password: root/123456)
+```
+$ ssh [email protected]
+```
+
 If you like this work, please donate some MIOTA to support it further development: 
 
 [U9XOVBWJUBCE99ZIKIUGXZFSSGLUAPHUG9XZTVOVHZ99HVTQXET9CD9V9FMDNLSLPQDYXOHKBA9MVHI9ZOVCVHVJXA](https://thetangle.org/address/U9XOVBWJUBCE99ZIKIUGXZFSSGLUAPHUG9XZTVOVHZ99HVTQXET9CD9V9FMDNLSLPQDYXOHKBA9MVHI9Z)

pow_accel_soc/hardware/constraints.sdc

@@ -2,7 +2,7 @@ create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
 create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
 create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
 
-create_clock -period 200MHz [get_pins -compatibility_mode u0|hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk]
+create_clock -period 100MHz [get_pins -compatibility_mode u0|hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk]
 
 derive_pll_clocks
 

pow_accel_soc/hardware/curl_fpga.qsf

@@ -37,14 +37,14 @@
 
 
 set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name DEVICE 5CSEBA6U23I7
+set_global_assignment -name DEVICE 5CSXFC6D6F31C6
 set_global_assignment -name TOP_LEVEL_ENTITY soc_top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:03:21  FEBRUARY 11, 2018"
 set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
@@ -54,8 +54,8 @@ set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_location_assignment PIN_V11 -to FPGA_CLK1_50
-set_location_assignment PIN_Y13 -to FPGA_CLK2_50
+set_location_assignment PIN_W15 -to FPGA_CLK1_50
+set_location_assignment PIN_AA16 -to FPGA_CLK2_50
 set_location_assignment PIN_E11 -to FPGA_CLK3_50
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 set_global_assignment -name ECO_REGENERATE_REPORT ON