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ElectronicCats / Multifunctional-signal-generator_verilog Public template

forked from TinyTapeout/tt08-verilog-template

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gds

feat: bits truncation in UART #62

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feat: bits truncation in UART

feat: bits truncation in UART #62

Summary
Jobs
- gds
- precheck
- gl_test
- viewer
Run details
- Usage
- Workflow file

Usage Workflow file

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1 error

The run was canceled by @Elizabeth-0.

gl_test

cancelled Nov 5, 2024 in 11m 4s

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