Merge pull request #372 from GSI-CS-CO/fallout

Saftlib v3.1.3 + eb-reset patch (force)
GSI-CS-CO · Jul 25, 2024 · 1af3733 · 1af3733
2 parents 7331c55 + 85c98e0
commit 1af3733
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Showing 5 changed files with 45 additions and 36 deletions.
diff --git a/README.md b/README.md
@@ -269,11 +269,11 @@ Solution: In case a simple "make" does not fix this:
 make hdlmake_install
 ```
 
-#### Tool hdlmake not found (Python 2.7)
+#### Tool hdlmake not found (for both Python 2.7 & Python 3.x)
 
 Error: /bin/sh: 1: hdlmake: not found
 
-Solution: You should run "make" to install hdlmake locally. In case you're still using Python 2.7 you have to adjust your PATH variable:
+Solution: You should run "make" to install hdlmake locally and adjust your PATH variable:
 
 ```
 export PATH=$PATH:$HOME/.local/bin

diff --git a/ip_cores/saftlib b/ip_cores/saftlib
diff --git a/tools/eb-reset.c b/tools/eb-reset.c
@@ -3,7 +3,7 @@
  *
  *  created : 2017
  *  author  : Dietrich Beck, GSI-Darmstadt
- *  version : 02-Jun-2021
+ *  version : 25-Jul-2024
  *
  * Command-line interface for resetting a FPGA. This forces a restart using the image stored
  * in the local flash of the timing receiver.
@@ -36,7 +36,7 @@
  * For all questions and ideas contact: [email protected]
  * Last update: 01-December-2017
  ********************************************************************************************/
-#define EBRESET_VERSION "1.3.0"
+#define EBRESET_VERSION "1.3.1"
 
 // standard includes
 #include <unistd.h> // getopt
@@ -71,6 +71,8 @@ static void help(void) {
   fprintf(stderr, "\n");
   fprintf(stderr, "  -e               display etherbone version\n");
   fprintf(stderr, "  -p<t>            after FPGA reset, wait for the specified time [s] and probe device\n");
+  fprintf(stderr, "  -f               force 'fpgareset' of FPGA with incompatible FPGA gateware\n");
+  fprintf(stderr, "                   use the 'force' option at your own risk: this might brick your device\n");
   fprintf(stderr, "  -h               display this help and exit\n");
   fprintf(stderr, "\n");
   fprintf(stderr, "  wddisable        disables the watchdog (preventing automated FPGA reset permanently)\n");
@@ -104,12 +106,13 @@ int main(int argc, char** argv) {
 
   const char* devName;
   const char* command;
-  int         cmdExecuted=0;
+  int         cmdExecuted     = 0;
 
-  int         getEBVersion=0;
-  int         probeAfterReset=0;
-  int         waitTime=1;
-  int         exitCode=0;
+  int         getEBVersion    = 0;
+  int         flagForce       = 0;
+  int         probeAfterReset = 0;
+  int         waitTime        = 1;
+  int         exitCode        = 0;
   uint32_t    nCPU;
   uint64_t    i;
 
@@ -121,29 +124,32 @@ int main(int argc, char** argv) {
 
   program = argv[0];
 
-  while ((opt = getopt(argc, argv, "p:eh")) != -1) {
+  while ((opt = getopt(argc, argv, "p:feh")) != -1) {
     switch (opt) {
-    case 'p' :
-      probeAfterReset=1;
-      waitTime = strtol(optarg, &tail, 0);
-      if (*tail != 0) {
-        fprintf(stderr, "Specify a proper number, not '%s'!\n", optarg);
-        exit(1);
-      } // if *tail
-      break;
-    case 'e':
-      getEBVersion=1;
-      break;
-    case 'h':
-      help();
-      return 0;
+      case 'p' :
+        probeAfterReset=1;
+        waitTime = strtol(optarg, &tail, 0);
+        if (*tail != 0) {
+          fprintf(stderr, "Specify a proper number, not '%s'!\n", optarg);
+          exit(1);
+        } // if *tail
+        break;
+      case 'e':
+        getEBVersion = 1;
+        break;
+      case 'f':
+        flagForce = 1;
+        break;
+      case 'h':
+        help();
+        return 0;
       case ':':
       case '?':
         error = 1;
-      break;
-    default:
-      fprintf(stderr, "%s: bad getopt result\n", program);
-      return 1;
+        break;
+      default:
+        fprintf(stderr, "%s: bad getopt result\n", program);
+        return 1;
     } // switch opt
   } // while opt
 
@@ -186,8 +192,8 @@ int main(int argc, char** argv) {
       cmdExecuted = 1;
 
       // depending on the device, the etherbone cycle either completes or times out
-      status = wb_wr_reset(device, devIndex, 0xdeadbeef);
-      if ((status != EB_TIMEOUT) && (status != EB_OK)) die("RESET FPGA", status);
+      status = wb_wr_reset(device, devIndex, 0xdeadbeef, flagForce);
+      if ((status != EB_TIMEOUT) && (status != EB_OK) && (status != EB_ABI)) die("RESET FPGA", status);
 
       if (probeAfterReset) {
         //close, wait and reopen socket, try to read a property (here: ip) from the device

diff --git a/tools/wb_api.c b/tools/wb_api.c
@@ -3,7 +3,7 @@
 //
 //  created : Apr 10, 2013
 //  author  : Dietrich Beck, GSI-Darmstadt
-//  version : 22-Jun-2023
+//  version : 24-Jul-2024
 //
 // Api for wishbone devices for timing receiver nodes. This is not a timing receiver API,
 // but only a temporary solution.
@@ -833,7 +833,7 @@ eb_status_t wb_1wire_get_temp(eb_device_t device, int devIndex, unsigned int bus
 } // wb_1wire_get_temp
 
 
-eb_status_t wb_wr_reset(eb_device_t device, int devIndex, uint32_t value)
+eb_status_t wb_wr_reset(eb_device_t device, int devIndex, uint32_t value, int flagForce)
 {
   eb_data_t    data;
   eb_address_t address;
@@ -844,7 +844,9 @@ eb_status_t wb_wr_reset(eb_device_t device, int devIndex, uint32_t value)
   return EB_OK;
 #endif
 
-  if ((status = wb_check_device(device, FPGA_RESET_VENDOR, FPGA_RESET_PRODUCT, FPGA_RESET_VMAJOR, FPGA_RESET_VMINOR, devIndex, &reset_addr)) != EB_OK) return status;
+  status = wb_check_device(device, FPGA_RESET_VENDOR, FPGA_RESET_PRODUCT, FPGA_RESET_VMAJOR, FPGA_RESET_VMINOR, devIndex, &reset_addr);
+  if ((status != EB_OK)  && (status != EB_ABI)) return status;
+  if ((status == EB_ABI) && !flagForce)         return status;
 
   address = reset_addr + FPGA_RESET_RESET;
   data    = (eb_data_t)value;

diff --git a/tools/wb_api.h b/tools/wb_api.h
@@ -11,7 +11,7 @@
 //            -- Tomasz Wlostowski <[email protected]>
 //  version : 21-Jun-2023
 //
-#define WB_API_VERSION "0.16.0"
+#define WB_API_VERSION "0.17.0"
 //
 // Api for wishbone devices for timing receiver nodes. This is not a timing receiver API.
 //
@@ -211,7 +211,8 @@ eb_status_t wb_1wire_get_temp(eb_device_t device,              // EB device
 // reset the FPGA, reload new image from flash
 eb_status_t wb_wr_reset(eb_device_t device,                    // EB device
                         int devIndex,                          // 0,1,2... - there may be more than 1 device on the WB bus
-                        uint32_t value                         // value to be written to the reset controller
+                        uint32_t value,                        // value to be written to the reset controller
+                        int flagForce                          // 1: force reset even with incompatible gateware; 0: don't force reset
                         );
 
 // disable or enable the watchdog for automated FPGA reset