Skip to content

Commit

Permalink
Merge pull request #368 from GSI-CS-CO/feature_BLM_ACO
Browse files Browse the repository at this point in the history
Feature blm aco
  • Loading branch information
stefanrauch authored Jul 22, 2024
2 parents e902eac + 00cf0bb commit 805123e
Show file tree
Hide file tree
Showing 25 changed files with 5,089 additions and 139 deletions.
18 changes: 18 additions & 0 deletions syn/blm_aco/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
TARGET = blm_aco
DEVICE = EP2AGX125
FLASH = EPCS128
RAM_SIZE = 32768
PHK = ../../modules/scu_bus/housekeeping_sw
PBLM = ../../top/blm_aco
W1 = ../../ip_cores/wrpc-sw
CFLAGS = -I$(PHK)/include -I$(PBLM)
USRCPUCLK = 125000

include ../build.mk

$(TARGET).mif: housekeeping.mif

housekeeping.elf: $(PHK)/main.c $(W1)/dev/w1.c $(W1)/dev/w1-temp.c $(W1)/dev/w1-hw.c

clean::
rm -f $(POW)/*.o $(PHK)/main.o $(W1)/dev/*.o
19 changes: 19 additions & 0 deletions syn/blm_aco/Manifest.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
target = "altera"
action = "synthesis"

fetchto = "../../ip_cores"

syn_device = "ep2agx125df"
syn_grade = "c5"
syn_package = "25"
syn_top = "blm_aco"
syn_project = "blm_aco"

quartus_preflow = "blm_aco.tcl"

modules = {
"local" : [
"../../top/blm_aco/",
]
}
syn_tool = "quartus"
30 changes: 30 additions & 0 deletions syn/blm_aco/blm_aco.qpf
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
# Date created = 14:31:14 February 16, 2023
#
# -------------------------------------------------------------------------- #

QUARTUS_VERSION = "18.1"
DATE = "14:31:14 February 16, 2023"

# Revisions

PROJECT_REVISION = "blm_aco"
Loading

0 comments on commit 805123e

Please sign in to comment.