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Feature blm aco #373

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Feature blm aco #373

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27dd3bb
BLM: added the control through event cycles, the readout of all the c…
ruantea Jul 31, 2024
48d36b5
BLM qsf file
ruantea Jul 31, 2024
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10 changes: 9 additions & 1 deletion syn/blm_aco/blm_aco.qsf
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Original file line number Diff line number Diff line change
Expand Up @@ -234,6 +234,9 @@









Expand Down Expand Up @@ -740,9 +743,13 @@ set_global_assignment -name VHDL_FILE ../../modules/daq/daq.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/daq/Zeitbasis_daq.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper_pkg.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/ddr3/ddr3_wrapper.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/diob/del_quench_detection.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/diob/hw_interlock.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/diob/QuD_masken_reg.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/diob/qud_pkg.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/diob/quench_detection.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/diob/spill_abort.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/diob/TM_quench_detection.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto_pkg.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag_auto.vhd -library work
set_global_assignment -name VHDL_FILE ../../modules/dm_diag/dm_diag.vhd -library work
Expand Down Expand Up @@ -918,7 +925,7 @@ set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_ctrl.vhd -libra
set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_puls_n.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/atr_timeout.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/aw_io_reg.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/Beam_Loss_check_v1.2.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/Beam_Loss_check_v2.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_24_9_9_9pll.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/blm_aco_v1.0.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_cnt_pulse_former.vhd -library work
Expand All @@ -932,6 +939,7 @@ set_global_assignment -name VHDL_FILE ../../top/blm_aco/BLM_watchdog_v1.0.vhd -l
set_global_assignment -name VHDL_FILE ../../top/blm_aco/config_status.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_debounce.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/diob_sync.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/event_ctrl_el.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/fg901040.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/flanke.vhd -library work
set_global_assignment -name VHDL_FILE ../../top/blm_aco/front_board_id_v0.vhd -library work
Expand Down
6 changes: 3 additions & 3 deletions top/blm_aco/BLM_counter_pool_el.vhd
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Expand Up @@ -5,7 +5,7 @@ use work.scu_diob_pkg.all;

entity BLM_counter_pool_el is
generic (
WIDTH : integer := 30 -- Counter width
WIDTH : integer := 32 -- Counter width

);
port (
Expand Down Expand Up @@ -45,7 +45,7 @@ signal cnt_up, cnt_down: std_logic;
component up_down_counter is
generic (

WIDTH : integer := 30 -- Counter width
WIDTH : integer := 32 -- Counter width

);
port (
Expand Down Expand Up @@ -122,7 +122,7 @@ end process;
Counter_module: up_down_counter
generic map
(
WIDTH => 30 --WIDTH -- Counter width
WIDTH => 32 --WIDTH -- Counter width

)
port map
Expand Down
42 changes: 4 additions & 38 deletions top/blm_aco/BLM_out_el_m_v1.0.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ port (
gate_in : in std_logic_vector(11 downto 0); -- to be sent to the status registers
gate_error : in std_logic_vector(11 downto 0); -- to be sent to the status registers
gate_out : in std_logic_vector (11 downto 0); --gate error
counter_reg: in t_BLM_counter_Array;
-- counter_reg: in t_BLM_counter_Array;
gate_state: in std_logic_vector(47 downto 0);
led_id_state : in std_logic_vector(3 downto 0);
BLM_Output : out std_logic_vector(5 downto 0);
Expand Down Expand Up @@ -131,41 +131,7 @@ begin
end process;


----------------------------------------------------------------------------------------
out_counter_buffer_proc: process (clk, nRST)
begin
if not nRST='1' then
for i in 0 to 127 loop
up_down_counter_val(i) <= (others =>'0');
end loop;

out_cnt_wr <='0';

elsif (clk'EVENT AND clk= '1') then

out_cnt_wr<= BLM_out_sel_reg(126)(15);



if out_cnt_wr='1' then

for i in 0 to 127 loop
up_down_counter_val(i) <= counter_reg(i);

end loop;
end if;

end if;
end process;

status_reg_counter_value_process: process (up_down_counter_val, BLM_out_sel_reg(121))
begin

read_counters <= to_integer(unsigned(BLM_out_sel_Reg(126)(6 downto 0)));
cnt_readback <= up_down_counter_val(read_counters);


end process;
------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
----- BLM_STATUS_REGISTERS
--------------------------------------------------------------------------------------------------
Expand All @@ -181,8 +147,8 @@ end process;
BLM_status_reg(18) <= wd_output(31 downto 16);
BLM_status_reg(19) <= wd_output(47 downto 32);
BLM_status_reg(20) <= "0000000000" & wd_output(53 downto 48);
BLM_status_reg(21) <= cnt_readback(15 downto 0);
BLM_status_reg(22) <= cnt_readback(29) & cnt_readback(29) & cnt_readback(29 downto 16);
BLM_status_reg(21) <=(others =>'0');
BLM_status_reg(22) <=(others =>'0');
BLM_status_reg(23) <= "0000" & gate_input;
BLM_status_reg(24) <= "0000" & gate_output;
BLM_status_reg(25) <= "0000000000" & BLM_out_signal;
Expand Down
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