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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,41 @@ | ||
| package hajime.vectorOoO | ||
|
|
||
| import chisel3._ | ||
| import circt.stage.ChiselStage | ||
| import chisel3.util._ | ||
| import hajime.common.BundleInitializer._ | ||
| import hajime.common._ | ||
| import hajime.simple4Stage._ | ||
| import hajime.vectormodules.VectorDecoderResp | ||
|
|
||
| class DispatcherDataSignals(implicit params: HajimeCoreParams) extends Bundle { | ||
| import params._ | ||
| val pc = new ProgramCounter() | ||
| val renamedRs1 = Valid(UInt(physicalRegWidth.W)) | ||
| val renamedRs2 = Valid(UInt(physicalRegWidth.W)) | ||
| val renamedRd = Valid(UInt(physicalRegWidth.W)) | ||
| // jalr: immVal1 -> inst[31,20], immVal2 -> pc from RAS | ||
| // csr: immVal1 -> inst[31,20] (csr addr), immVal2 -> inst[4:0] | ||
| // vsetvli: immVal1 -> inst[30,20] | ||
| // vsetivli: immVal1 -> inst[29,20], immVal2 -> inst[4:0] | ||
| // vop.vi: immVal2 -> inst[4:0] | ||
| val immVal1 = UInt(xprlen.W) | ||
| val immVal2 = UInt(xprlen.W) | ||
| } | ||
| class DispatcherOutput(implicit params: HajimeCoreParams) extends Bundle { | ||
| val dataSignals = new DispatcherDataSignals() | ||
| val ctrlSignals = new BasicCtrlSignals() | ||
| val exceptionSignals = new Valid(UInt(params.xprlen.W)) | ||
| val vectorCtrlSignals = if(params.useVector) Some(new VectorDecoderResp()) else None | ||
| val debug = if(params.debug) Some(new Debug_Info()) else None | ||
| } | ||
|
|
||
| class DispatcherIO(implicit params: HajimeCoreParams) extends Module { | ||
| val frontend = Flipped(new FrontEndCpuIO()) | ||
| val hartid = Input(UInt(params.xprlen.W)) | ||
| val toExecutor = new DecoupledIO(new DispatcherOutput()) | ||
| } | ||
|
|
||
| class Dispatcher(implicit params: HajimeCoreParams) extends Module { | ||
|
|
||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,27 +1,48 @@ | ||
| package hajime.vectorOoO | ||
|
|
||
| import circt.stage.ChiselStage | ||
| import chisel3._ | ||
| import circt.stage.ChiselStage | ||
| import chisel3.util._ | ||
| import hajime.axiIO.AXI4liteIO | ||
| import hajime.common.BundleInitializer._ | ||
| import hajime.common._ | ||
| import hajime.simple4Stage._ | ||
| import hajime.common.BundleInitializer._ | ||
|
|
||
| class FrontEndForOoO(implicit params: HajimeCoreParams) extends Module { | ||
| val io = IO(new FrontEndIO()) | ||
| io := DontCare | ||
|
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||
| val pc_reg = RegInit(Valid(new ProgramCounter()).Init( | ||
| _.valid -> true.B, | ||
| _.valid -> false.B, | ||
| _.bits.addr -> io.reset_vector, | ||
| )) | ||
| val toAxiAR = MuxCase(pc_reg.bits.nextPC, Seq( | ||
| io.cpu.req.valid -> io.cpu.req.bits.addr, | ||
| // axiがreadyでなければPCを維持 | ||
| (!io.icache_axi4lite.ar.ready || !io.icache_axi4lite.r.valid || !io.cpu.resp.ready) -> pc_reg.bits.addr | ||
| )) | ||
| // cpuがFrontEndから命令を読み取ればaddr | ||
| when(io.cpu.resp.valid && io.cpu.resp.ready) { | ||
| pc_reg := io.cpu.req.bits | ||
| // PCの更新はCPUが行う | ||
| when(io.cpu.req.valid) { | ||
| pc_reg := io.cpu.req | ||
| } | ||
| .otherwise { | ||
| pc_reg.valid := false.B | ||
| } | ||
|
|
||
| io.icache_axi4lite.ar.bits.addr := Mux(io.cpu.req.valid, io.cpu.req.bits.addr, pc_reg.bits.addr) | ||
| io.icache_axi4lite.ar.bits.prot := 0.U | ||
| io.icache_axi4lite.ar.valid := io.cpu.req.valid || pc_reg.valid | ||
|
|
||
| io.cpu.resp.bits.pc := pc_reg.bits | ||
| io.cpu.resp.bits.inst.bits := io.icache_axi4lite.r.bits.data | ||
| io.cpu.resp.valid := io.icache_axi4lite.r.valid | ||
| io.icache_axi4lite.r.ready := io.cpu.resp.ready | ||
|
|
||
| val instAccessFault = pc_reg.bits.addr > 0x1FFC.U | ||
| val instAddressMisaligned = pc_reg.bits.addr(1, 0) =/= 0.U | ||
| io.cpu.resp.bits.exceptionSignals.bits := MuxCase(0.U, Seq( | ||
| instAccessFault -> Causes.fetch_access.U, | ||
| instAddressMisaligned -> Causes.misaligned_fetch.U, | ||
| )) | ||
| io.cpu.resp.bits.exceptionSignals.valid := instAccessFault || instAddressMisaligned | ||
| } | ||
|
|
||
| object FrontEndForOoO extends App { | ||
| implicit val params: HajimeCoreParams = HajimeCoreParams() | ||
| def apply(implicit params: HajimeCoreParams): FrontEndForOoO = new FrontEndForOoO() | ||
| ChiselStage.emitSystemVerilogFile(new FrontEndForOoO(), firtoolOpts = COMPILE_CONSTANTS.FIRTOOLOPS) | ||
| } |
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