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HidetaroTanaka committed Jan 30, 2024
1 parent e7e3b63 commit 2675df0
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Showing 2 changed files with 9 additions and 9 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@ import chiseltest._
import org.scalatest.flatspec._
import hajime.vectormodules.MemInitializer._

object Core_ApplicationTest {
def get_toHostChar[T <: CpuModule](dut: CoreAndCache[T]): Char = {
object CoreApplicationTest {
def getToHostChar[T <: CpuModule](dut: CoreAndCache[T]): Char = {
dut.io.toHost.bits.peekInt().toChar
}

def get_toHostValid[T <: CpuModule](dut: CoreAndCache[T]): Boolean = {
def getToHostValid[T <: CpuModule](dut: CoreAndCache[T]): Boolean = {
dut.io.toHost.valid.peekBoolean()
}

Expand All @@ -26,11 +26,11 @@ object Core_ApplicationTest {
dut.io.hartid.poke(0.U)

var toHostWrittenChar: List[Char] = Nil
while (!(get_toHostValid(dut) && (get_toHostChar(dut) == '\u0000'))) {
while (!(getToHostValid(dut) && (getToHostChar(dut) == '\u0000'))) {
dut.clock.step()
if (get_toHostValid(dut)) {
// print(get_toHostChar())
toHostWrittenChar = toHostWrittenChar :+ get_toHostChar(dut)
if (getToHostValid(dut)) {
// print(getToHostChar())
toHostWrittenChar = toHostWrittenChar :+ getToHostChar(dut)
}
}
dut.io.debugIO.debugAbiMap.a0.expect(0.U(64.W))
Expand All @@ -39,7 +39,7 @@ object Core_ApplicationTest {
}
}

import Core_ApplicationTest._
import CoreApplicationTest._

class Rv64iApplicationTest extends AnyFlatSpec with ChiselScalatestTester {
val rv64iTestList = Seq(
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2 changes: 1 addition & 1 deletion src/test/scala/hajime/vectormodules/VectorCpuSpec.scala
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package hajime.vectormodules

import chisel3._
import chiseltest._
import hajime.simple4Stage.Core_ApplicationTest._
import hajime.simple4Stage.CoreApplicationTest._
import hajime.vectormodules.MemInitializer._
import hajime.simple4Stage._
import org.scalatest.flatspec._
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