And the refactoring is going again 2

HidetaroTanaka · Jan 29, 2024 · 528cf43 · 528cf43
1 parent b0acf72
commit 528cf43
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Showing 4 changed files with 10 additions and 10 deletions.
diff --git a/src/test/scala/hajime/simple4Stage/CoreAndCache.scala b/src/test/scala/hajime/simple4Stage/CoreAndCache.scala
@@ -18,7 +18,7 @@ class CoreAndCache[T <: CpuModule](iCacheMemsize: Int = 8192, dCacheMemsize: Int
     val iCacheInitialising = Input(Bool())
     val dCacheInitialising = Input(Bool())
     val iMemInitialiseAxi = Flipped(new AXI4liteIO(addrWidth = 64, dataWidth = 32))
-    val dmem_initialiseAXI = Flipped(new AXI4liteIO(addrWidth = 64, dataWidth = 64))
+    val dMemInitialiseAxi = Flipped(new AXI4liteIO(addrWidth = 64, dataWidth = 64))
   })
 
   val core = withReset(io.iCacheInitialising || io.dCacheInitialising || reset.asBool) {
@@ -31,7 +31,7 @@ class CoreAndCache[T <: CpuModule](iCacheMemsize: Int = 8192, dCacheMemsize: Int
   io.iMemInitialiseAxi := DontCare
   core.io.iCacheAxi4Lite := DontCare
   dcache.io := DontCare
-  io.dmem_initialiseAXI := DontCare
+  io.dMemInitialiseAxi := DontCare
   core.io.dCacheAxi4Lite := DontCare
 
   when(io.iCacheInitialising) {
@@ -47,15 +47,15 @@ class CoreAndCache[T <: CpuModule](iCacheMemsize: Int = 8192, dCacheMemsize: Int
   }
 
   when(io.dCacheInitialising) {
-    dcache.io <> io.dmem_initialiseAXI
+    dcache.io <> io.dMemInitialiseAxi
     core.io.dCacheAxi4Lite.ar.ready := false.B
     core.io.dCacheAxi4Lite.aw.ready := false.B
     core.io.dCacheAxi4Lite.w.ready := false.B
   } .otherwise {
     dcache.io <> core.io.dCacheAxi4Lite
-    io.dmem_initialiseAXI.ar.ready := false.B
-    io.dmem_initialiseAXI.aw.ready := false.B
-    io.dmem_initialiseAXI.w.ready := false.B
+    io.dMemInitialiseAxi.ar.ready := false.B
+    io.dMemInitialiseAxi.aw.ready := false.B
+    io.dMemInitialiseAxi.w.ready := false.B
   }
 
   core.io.resetVector := io.resetVector

diff --git a/src/test/scala/hajime/simple4Stage/CoreTest.scala b/src/test/scala/hajime/simple4Stage/CoreTest.scala
@@ -14,7 +14,7 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
   }
 
   def initialiseDmem[T <: CpuModule](filename: String, dut: CoreAndCache[T]): Unit = {
-    hajime.vectormodules.MemInitializer.initialiseMemWithAxi(filename, dut.io.dmem_initialiseAXI, dut.io.dCacheInitialising, dut.clock, 0x4000)
+    hajime.vectormodules.MemInitializer.initialiseMemWithAxi(filename, dut.io.dMemInitialiseAxi, dut.io.dCacheInitialising, dut.clock, 0x4000)
   }
 
   val instList_noDmem = Seq(

diff --git a/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala b/src/test/scala/hajime/simple4Stage/Core_ApplicationTest.scala
@@ -19,7 +19,7 @@ object Core_ApplicationTest {
     fork {
       initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_inst.hex", dut.io.iMemInitialiseAxi, dut.io.iCacheInitialising, dut.clock, 0)
     }.fork {
-      initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_data.hex", dut.io.dmem_initialiseAXI, dut.io.dCacheInitialising, dut.clock, 0x4000)
+      initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_data.hex", dut.io.dMemInitialiseAxi, dut.io.dCacheInitialising, dut.clock, 0x4000)
     }.join()
     dut.clock.setTimeout(1048576)
     dut.io.resetVector.poke(0.U)

diff --git a/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala b/src/test/scala/hajime/vectormodules/VectorCpuSpec.scala
@@ -65,7 +65,7 @@ class VectorCpuSpec extends AnyFlatSpec with ChiselScalatestTester {
         }.fork {
           initialiseMemWithAxi(
             filename = s"src/main/resources/rv64ui/${e}_data.hex",
-            axi = dut.io.dmem_initialiseAXI,
+            axi = dut.io.dMemInitialiseAxi,
             initialising = dut.io.dCacheInitialising,
             clock = dut.clock,
             baseAddr = 0x4000
@@ -162,7 +162,7 @@ class FpgaTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester {
     fork {
       initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_inst.mem", dut.io.iMemInitialiseAxi, dut.io.iCacheInitialising, dut.clock, 0)
     }.fork {
-      initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_data.mem", dut.io.dmem_initialiseAXI, dut.io.dCacheInitialising, dut.clock, 0x4000)
+      initialiseMemWithAxi(s"src/main/resources/applications_${testType}/${testName}_data.mem", dut.io.dMemInitialiseAxi, dut.io.dCacheInitialising, dut.clock, 0x4000)
     }.join()
     dut.clock.setTimeout(0)
     dut.io.resetVector.poke(0.U)