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HidetaroTanaka · Dec 1, 2023 · 5a4e4f5 · 5a4e4f5
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Showing 23 changed files with 3,741 additions and 10 deletions.
diff --git a/fpga/fpga.v b/fpga/fpga.v
@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 12/01/2023 04:05:10 PM
+// Design Name:
+// Module Name: fpga
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module fpga(
+    input clk_in1_0,
+    input RST_0,
+    output [6:0] SEG_0,
+	output [7:0] AN_0
+    );
+    wire [31:0] check;
+    wire CLK_top;
+
+    design_1_wrapper clk_wiz(
+        .clk_in1_0(clk_in1_0),
+        .clk_out1_0(CLK_top)
+    );
+
+    top top(
+        .CLK(CLK_top),
+        .RST(RST_0),
+        .tohost(check)
+    );
+    SEG_PUT seg_put(
+        .CLK(clk_in1_0),
+        .reset(RST_0),
+        .check(check),
+        .SEG(SEG_0),
+        .AN(AN_0)
+    );
+endmodule
diff --git a/fpga/sim.v b/fpga/sim.v
@@ -36,7 +36,7 @@ module sim();
 
     #256 RST = 0;
     #256 RST = 1;
-    #1024 $finish;
+    #1048576 $finish;
   end
 
   always begin

diff --git a/fpga/top.v b/fpga/top.v
@@ -32,7 +32,7 @@ module top(
     wire io_icache_axi4lite_r_valid;
     wire [31:0] io_icache_axi4lite_r_bits_data;
     wire [2:0] io_icache_axi4lite_r_bits_resp;
-    wire io_icache_axi4lite_w_ready;
+    // wire io_icache_axi4lite_w_ready;
     wire io_dcache_axi4lite_ar_ready;
     wire io_dcache_axi4lite_aw_ready;
     wire io_dcache_axi4lite_b_valid;
@@ -41,8 +41,8 @@ module top(
     wire  [63:0] io_dcache_axi4lite_r_bits_data;
     wire  [2:0]  io_dcache_axi4lite_r_bits_resp;
     wire         io_dcache_axi4lite_w_ready;
-    wire  [63:0] io_reset_vector;
-    wire io_hartid;
+    // wire  [63:0] io_reset_vector;
+    // wire io_hartid;
     wire        io_icache_axi4lite_ar_valid;
     wire [63:0] io_icache_axi4lite_ar_bits_addr;
     wire [2:0]  io_icache_axi4lite_ar_bits_prot;
@@ -78,7 +78,7 @@ module top(
       .io_icache_axi4lite_r_valid(io_icache_axi4lite_r_valid),
       .io_icache_axi4lite_r_bits_data(io_icache_axi4lite_r_bits_data),
       .io_icache_axi4lite_r_bits_resp(io_icache_axi4lite_r_bits_resp),
-      .io_icache_axi4lite_w_ready(io_icache_axi4lite_w_ready),
+      .io_icache_axi4lite_w_ready(),
       .io_dcache_axi4lite_ar_ready(io_dcache_axi4lite_ar_ready),
       .io_dcache_axi4lite_aw_ready(io_dcache_axi4lite_aw_ready),
       .io_dcache_axi4lite_b_valid(io_dcache_axi4lite_b_valid),

diff --git a/fpga/vector_matmul_data.mem b/fpga/vector_matmul_data.mem
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