some Register Initialisations

HidetaroTanaka · Nov 29, 2023 · 6222eb7 · 6222eb7
1 parent a0542bd
commit 6222eb7
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Showing 4 changed files with 10 additions and 4 deletions.
diff --git a/src/main/scala/hajime/common/HajimeCoreParams.scala b/src/main/scala/hajime/common/HajimeCoreParams.scala
@@ -32,6 +32,7 @@ case class HajimeCoreParams(
   useVector: Boolean = true,
   usePackedSIMD: Boolean = false,
   debug: Boolean = true,
+  fpga: Boolean = false,
   vlen: Int = 256,
   vecAluExecUnitNum: Int = 2,
 ) {

diff --git a/src/main/scala/hajime/simple4Stage/Core.scala b/src/main/scala/hajime/simple4Stage/Core.scala
@@ -47,7 +47,7 @@ class Core[T <: CpuModule](cpu: Class[T])(implicit params: HajimeCoreParams) ext
 }
 
 object Core extends App {
-  implicit val params = HajimeCoreParams()
+  implicit val params = HajimeCoreParams(useException = false, useVector = true, debug = false)
   def apply[T <: CpuModule](cpu: Class[T])(implicit params: HajimeCoreParams): Core[T] = {
     if(cpu == classOf[VectorCpu] && !params.useVector) {
       throw new Exception("useVector is false")

diff --git a/src/main/scala/hajime/vectormodules/VectorCpu.scala b/src/main/scala/hajime/vectormodules/VectorCpu.scala
@@ -62,8 +62,12 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar
 
   val decoded_inst = Wire(new InstBundle())
   decoded_inst := io.frontend.resp.bits.inst
-  val ID_EX_REG = Reg(Valid(new ID_EX_IO()))
-  val EX_WB_REG = Reg(Valid(new EX_WB_IO()))
+  val ID_EX_REG = RegInit(Valid(new ID_EX_IO()).Lit(
+    _.valid -> false.B,
+  ))
+  val EX_WB_REG = RegInit(Valid(new EX_WB_IO()).Lit(
+    _.valid -> false.B,
+  ))
 
   // これらがtrueならばベクトル命令を発行できる
   val vs1NonRequiredOrReady = !vrfReadyTable.io.vs1Check.valid || vrfReadyTable.io.vs1Check.ready

diff --git a/src/test/scala/hajime/publicmodules/Dcache_for_Verilator.scala b/src/test/scala/hajime/publicmodules/Dcache_for_Verilator.scala
@@ -11,6 +11,7 @@ import org.scalatest.flatspec._
 import scala.io._
 
 // 命令キャッシュと異なりマスター側のreadyが下がることは無いので，出力のストールは考えない
+// TODO: FPGA用に例えばledへの出力を追加する，正常終了フラグや例外終了フラグなど
 class Dcache_for_Verilator(dcacheBaseAddr: Int, tohost: Int, memsize: Int = 0x2000) extends Module with ChecksAxiReadResp with ChecksAxiWriteResp{
   require(memsize % 8 == 0, s"memsize $memsize is not multiple of 8")
 
@@ -79,5 +80,5 @@ class Dcache_for_Verilator(dcacheBaseAddr: Int, tohost: Int, memsize: Int = 0x20
 
 object Dcache_for_Verilator extends App {
   def apply(dcacheBaseAddr: Int = 0x00004000, tohost: Int = 0x10000000, memsize: Int = 0x2000): Dcache_for_Verilator = new Dcache_for_Verilator(dcacheBaseAddr, tohost, memsize)
-  ChiselStage.emitSystemVerilogFile(Dcache_for_Verilator(), firtoolOpts = COMPILE_CONSTANTS.FIRTOOLOPS)
+  ChiselStage.emitSystemVerilogFile(Dcache_for_Verilator(dcacheBaseAddr = 0x00004000, tohost = 0x10000000, memsize = 8192), firtoolOpts = COMPILE_CONSTANTS.FIRTOOLOPS)
 }