My last commie errored in Scalar helloworld test, but that was becaus…

…e VectorCpuSpec hllowworld used same directory. btw vector memtest somehow works for these unit-strides

src/main/scala/hajime/vectormodules/VectorCpu.scala

@@ -187,24 +187,24 @@ class VectorCpu(implicit params: HajimeCoreParams) extends CpuModule with Scalar
   vectorDecoder.io.inst := decoded_inst
 
   // ベクトル命令がベクトル設定・メモリアクセスでなく，かつvvならばvs1を使用する
-  vrfReadyTable.io.vs1Check.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !(vectorDecoder.io.out.avl_sel === AVL_SEL.NONE.asUInt) && vectorDecoder.io.out.mop === MOP.NONE.asUInt && (vectorDecoder.io.out.vSource === VSOURCE.VV.asUInt)
+  vrfReadyTable.io.vs1Check.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !vectorDecoder.io.out.isConfsetInst && vectorDecoder.io.out.mop === MOP.NONE.asUInt && (vectorDecoder.io.out.vSource === VSOURCE.VV.asUInt)
   vrfReadyTable.io.vs1Check.bits.idx := decoded_inst.rs1
   vrfReadyTable.io.vs1Check.bits.vtype := vtypeBypass
   vrfReadyTable.io.vs1Check.bits.vm := vectorDecoder.io.out.veuFun.isMaskInst
   // ベクトル設定命令でなく，かつメモリアクセスでないまたはインデックスならばvs2を使用する
-  vrfReadyTable.io.vs2Check.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !(vectorDecoder.io.out.avl_sel === AVL_SEL.NONE.asUInt) && ((vectorDecoder.io.out.mop === MOP.NONE.asUInt) || (vectorDecoder.io.out.mop === MOP.IDX_ORDERED.asUInt))
+  vrfReadyTable.io.vs2Check.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !vectorDecoder.io.out.isConfsetInst && ((vectorDecoder.io.out.mop === MOP.NONE.asUInt) || (vectorDecoder.io.out.mop === MOP.IDX_ORDERED.asUInt))
   vrfReadyTable.io.vs2Check.bits.idx := decoded_inst.rs2
   vrfReadyTable.io.vs2Check.bits.vtype := vtypeBypass
   vrfReadyTable.io.vs2Check.bits.vm := vectorDecoder.io.out.veuFun.isMaskInst
   // ベクトル設定命令でないならばvdを使用する
-  vrfReadyTable.io.vdCheck.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !(vectorDecoder.io.out.avl_sel === AVL_SEL.NONE.asUInt)
+  vrfReadyTable.io.vdCheck.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !vectorDecoder.io.out.isConfsetInst
   vrfReadyTable.io.vdCheck.bits.idx := decoded_inst.rd
   vrfReadyTable.io.vdCheck.bits.vtype := vtypeBypass
   vrfReadyTable.io.vdCheck.bits.vm := vectorDecoder.io.out.veuFun.writeAsMask
   // vmフィールドが1ならばvmを使用する
-  vrfReadyTable.io.vmCheck.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !(vectorDecoder.io.out.avl_sel === AVL_SEL.NONE.asUInt) && !vectorDecoder.io.out.vm
+  vrfReadyTable.io.vmCheck.valid := decoder.io.out.valid && decoder.io.out.bits.vector.get && !vectorDecoder.io.out.isConfsetInst && !vectorDecoder.io.out.vm
   // ベクトル設定命令でなく，かつストア命令で無ければvdへ書き込む
-  vrfReadyTable.io.invalidateVd := io.frontend.resp.valid && io.frontend.resp.ready && decoder.io.out.valid && decoder.io.out.bits.vector.get && (vectorDecoder.io.out.avl_sel =/= AVL_SEL.NONE.asUInt) && !decoder.io.out.bits.memWrite
+  vrfReadyTable.io.invalidateVd := io.frontend.resp.valid && io.frontend.resp.ready && decoder.io.out.valid && decoder.io.out.bits.vector.get && !vectorDecoder.io.out.isConfsetInst && !decoder.io.out.bits.memWrite
 
   // vecAluExecUnitを使用するなら，空いている方をvalidにする
   when(ID_flush) {

src/test/scala/hajime/vectormodules/VectorCpuSpec.scala

@@ -49,7 +49,7 @@ class VectorCpuSpec extends AnyFlatSpec with ChiselScalatestTester {
     "sb", "sd", "sh", "sw"
   ) else Nil
   for (e <- instListWithDmem) {
-    it should s"pass the test ${e}" in {
+    it should s"Vector CPU pass the test ${e}" in {
       test(new Core_and_cache(icache_memsize = 8192, dcache_memsize = 8192, tohost = 0x10000000, useVector = true, cpu = classOf[VectorCpu])).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
         dut.clock.setTimeout(1024)
         dut.io.reset_vector.poke(0.U)
@@ -85,7 +85,7 @@ class VectorCpuSpec extends AnyFlatSpec with ChiselScalatestTester {
     "mul", "mulh", "mulhsu", "mulhu", "mulw"
   ) else Nil
   for (e <- instListMult) {
-    it should s"pass the test ${e}" in {
+    it should s"Vector CPU pass the test ${e}" in {
       test(new Core_and_cache(icache_memsize = 8192, dcache_memsize = 8192, tohost = 0x10000000, useVector = true, cpu = classOf[VectorCpu])).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
         dut.clock.setTimeout(1024)
         dut.io.reset_vector.poke(0.U)
@@ -115,7 +115,7 @@ class Rv64imAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester {
     "helloworld", "median", "printInt64", "selection_sort", "memcpy", "quicksort"
   )
   for (e <- rv64iTestList) {
-    it should s"execute $e" in {
+    it should s"Vector CPU execute $e" in {
       test(new Core_and_cache(useVector = true, cpu = classOf[VectorCpu])).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
         executeTest(dut, e, "rv64i")
       }
@@ -125,10 +125,23 @@ class Rv64imAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester {
     "factorial", "power", "vector_innerproduct"
   )
   for (e <- rv64mTestList) {
-    it should s"execute $e" in {
+    it should s"Vector CPU execute $e" in {
       test(new Core_and_cache(useVector = true, cpu = classOf[VectorCpu])).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
         executeTest(dut, e, "rv64m")
       }
     }
   }
+}
+
+class Zve64xAppTestForVecCpu extends AnyFlatSpec with ChiselScalatestTester {
+  val zve64xTestList = Seq(
+    "vector_conf", "vector_ldst", "vector_memcpy"
+  )
+  for (e <- zve64xTestList) {
+    it should s"Vector CPU execute $e" in {
+      test(new Core_and_cache(useVector = true, cpu = classOf[VectorCpu])).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+        executeTest(dut, e, "vector")
+      }
+    }
+  }
 }