Merge branch 'vectorOoO' into pushToVectorOoO

src/main/scala/hajime/common/BundleInitializer.scala

@@ -0,0 +1,15 @@
+package hajime.common
+
+import chisel3._
+import chisel3.experimental._
+object BundleInitializer {
+  implicit class AddBundleInitializerConstructor[T <: Record](x: T) {
+    def Init(elems: (T => (Data, Data))*)(implicit sourceInfo: SourceInfo): T = {
+      val w = Wire(x)
+      for(e <- elems) {
+        e(w)._1 := e(w)._2
+      }
+      w
+    }
+  }
+}

src/main/scala/hajime/common/HajimeCoreParams.scala

@@ -6,11 +6,10 @@ import chisel3.util._
 // TODO: add inst/data memory info
 // Do I even need multi issue? Vector and Multiply can overlap
 case class HajimeCoreParams(
-  issue_width: Int = 1,
   threads: Int = 1,
   xprlen: Int = 64,
   frequency: Int = 50*1000*1000, // x[MHz] = x * 1000 * 1000
-  physicalRegFileEntries: Int = 48,
+  physicalRegFileEntriesFor1Thread: Int = 48,
   ras_depth: Int = 8,
   robEntries: Int = 8,
   useException: Boolean = true,
@@ -37,6 +36,7 @@ case class HajimeCoreParams(
   vecAluExecUnitNum: Int = 2,
 ) {
   require(isPow2(vlen), s"vlen(${vlen.toString}) is not power of 2. Please read BL Doujinshi for more details.")
+  def physicalRegWidth: Int = log2Up(physicalRegFileEntriesFor1Thread)
   def robTagWidth: Int = log2Up(robEntries)
   def generateDefaultMISA: UInt = {
     Cat((xprlen match {

src/main/scala/hajime/common/InstBundle.scala

@@ -4,6 +4,8 @@ import chisel3._
 import chisel3.util._
 import Functions._
 
+import scala.annotation.unused
+
 class InstBundle(implicit params: HajimeCoreParams) extends Bundle {
   import params._
   val bits: UInt = UInt(32.W)
@@ -14,12 +16,15 @@ class InstBundle(implicit params: HajimeCoreParams) extends Bundle {
   def funct3: UInt    = bits(14,12)
   def rd: UInt        = bits(11,7)
   def opcode: UInt    = bits(6,0)
-  // TODO: refactor to better looking name
-  def i_imm: UInt     = bits(31,20).ext(xprlen)
-  def s_imm: UInt     = Cat(this.funct7, this.rd).ext(xprlen)
-  def b_imm: UInt     = Cat(bits(31), bits(7), bits(30, 25), bits(11,8), 0.U(1.W)).ext(xprlen)
-  def u_imm: UInt     = Cat(bits(31,12), 0.U(12.W)).ext(xprlen)
-  def j_imm: UInt     = Cat(bits(31), bits(19,12), bits(20), bits(30,21), 0.U(1.W)).ext(xprlen)
+  def getImm(immType: ImmediateEnum.Type): UInt = {
+    MuxLookup(immType, 0.U)(Seq(
+      ImmediateEnum.I -> bits(31,20).ext(xprlen),
+      ImmediateEnum.S -> Cat(this.funct7, this.rd).ext(xprlen),
+      ImmediateEnum.B -> Cat(bits(31), bits(7), bits(30, 25), bits(11,8), 0.U(1.W)).ext(xprlen),
+      ImmediateEnum.U -> Cat(bits(31,12), 0.U(12.W)).ext(xprlen),
+      ImmediateEnum.J -> Cat(bits(31), bits(19,12), bits(20), bits(30,21), 0.U(1.W)).ext(xprlen)
+    ))
+  }
   def zimm: UInt      = bits(31,20)
   def uimm19To15: UInt      = Cat(false.B, this.rs1)
   def imm19To15: UInt = this.rs1.ext(xprlen)
@@ -28,6 +33,10 @@ class InstBundle(implicit params: HajimeCoreParams) extends Bundle {
 class ProgramCounter(implicit params: HajimeCoreParams) extends Bundle {
   val addr = UInt(params.xprlen.W)
   def nextPC: UInt = addr + 4.U(params.xprlen.W)
+
+  // C拡張用
+  @unused
+  def nextCompressedPC: UInt = addr + 2.U(params.xprlen.W)
   def initialise(initial: UInt): ProgramCounter = {
     val initalisedWire = Wire(this)
     initalisedWire.addr := initial

src/main/scala/hajime/common/RISCV_Consts.scala → src/main/scala/hajime/common/ScalarOpConstants.scala

@@ -1,12 +1,7 @@
 package hajime.common
 
 import chisel3._
-import chisel3.util._
-import Functions._
-
-object RISCV_Consts {
-  val INST_LEN: Int = 32
-}
+import hajime.common.Functions._
 
 trait ScalarOpConstants {
   object ContentValid extends ChiselEnum {
@@ -67,6 +62,14 @@ trait ScalarOpConstants {
   }
 }
 
+object ImmediateEnum extends ChiselEnum {
+  val I, S, B, U, J = Value
+}
+
+object UseRegisterAs extends ChiselEnum {
+  val NONE, SCALAR, VECTOR = Value
+}
+
 object COMPILE_CONSTANTS {
   val CHISELSTAGE_ARGS = Array("--emission-options=disableMemRandomization,disableRegisterRandomization")
   val FIRTOOLOPS = Array("-disable-all-randomization", "-strip-debug-info", "-add-vivado-ram-address-conflict-synthesis-bug-workaround")

src/main/scala/hajime/publicmodules/ALU.scala

@@ -1,11 +1,10 @@
 package hajime.publicmodules
 
-import circt.stage.ChiselStage
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import hajime.common.RISCV_Consts._
+import hajime.common.Functions._
 import hajime.common._
-import Functions._
 
 class ALUIO(implicit params: HajimeCoreParams) extends Bundle {
   import params._

src/main/scala/hajime/simple4Stage/BranchEvaluator.scala

@@ -20,7 +20,7 @@ class BranchEvaluatorReq(implicit params: HajimeCoreParams) extends Bundle with
 
 class BranchEvaluatorIO(implicit params: HajimeCoreParams) extends Bundle {
   val req = Flipped(new ValidIO(new BranchEvaluatorReq()))
-  val out = new ValidIO(new FrontEndReq())
+  val out = new ValidIO(new ProgramCounter())
 }
 
 class BranchEvaluator(implicit params: HajimeCoreParams) extends Module with ScalarOpConstants {
@@ -47,7 +47,7 @@ class BranchEvaluator(implicit params: HajimeCoreParams) extends Module with Sca
       x => x.asUInt -> (io.req.bits.bp_taken =/= branch_taken)
     )
   )
-  io.out.bits.pc := Mux(io.req.bits.BranchType === Branch.JALR.asUInt, Cat(io.req.bits.ALU_Result.head(params.xprlen-1), false.B), Mux(
+  io.out.bits.addr := Mux(io.req.bits.BranchType === Branch.JALR.asUInt, Cat(io.req.bits.ALU_Result.head(params.xprlen-1), false.B), Mux(
     branch_taken, io.req.bits.destPC, io.req.bits.pc.nextPC
   ))
 }

src/main/scala/hajime/simple4Stage/BranchPredictor.scala

@@ -1,16 +1,15 @@
 package hajime.simple4Stage
 
-import circt.stage.ChiselStage
 import chisel3._
+import circt.stage.ChiselStage
 import chisel3.util._
-import hajime.common.{ScalarOpConstants, _}
-import hajime.common.RISCV_Consts._
+import hajime.common._
 
 class BranchPredictorIO(implicit params: HajimeCoreParams) extends Bundle with ScalarOpConstants {
   // 分岐成立予測であれば，io.out.validはtrue
   // （分岐不成立予測なら単にPC+4を入れるだけ）
   // 分岐先予測はio.out.bits.pc
-  val out = new ValidIO(new FrontEndReq())
+  val out = new ValidIO(new ProgramCounter())
   val pc = Input(new ProgramCounter())
   val imm = Input(UInt(params.xprlen.W))
   val BranchType = Input(UInt(Branch.getWidth.W))
@@ -49,7 +48,7 @@ class BranchPredictor(implicit params: HajimeCoreParams) extends Module with Sca
 
   io.out.valid := branch_predict_taken
   // JALRならばRAS、それ以外はpc+imm (branch, jal)
-  io.out.bits.pc := Mux(io.BranchType === Branch.JALR.asUInt, RAS_pop(), io.pc.addr + io.imm)
+  io.out.bits.addr := Mux(io.BranchType === Branch.JALR.asUInt, RAS_pop(), io.pc.addr + io.imm)
 }
 
 object BranchPredictor extends App {