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code style & unsigned marking serial header files
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@heikokue
heikokue committed Mar 3, 2024
1 parent 3436516 commit fd11d5d
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70 changes: 35 additions & 35 deletions src/class/cdc/serial/ch34x.h
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Expand Up @@ -24,8 +24,8 @@
* This file is part of the TinyUSB stack.
*/

#ifndef _CH34X_H_
#define _CH34X_H_
#ifndef TUSB_CH34X_H
#define TUSB_CH34X_H

// There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found
// - https://github.com/WCHSoftGroup/ch341ser_linux
Expand All @@ -40,45 +40,45 @@
#endif

// USB requests
#define CH34X_REQ_READ_VERSION 0x5F // dec 95
#define CH34X_REQ_WRITE_REG 0x9A // dec 154
#define CH34X_REQ_READ_REG 0x95 // dec 149
#define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161
#define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164
#define CH34X_REQ_READ_VERSION 0x5F // dec 95
#define CH34X_REQ_WRITE_REG 0x9A // dec 154
#define CH34X_REQ_READ_REG 0x95 // dec 149
#define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161
#define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164

// registers
#define CH34X_REG_BREAK 0x05
#define CH34X_REG_PRESCALER 0x12
#define CH34X_REG_DIVISOR 0x13
#define CH34X_REG_LCR 0x18
#define CH34X_REG_LCR2 0x25
#define CH34X_REG_MCR_MSR 0x06
#define CH34X_REG_MCR_MSR2 0x07
#define CH34X_NBREAK_BITS 0x01
#define CH34X_REG_BREAK 0x05
#define CH34X_REG_PRESCALER 0x12
#define CH34X_REG_DIVISOR 0x13
#define CH34X_REG_LCR 0x18
#define CH34X_REG_LCR2 0x25
#define CH34X_REG_MCR_MSR 0x06
#define CH34X_REG_MCR_MSR2 0x07
#define CH34X_NBREAK_BITS 0x01

#define CH341_REG_0x0F 0x0F // undocumented register
#define CH341_REG_0x2C 0x2C // undocumented register
#define CH341_REG_0x27 0x27 // hardware flow control (cts/rts)
#define CH341_REG_0x0F 0x0F // undocumented register
#define CH341_REG_0x2C 0x2C // undocumented register
#define CH341_REG_0x27 0x27 // hardware flow control (cts/rts)

#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
#define CH32X_REG16_LCR2_LCR TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
#define CH32X_REG16_LCR2_LCR TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)

// modem control bits
#define CH34X_BIT_RTS ( 1 << 6 )
#define CH34X_BIT_DTR ( 1 << 5 )
#define CH34X_BIT_RTS (1u << 6)
#define CH34X_BIT_DTR (1u << 5)

// line control bits
#define CH34X_LCR_ENABLE_RX 0x80
#define CH34X_LCR_ENABLE_TX 0x40
#define CH34X_LCR_MARK_SPACE 0x20
#define CH34X_LCR_PAR_EVEN 0x10
#define CH34X_LCR_ENABLE_PAR 0x08
#define CH34X_LCR_PAR_MASK 0x38 // all parity bits
#define CH34X_LCR_STOP_BITS_2 0x04
#define CH34X_LCR_CS8 0x03
#define CH34X_LCR_CS7 0x02
#define CH34X_LCR_CS6 0x01
#define CH34X_LCR_CS5 0x00
#define CH34X_LCR_CS_MASK 0x03 // all CSx bits
#define CH34X_LCR_ENABLE_RX 0x80
#define CH34X_LCR_ENABLE_TX 0x40
#define CH34X_LCR_MARK_SPACE 0x20
#define CH34X_LCR_PAR_EVEN 0x10
#define CH34X_LCR_ENABLE_PAR 0x08
#define CH34X_LCR_PAR_MASK 0x38 // all parity bits
#define CH34X_LCR_STOP_BITS_2 0x04
#define CH34X_LCR_CS8 0x03
#define CH34X_LCR_CS7 0x02
#define CH34X_LCR_CS6 0x01
#define CH34X_LCR_CS5 0x00
#define CH34X_LCR_CS_MASK 0x03 // all CSx bits

#endif /* _CH34X_H_ */
#endif // TUSB_CH34X_H
86 changes: 43 additions & 43 deletions src/class/cdc/serial/cp210x.h
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Expand Up @@ -31,7 +31,7 @@
// parts are overtaken from vendors driver
// https://www.silabs.com/documents/public/software/cp210x-3.1.0.tar.gz

/* Config request codes */
// Config request codes
#define CP210X_IFC_ENABLE 0x00
#define CP210X_SET_BAUDDIV 0x01
#define CP210X_GET_BAUDDIV 0x02
Expand Down Expand Up @@ -60,56 +60,56 @@
#define CP210X_SET_BAUDRATE 0x1E
#define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device

/* SILABSER_IFC_ENABLE_REQUEST_CODE */
#define CP210X_UART_ENABLE 0x0001
#define CP210X_UART_DISABLE 0x0000
// SILABSER_IFC_ENABLE_REQUEST_CODE
#define CP210X_UART_ENABLE 0x0001u
#define CP210X_UART_DISABLE 0x0000u

/* SILABSER_SET_BAUDDIV_REQUEST_CODE */
#define CP210X_BAUD_RATE_GEN_FREQ 0x384000
// SILABSER_SET_BAUDDIV_REQUEST_CODE
#define CP210X_BAUD_RATE_GEN_FREQ 0x384000u

/*SILABSER_SET_LINE_CTL_REQUEST_CODE */
#define CP210X_BITS_DATA_MASK 0x0f00
#define CP210X_BITS_DATA_5 0x0500
#define CP210X_BITS_DATA_6 0x0600
#define CP210X_BITS_DATA_7 0x0700
#define CP210X_BITS_DATA_8 0x0800
#define CP210X_BITS_DATA_9 0x0900
// SILABSER_SET_LINE_CTL_REQUEST_CODE
#define CP210X_BITS_DATA_MASK 0x0f00u
#define CP210X_BITS_DATA_5 0x0500u
#define CP210X_BITS_DATA_6 0x0600u
#define CP210X_BITS_DATA_7 0x0700u
#define CP210X_BITS_DATA_8 0x0800u
#define CP210X_BITS_DATA_9 0x0900u

#define CP210X_BITS_PARITY_MASK 0x00f0
#define CP210X_BITS_PARITY_NONE 0x0000
#define CP210X_BITS_PARITY_ODD 0x0010
#define CP210X_BITS_PARITY_EVEN 0x0020
#define CP210X_BITS_PARITY_MARK 0x0030
#define CP210X_BITS_PARITY_SPACE 0x0040
#define CP210X_BITS_PARITY_MASK 0x00f0u
#define CP210X_BITS_PARITY_NONE 0x0000u
#define CP210X_BITS_PARITY_ODD 0x0010u
#define CP210X_BITS_PARITY_EVEN 0x0020u
#define CP210X_BITS_PARITY_MARK 0x0030u
#define CP210X_BITS_PARITY_SPACE 0x0040u

#define CP210X_BITS_STOP_MASK 0x000f
#define CP210X_BITS_STOP_1 0x0000
#define CP210X_BITS_STOP_1_5 0x0001
#define CP210X_BITS_STOP_2 0x0002
#define CP210X_BITS_STOP_MASK 0x000fu
#define CP210X_BITS_STOP_1 0x0000u
#define CP210X_BITS_STOP_1_5 0x0001u
#define CP210X_BITS_STOP_2 0x0002u

/* SILABSER_SET_BREAK_REQUEST_CODE */
#define CP210X_BREAK_ON 0x0001
#define CP210X_BREAK_OFF 0x0000
// SILABSER_SET_BREAK_REQUEST_CODE
#define CP210X_BREAK_ON 0x0001u
#define CP210X_BREAK_OFF 0x0000u

/* SILABSER_SET_MHS_REQUEST_CODE */
#define CP210X_MCR_DTR 0x0001
#define CP210X_MCR_RTS 0x0002
#define CP210X_MCR_ALL 0x0003
#define CP210X_MSR_CTS 0x0010
#define CP210X_MSR_DSR 0x0020
#define CP210X_MSR_RING 0x0040
#define CP210X_MSR_DCD 0x0080
#define CP210X_MSR_ALL 0x00F0
// SILABSER_SET_MHS_REQUEST_CODE
#define CP210X_MCR_DTR 0x0001u
#define CP210X_MCR_RTS 0x0002u
#define CP210X_MCR_ALL 0x0003u
#define CP210X_MSR_CTS 0x0010u
#define CP210X_MSR_DSR 0x0020u
#define CP210X_MSR_RING 0x0040u
#define CP210X_MSR_DCD 0x0080u
#define CP210X_MSR_ALL 0x00F0u

#define CP210X_CONTROL_WRITE_DTR 0x0100
#define CP210X_CONTROL_WRITE_RTS 0x0200
#define CP210X_CONTROL_WRITE_DTR 0x0100u
#define CP210X_CONTROL_WRITE_RTS 0x0200u

#define CP210X_LSR_BREAK 0x0001
#define CP210X_LSR_FRAMING_ERROR 0x0002
#define CP210X_LSR_HW_OVERRUN 0x0004
#define CP210X_LSR_QUEUE_OVERRUN 0x0008
#define CP210X_LSR_PARITY_ERROR 0x0010
#define CP210X_LSR_ALL 0x001F
#define CP210X_LSR_BREAK 0x0001u
#define CP210X_LSR_FRAMING_ERROR 0x0002u
#define CP210X_LSR_HW_OVERRUN 0x0004u
#define CP210X_LSR_QUEUE_OVERRUN 0x0008u
#define CP210X_LSR_PARITY_ERROR 0x0010u
#define CP210X_LSR_ALL 0x001Fu

// supported baudrates
// reference: datasheets and AN205 "CP210x Baud Rate Support"
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