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JonathSpirit · May 23, 2020 · f98e455 · f98e455
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diff --git a/ALUGP8B.xise b/ALUGP8B.xise
diff --git a/_pace.ucf b/_pace.ucf
@@ -0,0 +1,44 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "clkNumLeft"  LOC = "P22" | BUFG = CLK ; 
+NET "clkNumRight"  LOC = "P23" | BUFG = CLK ; 
+NET "clkOpChoose"  LOC = "P27" | BUFG = CLK ; 
+NET "numLeft<0>"  LOC = "P11"  ; 
+NET "numLeft<1>"  LOC = "P12"  ; 
+NET "numLeft<2>"  LOC = "P13"  ; 
+NET "numLeft<3>"  LOC = "P14"  ; 
+NET "numLeft<4>"  LOC = "P15"  ; 
+NET "numLeft<5>"  LOC = "P16"  ; 
+NET "numLeft<6>"  LOC = "P17"  ; 
+NET "numLeft<7>"  LOC = "P18"  ; 
+NET "numRight<0>"  LOC = "P99"  ; 
+NET "numRight<1>"  LOC = "P1"  ; 
+NET "numRight<2>"  LOC = "P2"  ; 
+NET "numRight<3>"  LOC = "P3"  ; 
+NET "numRight<4>"  LOC = "P4"  ; 
+NET "numRight<5>"  LOC = "P6"  ; 
+NET "numRight<6>"  LOC = "P7"  ; 
+NET "numRight<7>"  LOC = "P8"  ; 
+NET "opChoose<0>"  LOC = "P87"  ; 
+NET "opChoose<1>"  LOC = "P89"  ; 
+NET "opChoose<2>"  LOC = "P90"  ; 
+NET "opChoose<3>"  LOC = "P91"  ; 
+NET "opChoose<4>"  LOC = "P92"  ; 
+NET "opChoose<5>"  LOC = "P93"  ; 
+NET "opChoose<6>"  LOC = "P94"  ; 
+NET "opChoose<7>"  LOC = "P95"  ; 
+NET "result<0>"  LOC = "P35"  ; 
+NET "result<1>"  LOC = "P36"  ; 
+NET "result<2>"  LOC = "P37"  ; 
+NET "result<3>"  LOC = "P39"  ; 
+NET "result<4>"  LOC = "P40"  ; 
+NET "result<5>"  LOC = "P41"  ; 
+NET "result<6>"  LOC = "P42"  ; 
+NET "result<7>"  LOC = "P43"  ; 
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/fuse.log b/fuse.log
@@ -0,0 +1,42 @@
+Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib uni9000_ver -lib aim_ver -lib cpld_ver -lib xilinxcorelib_ver -o C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_isim_beh.exe -prj C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_beh.prj work.testbench work.glbl 
+ISim P.20131013 (signature 0x7708f090)
+Number of CPUs detected in this system: 8
+Turning on mult-threading, number of parallel sub-compilation jobs: 16 
+Determining compilation order of HDL files
+Analyzing Verilog file "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/main.v" into library work
+Analyzing Verilog file "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench.v" into library work
+Analyzing Verilog file "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
+Starting static elaboration
+WARNING:HDLCompiler:189 - "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/main.v" Line 250: Size mismatch in connection of port <r>. Formal port size is 3-bit while actual signal size is 8-bit.
+WARNING:HDLCompiler:189 - "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/main.v" Line 252: Size mismatch in connection of port <r>. Formal port size is 3-bit while actual signal size is 8-bit.
+Completed static elaboration
+Compiling module RisingEdge_DFlipFlop8bit
+Compiling module unsigned_8bitAdder
+Compiling module unsigned_8bitSubstract
+Compiling module op_8bitAndBitwise
+Compiling module op_8bitOrBitwise
+Compiling module op_8bitXorBitwise
+Compiling module op_8bitAnd
+Compiling module op_8bitOr
+Compiling module op_8bitXor
+Compiling module op_8bitShiftR
+Compiling module op_8bitShiftL
+Compiling module op_8bitSBigger
+Compiling module op_8bitSSmaller
+Compiling module op_8bitBigger
+Compiling module op_8bitSmaller
+Compiling module op_8bitEqual
+Compiling module op_8bitInvertBitwise
+Compiling module op_8bitInvert
+Compiling module unsigned_8bitMult
+Compiling module op_8bit2Complement
+Compiling module op_8bitRotate
+Compiling module main
+Compiling module testbench
+Compiling module glbl
+Time Resolution for simulation is 1ps.
+Waiting for 9 sub-compilation(s) to finish...
+Compiled 24 Verilog Units
+Built simulation executable C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_isim_beh.exe
+Fuse Memory Usage: 28508 KB
+Fuse CPU Usage: 515 ms
diff --git a/fuse.xmsgs b/fuse.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/main.v" Line 250: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">r</arg>&gt;. Formal port size is <arg fmt="%d" index="2">3</arg>-bit while actual signal size is <arg fmt="%d" index="1">8</arg>-bit.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/main.v" Line 252: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">r</arg>&gt;. Formal port size is <arg fmt="%d" index="2">3</arg>-bit while actual signal size is <arg fmt="%d" index="1">8</arg>-bit.
+</msg>
+
+</messages>
+
diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd
@@ -0,0 +1 @@
+-intstyle "ise" -incremental -lib "uni9000_ver" -lib "aim_ver" -lib "cpld_ver" -lib "xilinxcorelib_ver" -o "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_isim_beh.exe" -prj "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_beh.prj" "work.testbench" "work.glbl" 
diff --git a/isim.cmd b/isim.cmd
@@ -0,0 +1,3 @@
+onerror {resume}
+wave add /
+run 1000 ns;
diff --git a/isim.log b/isim.log
@@ -0,0 +1,15 @@
+ISim log file
+Running: C:\Users\guill\Desktop\Creation\electronique\Xilinx\ALUGP8B\testbench_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_isim_beh.wdb 
+ISim P.20131013 (signature 0x7708f090)
+WARNING: A WEBPACK license was found.
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
+This is a Lite version of ISim.
+WARNING: File "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/main.v" Line 225.  For instance uut/shiftR/, width 3 of formal port r is not equal to width 8 of actual signal numRightReg.
+WARNING: File "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/main.v" Line 225.  For instance uut/shiftL/, width 3 of formal port r is not equal to width 8 of actual signal numRightReg.
+Time resolution is 1 ps
+# onerror resume
+# wave add /
+# run 1000 ns
+Simulator is doing circuit initialization process.
+Finished circuit initialization process.
diff --git a/isim/isim_usage_statistics.html b/isim/isim_usage_statistics.html
@@ -0,0 +1,16 @@
+<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="ISimStatistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
+<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value></xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>515 ms, 28508 KB</xtag-isim-property-value></TD></TR>
+
+<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>105</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>232</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>26</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>48</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.640625 sec, 5317988 KB</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
+</xtag-section>
+</TABLE>
diff --git a/isim/pn_info b/isim/pn_info
@@ -0,0 +1 @@
+14.7
diff --git a/isim/temp/@rising@edge_@d@[email protected] b/isim/temp/@rising@edge_@d@[email protected]
diff --git a/isim/temp/glbl.sdb b/isim/temp/glbl.sdb
diff --git a/isim/temp/main.sdb b/isim/temp/main.sdb
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/op_8bit@[email protected] b/isim/temp/op_8bit@[email protected]
diff --git a/isim/temp/testbench.sdb b/isim/temp/testbench.sdb
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/temp/[email protected] b/isim/temp/[email protected]
diff --git a/isim/testbench_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/testbench_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
diff --git a/isim/testbench_isim_beh.exe.sim/isimcrash.log b/isim/testbench_isim_beh.exe.sim/isimcrash.log
diff --git a/isim/testbench_isim_beh.exe.sim/isimkernel.log b/isim/testbench_isim_beh.exe.sim/isimkernel.log
@@ -0,0 +1,29 @@
+Command line:
+   testbench_isim_beh.exe
+     -simmode  gui
+     -simrunnum  0
+     -socket  65317
+
+Sun Aug 25 18:35:49 2019
+
+
+ Elaboration Time: 0.1875 sec
+
+ Current Memory Usage: 5814.95 Meg
+
+ Total Signals          : 105
+ Total Nets             : 232
+ Total Signal Drivers   : 42
+ Total Blocks           : 26
+ Total Primitive Blocks : 24
+ Total Processes        : 48
+ Total Traceable Variables  : 28
+ Total Scalar Nets and Variables : 371
+Total Line Count : 92
+
+ Total Simulation Time: 0.640625 sec
+
+ Current Memory Usage: 5343.06 Meg
+
+Sun Aug 25 18:37:44 2019
+
diff --git a/isim/testbench_isim_beh.exe.sim/libPortability.dll b/isim/testbench_isim_beh.exe.sim/libPortability.dll
diff --git a/isim/testbench_isim_beh.exe.sim/netId.dat b/isim/testbench_isim_beh.exe.sim/netId.dat
diff --git a/isim/testbench_isim_beh.exe.sim/testbench_isim_beh.exe b/isim/testbench_isim_beh.exe.sim/testbench_isim_beh.exe
diff --git a/isim/testbench_isim_beh.exe.sim/tmp_save/_1 b/isim/testbench_isim_beh.exe.sim/tmp_save/_1
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		-intstyle "ise" -incremental -lib "uni9000_ver" -lib "aim_ver" -lib "cpld_ver" -lib "xilinxcorelib_ver" -o "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_isim_beh.exe" -prj "C:/Users/guill/Desktop/Creation/electronique/Xilinx/ALUGP8B/testbench_beh.prj" "work.testbench" "work.glbl"