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Issues: Juniper/open-register-design-tool
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Sticky interrupt with hardware precedence and write-one-to-clear can not be cleared
#87
opened Dec 15, 2020 by
tenaliram
addressing and alignment properties of addressmap not being followed
#85
opened Aug 25, 2020 by
tenaliram
When there is a secondary processor, decoder logic is out of sync.
#81
opened Apr 14, 2020 by
kongty
Is there an option to enable address channel for each write and read, instead of one address channel?
#80
opened Apr 10, 2020 by
kongty
Is there an option to enable or disable the flopping of inputs and/or outputs to the RTL generated?
#75
opened Oct 18, 2019 by
neenuprince
RTl code has floating signals for HWRead SWwrite registers causing X's
#70
opened Jul 18, 2019 by
neenuprince
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