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_posts/2024-10-13-coa-two.md

@@ -144,10 +144,11 @@ As for the 24-bit address, it is seperated into 12 bits of tag, 10 bits of set n
 - **Word**: 4 bits
 
 **Line Structure:**
-Different from normal cache line, it includes 21 bits of tag and a single “line valid bit” and three bits, B0, B1, and B2 (the “LRU” bits), and 16 bytes of data.
+Different from normal cache line, it includes 21 bits of tag and a single “line valid bit” and three bits, B0, B1, and B2 (the “LRU” bits), and 16 bytes of data. Note that only when the line valid bit is 1, the content of the line is valid.
 
 {: .box-note}
 **Question 4.8**:Consider a machine with a byte addressable main memory of 64K bytes and block size of 8 bytes. Assume that a **direct-mapped cache consisting of 32 lines** is used with the machine. Answer the following questions:
+
 {: .box-note}
 
 - How is a 16-bit memory address divided into tag, line, and byte number?
@@ -181,6 +182,10 @@ Different from normal cache line, it includes 21 bits of tag and a single “lin
 - `0001 1010 0001 1001`
 - `0001 1010 0001 1010`(self)
 - `0001 1010 0001 1011`
+- `0001 1010 0001 1100`
+- `0001 1010 0001 1101`
+- `0001 1010 0001 1110`
+- `0001 1010 0001 1111`
 
 **Question D**:The total number of bytes that can be stored in the cache is: