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Logic #82
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added extra parts
added more parts
changed body line width to .254
adjusted gate pin names fixed XOR symbols changed create date
resynced uuids to Logic lib repo
Now fully generates LibrePCB_Logic.lplib repo
added entities/component.py with added gates method
dbrgn
reviewed
Mar 31, 2020
PIN,B,L,-6.00,-2.00,0 | ||
PIN,OUT,R,6.00,0,0 | ||
TEXT,-4.00,3.00,NAME | ||
TEXT,-4.00,-3.00,VALUE |
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Hello @ouabache. Where did you get this data from?
Hi Danilo,
I created a csv file for each symbol and use a python script to generate
the symbol. They are currently hand crafted but I am working on another
script to read LibrePCB files and extract their data into csv files.
That way when the file formats change we can rewrite the script and
regenerate the entire library.
The distances are given in snap grid units so it is easy to generate either
metric or english. I have a scale factor so if I want to make another gate
at half size I can copy the file, change the name and scale factor and
generate a new gate. You have to manually tweak the pads since the hot
spots must remain on a 2.54 mm grid.
The scripts that I checked into librepcb-parts-generator were used to
create all the gates I checked into LibrePCB_ICs.lplib.
John Eaton
…On Mon, Mar 30, 2020 at 11:50 PM Danilo Bargen ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In Logic/Logic/AND2_4.csv
<#82 (comment)>
:
> +POLYPT,-6.00,2.00,0
+POLYPT,-4.00,2.00,0
+POLYST
+POLY,.0622,N
+POLYPT,-6.00,-2.00,0
+POLYPT,-4.00,-2.00,0
+POLYST
+POLY,.0622,N
+POLYPT,6.00,0,0
+POLYPT,4.00,0,0
+POLYST
+PIN,A,L,-6.00,2.00,0
+PIN,B,L,-6.00,-2.00,0
+PIN,OUT,R,6.00,0,0
+TEXT,-4.00,3.00,NAME
+TEXT,-4.00,-3.00,VALUE
Hello @ouabache <https://github.com/ouabache>. Where did you get this
data from?
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Digital logic primitives sized at 1/4 scale